Texas Instruments ADS1274 User manual

VREFP VREFN AVDD DVDD
TEST[1:0]
FORMAT[2:0]
CLK
SYNC
PWDN[8:1]
CLKDIV
Control
Logic
SPI
and
Frame-
Sync
Interface
IOVDD
DGNDAGND
DRDY/FSYNC
SCLK
DOUT[8:1]
DIN
Input2
Input1
Input4
Input3
Input6
Input5
Input8
Input7
DS
DS
DS
DS
DS
DS
DS
DS
PWDN[4:1]
ADS1278
Four
Digital
Filters
AVDD DVDD
TEST[1:0]
FORMAT[2:0]
CLK
SYNC
CLKDIV
Control
Logic
SPI
and
Frame-
Sync
Interface
IOVDD
DGNDAGND
DRDY/FSYNC
SCLK
DOUT[4:1]
DIN
ADS1274
MODE[1:0]
MODE[1:0]
Eight
Digital
Filters
VREFP VREFN
Input2
Input1
Input4
Input3
DS
DS
DS
DS
ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters
Check for Samples: ADS1274,ADS1278
1FEATURES DESCRIPTION
234•Simultaneously Measure Four/Eight Channels Based on the single-channel ADS1271, the ADS1274
(quad) and ADS1278 (octal) are 24-bit, delta-sigma
•Up to 144kSPS Data Rate (ΔΣ) analog-to-digital converters (ADCs) with data
•AC Performance: rates up to 144k samples per second (SPS), allowing
70kHz Bandwidth simultaneous sampling of four or eight channels. The
111dB SNR (High-Resolution Mode) devices are offered in identical packages, permitting
–108dB THD drop-in expandability.
•DC Accuracy: Traditionally, industrial delta-sigma ADCs offering
0.8μV/°C Offset Drift good drift performance use digital filters with large
1.3ppm/°C Gain Drift passband droop. As a result, they have limited signal
•Selectable Operating Modes: bandwidth and are mostly suited for dc
High-Speed: 144kSPS, 106dB SNR measurements. High-resolution ADCs in audio
applications offer larger usable bandwidths, but the
High-Resolution: 52kSPS, 111dB SNR offset and drift specifications are significantly weaker
Low-Power: 52kSPS, 31mW/ch than respective industrial counterparts. The ADS1274
Low-Speed: 10kSPS, 7mW/ch and ADS1278 combine these types of converters,
•Linear Phase Digital Filter allowing high-precision industrial measurement with
•SPI™or Frame-Sync Serial Interface excellent dc and ac specifications.
•Low Sampling Aperture Error The high-order, chopper-stabilized modulator
•Modulator Output Option (digital filter bypass) achieves very low drift with low in-band noise. The
onboard decimation filter suppresses modulator and
•Analog Supply: 5V signal out-of-band noise. These ADCs provide a
•Digital Core: 1.8V usable signal bandwidth up to 90% of the Nyquist
•I/O Supply: 1.8V to 3.3V rate with less than 0.005dB of ripple.
Four operating modes allow for optimization of speed,
APPLICATIONS resolution, and power. All operations are controlled
•Vibration/Modal Analysis directly by pins; there are no registers to program.
•Multi-Channel Data Acquisition The devices are fully specified over the extended
industrial range (–40°C to +105°C) and are available
•Acoustics/Dynamic Strain Gauges in an HTQFP-64 PowerPAD™package.
•Pressure Sensors
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments, Inc.
3SPI is a trademark of Motorola, Inc.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. ©2007–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted(1)
ADS1274, ADS1278 UNIT
AVDD to AGND –0.3 to +6.0 V
DVDD, IOVDD to DGND –0.3 to +3.6 V
AGND to DGND –0.3 to +0.3 V
Momentary 100 mA
Input current Continuous 10 mA
Analog input to AGND –0.3 to AVDD + 0.3 V
Digital input or output to DGND –0.3 to IOVDD + 0.3 V
Maximum junction temperature +150 °C
ADS1274 –40 to +125 °C
Operating temperature range ADS1278 –40 to +105 °C
Storage temperature range –60 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS
All specifications at TA=–40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted. ADS1274, ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale input voltage (FSR(1)) VIN = (AINP –AINN) ±VREF V
Absolute input voltage AINP or AINN to AGND AGND –0.1 AVDD + 0.1 V
Common-mode input voltage (VCM) VCM = (AINP + AINN)/2 2.5 V
High-Speed mode 14 kΩ
High-Resolution mode 14 kΩ
Differential input impedance Low-Power mode 28 kΩ
Low-Speed mode 140 kΩ
DC PERFORMANCE
Resolution No missing codes 24 Bits
fCLK = 37MHz 144,531 SPS(3)
High-Speed mode(2) fCLK = 32.768MHz 128,000 SPS
fCLK = 27MHz 105,469 SPS
Data rate (fDATA)High-Resolution mode 52,734 SPS
Low-Power mode 52,734 SPS
Low-Speed mode 10,547 SPS
Integral nonlinearity (INL)(4) Differential input, VCM = 2.5V ±0.0003 ±0.0012 % FSR(1)
Offset error 0.25 2 mV
Offset drift 0.8 μV/°C
Gain error 0.1 0.5 % FSR
Gain drift 1.3 ppm/°C
High-Speed mode Shorted input 8.5 16 μV, rms
High-Resolution mode Shorted input 5.5 12 μV, rms
Noise Low-Power mode Shorted input 8.5 16 μV, rms
Low-Speed mode Shorted input 8.0 16 μV, rms
Common-mode rejection fCM = 60Hz 90 108 dB
AVDD 80 dB
Power-supply rejection DVDD fPS = 60Hz 85 dB
IOVDD 105 dB
VCOM output voltage No load AVDD/2 V
(1) FSR = full-scale range = 2VREF.
(2) fCLK = 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for fCLK restrictions in High-Speed mode.
(3) SPS = samples per second.
(4) Best fit method.
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ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA=–40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted. ADS1274, ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
Crosstalk f = 1kHz, –0.5dBFS(5) –107 dB
High-Speed mode 101 106 dB
VREF = 2.5V 103 110 dB
High-Resolution mode
Signal-to-noise ratio (SNR)(6) VREF = 3V 111 dB
(unweighted) Low-Power mode 101 106 dB
Low-Speed mode 101 107 dB
Total harmonic distortion (THD)(7) VIN = 1kHz, –0.5dBFS –108 –96 dB
Spurious-free dynamic range 109 dB
Passband ripple ±0.005 dB
Passband 0.453 fDATA Hz
–3dB Bandwidth 0.49 fDATA Hz
High-Resolution mode 95 dB
Stop band attenuation All other modes 100
High-Resolution mode 0.547 fDATA 127.453 fDATA Hz
Stop band All other modes 0.547 fDATA 63.453 fDATA Hz
High-Resolution mode 39/fDATA s
Group delay All other modes 38/fDATA s
High-Resolution mode Complete settling 78/fDATA s
Settling time (latency) All other modes Complete settling 76/fDATA s
VOLTAGE REFERENCE INPUTS
Negative reference input (VREFN) AGND –0.1 AGND + 0.1 V
0.1 ≤fCLK ≤27MHz 0.5 2.5 3.1 V
Reference input voltage (VREF)(8) 27 <fCLK ≤32.768MHz 0.5 2.5 2.6 V
(VREF = VREFP –VREFN) 32.768MHz <fCLK ≤37MHz 0.5 2.048 2.1 V
High-Speed mode 1.3 kΩ
High-Resolution mode 1.3 kΩ
ADS1274
Reference Input impedance Low-Power mode 2.6 kΩ
Low-Speed mode 13 kΩ
High-Speed mode 0.65 kΩ
High-Resolution mode 0.65 kΩ
ADS1278
Reference Input impedance Low-Power mode 1.3 kΩ
Low-Speed mode 6.5 kΩ
DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)
VIH 0.7 IOVDD IOVDD V
VIL DGND 0.3 IOVDD V
VOH IOH = 4mA 0.8 IOVDD IOVDD V
VOL IOL = 4mA DGND 0.2 IOVDD V
Input leakage 0 <VIN DIGITAL <IOVDD ±10 μA
High-Speed mode(8) 0.1 37 MHz
Master clock rate (fCLK)Other modes 0.1 27 MHz
(5) Worst-case channel crosstalk between one or more channels.
(6) Minimum SNR is ensured by the limit of the DC noise specification.
(7) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
(8) fCLK = 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for VREF restrictions in High-Speed mode.
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ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA=–40°C to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted. ADS1274, ADS1278
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
AVDD 4.75 5 5.25 V
0.1 ≤fCLK ≤32.768MHz 1.65 1.8 1.95 V
DVDD(9) 32.768MHz <fCLK ≤37MHz 2.0 2.1 2.2 V
IOVDD 1.65 3.6 V
AVDD 1 10 μA
Power-down current DVDD 1 15 μA
IOVDD 1 10 μA
ADS1274
High-Speed mode 50 75 mA
High-Resolution mode 50 75 mA
ADS1274
AVDD current Low-Power mode 23 35 mA
Low-Speed mode 5 9 mA
High-Speed mode 18 24 mA
High-Resolution mode 12 17 mA
ADS1274
DVDD current Low-Power mode 10 15 mA
Low-Speed mode 2.5 4.5 mA
High-Speed mode 0.15 0.5 mA
High-Resolution mode 0.075 0.3 mA
ADS1274
IOVDD current Low-Power mode 0.075 0.3 mA
Low-Speed mode 0.02 0.15 mA
High-Speed mode 285 420 mW
High-Resolution mode 275 410 mW
ADS1274
Power dissipation Low-Power mode 135 210 mW
Low-Speed mode 30 55 mW
ADS1278
High-Speed mode 97 145 mA
High-Resolution mode 97 145 mA
ADS1278
AVDD current Low-Power mode 44 64 mA
Low-Speed mode 9 14 mA
High-Speed mode 23 30 mA
High-Resolution mode 16 20 mA
ADS1278
DVDD current Low-Power mode 12 17 mA
Low-Speed mode 2.5 4.5 mA
High-Speed mode 0.25 1 mA
High-Resolution mode 0.125 0.5 mA
ADS1278
IOVDD current Low-Power mode 0.125 0.5 mA
Low-Speed mode 0.035 0.2 mA
High-Speed mode 530 785 mW
High-Resolution mode 515 765 mW
ADS1278
Power dissipation Low-Power mode 245 355 mW
Low-Speed mode 50 80 mW
(9) fCLK = 37MHz max for High-Speed mode, and 27MHz max for all other modes. See Table 7 for DVDD restrictions in High-Speed mode.
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AINN7(1)
AINP7(1)
AINN8(1)
AINP8(1)
AVDD
AGND
PWDN1
PWDN2
PWDN3
PWDN4
PWDN5(1)
PWDN6(1)
PWDN7(1)
PWDN8(1)
MODE0
MODE1
AINP2
AINN2
AINP1
AINN1
AVDD
AGND
DGND
TEST0
TEST1
CLKDIV
SYNC
DIN
DOUT8(1)
DOUT7(1)
DOUT6(1)
DOUT5(1)
AINN3 AINP3 AINN4 AINP4
AVDD
AGND
VREFN VREFP VCOM
AGND AVDD
AINP5(1)
AINN6(1)
AINP6(1)
AINN5(1)
DOUT4
DOUT3
DOUT2
DOUT1
DGND
IOVDD IOVDD
DGND
DGND
DVDD
CLK
SCLK
DRDY/FSYNC
FORMAT2
FORMAT1
FORMAT0
ADS1274/ADS1278
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(PowerPAD Outline)
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
ADS1274/ADS1278 PIN ASSIGNMENTS
PAP PACKAGE
HTQFP-64
(TOP VIEW)
(1) Boldface pin names indicate additional pins for the ADS1278; see Table 1.
Table 1. ADS1274/ADS1278 PIN DESCRIPTIONS
PIN
NAME NO. FUNCTION DESCRIPTION
6, 43, 54,
AGND Analog ground Analog ground; connect to DGND using a single plane.
58, 59
AINP1 3 Analog input
AINP2 1 Analog input
AINP3 63 Analog input ADS1278: AINP[8:1] Positive analog input, channels 8 through 1.
AINP4 61 Analog input
AINP5 51 Analog input ADS1274: AINP[8:5] Connected to internal ESD rails. The inputs may float.
AINP[4:1] Positive analog input, channels 4 through 1.
AINP6 49 Analog input
AINP7 47 Analog input
AINP8 45 Analog input
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ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
Table 1. ADS1274/ADS1278 PIN DESCRIPTIONS (continued)
PIN
NAME NO. FUNCTION DESCRIPTION
AINN1 4 Analog input
AINN2 2 Analog input
AINN3 64 Analog input ADS1278: AINN[8:1] Negative analog input, channels 8 through 1.
AINN4 62 Analog input
AINN5 52 Analog input ADS1274: AINN[8:5] Connected to internal ESD rails. The inputs may float.
AINN[4:1] Negative analog input, channels 4 through 1.
AINN6 50 Analog input
AINN7 48 Analog input
AINN8 46 Analog input
AVDD 5, 44, 53, 60 Analog power supply Analog power supply (4.75V to 5.25V).
VCOM 55 Analog output AVDD/2 Unbuffered voltage output.
VREFN 57 Analog input Negative reference input.
VREFP 56 Analog input Positive reference input.
CLK 27 Digital input Master clock input (fCLK).
CLK input divider control: 1 = 37MHz (High-Speed mode)/otherwise 27MHz
CLKDIV 10 Digital input 0 = 13.5MHz (low-power)/5.4MHz (low-speed)
DGND 7, 21, 24, 25 Digital ground Digital ground power supply.
DIN 12 Digital input Daisy-chain data input.
DOUT1 20 Digital output DOUT1 is TDM data output (TDM mode).
DOUT2 19 Digital output
DOUT3 18 Digital output ADS1278: DOUT[8:1] Data output for channels 8 through 1.
DOUT4 17 Digital output
DOUT5 16 Digital output ADS1274: DOUT[8:5] Internally connected to active circuitry; outputs are
driven.
DOUT6 15 Digital output DOUT[4:1] Data output for channels 4 through 1.
DOUT7 14 Digital output
DOUT8 13 Digital output
DRDY/ 29 Digital input/output Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
FSYNC
DVDD 26 Digital power supply Digital core power supply.
FORMAT0 32 Digital input FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs,
FORMAT1 31 Digital input fixed/dynamic position TDM data, and modulator mode/normal operating mode.
FORMAT2 30 Digital input
IOVDD 22, 23 Digital power supply I/O power supply (+1.65V to +3.6V).
MODE0 34 Digital input MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed
mode operation.
MODE1 33 Digital input
PWDN1 42 Digital input
PWDN2 41 Digital input
PWDN3 40 Digital input ADS1278: PWDN[8:1] Power-down control for channels 8 through 1.
PWDN4 39 Digital input
PWDN5 38 Digital input ADS1274: PWDN[8:5] must = 0V.
PWDN[4:1] Power-down control for channels 4 through 1.
PWDN6 37 Digital input
PWDN7 36 Digital input
PWDN8 35 Digital input
SCLK 28 Digital input/output Serial clock input, Modulator clock output.
SYNC 11 Digital input Synchronize input (all channels).
TEST0 8 Digital input TEST[1:0] Test mode select: 01 = Do not use
00 = Normal operation 10 = Do not use
11 = Test mode
TEST1 9 Digital input
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CLK
tCPW
tCLK
tCPW
tSD tSCLK
tDIST
tDOHD
tSPW
Bit 23 (MSB) Bit 22 Bit 21
tSPW tDOPD
tCD
tDS
tMSBPD
tDIHD
· · ·
tCONV
DRDY
SCLK
DOUT
DIN
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
SPI FORMAT TIMING
SPI FORMAT TIMING SPECIFICATION
For TA=–40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V, unless otherwise noted.
SYMBOL PARAMETER MIN TYP MAX UNIT
tCLK CLK period (1/fCLK)(1) 37 10,000 ns
tCPW CLK positive or negative pulse width 15 ns
tCONV Conversion period (1/fDATA)(2) 256 2560 tCLK
tCD(3) Falling edge of CLK to falling edge of DRDY 22 ns
tDS(3) Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 tCLK
tMSBPD DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns
tSD(3) Falling edge of SCLK to rising edge of DRDY 18 ns
tSCLK(4) SCLK period 1 tCLK
tSPW SCLK positive or negative pulse width 0.4 tCLK
tDOHD(3)(5) SCLK falling edge to new DOUT invalid (hold time) 10 ns
32 ns
tDOPD(3) SCLK falling edge to new DOUT valid (propagation delay) 26 ns(6)
tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns
tDIHD(5) Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1) fCLK = 27MHz maximum.
(2) Depends on MODE[1:0] and CLKDIV selection. See Table 8 (fCLK/fDATA).
(3) Load on DRDY and DOUT = 20pF.
(4) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.
(5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.
(6) DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 1.7V to 1.9V.
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SCLK
FSYNC
DOUT
DIN
tDOHD
tFPW
tSCLK tSF tSPW
tSPW
tFRAME
tFPW
tFS
tDIHD
tMSBPD
tDIST
Bit 23 (MSB) Bit 22 Bit 21
tDOPD
CLK
tCPW
tCPW
tCS
tCLK
ADS1274
ADS1278
www.ti.com SBAS367F –JUNE 2007–REVISED FEBRUARY 2011
FRAME-SYNC FORMAT TIMING
FRAME-SYNC FORMAT TIMING SPECIFICATION
For TA=–40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 2.2V, unless otherwise noted.
SYMBOL PARAMETER MIN TYP MAX UNIT
High-Speed mode 27 10,000 ns
tCLK CLK period (1/fCLK) (see Table 7)Other modes 37 10,000 ns
tCPW CLK positive or negative pulse width 11 ns
tCS Falling edge of CLK to falling edge of SCLK –0.25 0.25 tCLK
tFRAME Frame period (1/fDATA)(1) 256 2560 tCLK
tFPW FSYNC positive or negative pulse width 1 tSCLK
tFS Rising edge of FSYNC to rising edge of SCLK 5 ns
tSF Rising edge of SCLK to rising edge of FSYNC 5 ns
tSCLK SCLK period(2) 1 tCLK
tSPW SCLK positive or negative pulse width 0.4 tCLK
tDOHD(3)(4) SCLK falling edge to old DOUT invalid (hold time) 10 ns
31 ns
tDOPD(4) SCLK falling edge to new DOUT valid (propagation delay) 21 ns(5)
25 ns(6)
31 ns
tMSBPD FSYNC rising edge to DOUT MSB valid (propagation delay) 21 ns(5)
25 ns(6)
tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns
tDIHD(3) Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1) Depends on MODE[1:0] and CLKDIV selection. See Table 8 (fCLK/fDATA).
(2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK.
(3) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.
(4) Load on DOUT = 20pF.
(5) DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 2V to 2.2V.
(6) DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 1.7V to 1.9V.
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10 100 1k
Frequency (Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
Amplitude (dB)
10k 100k
High-Speed Mode
f = 1kHz, 0.5dBFS-
IN
32,768 Points
10 100 1k
Frequency (Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
Amplitude (dB)
10k 100k
High-Speed Mode
f = 1kHz, 20dBFS-
IN
32,768 Points
1 10 100 1k
Frequency (Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
Amplitude (dB)
10k 100k
High-Speed Mode
Shorted Input
262,144 Points
-35 -28 -21 -14
-7
0 7
14 21 28 35
Output ( V)m
25k
20k
15k
10k
5k
0
Number of Occurrences
High-Speed Mode
Shorted Input
262,144 Points
10 100 1k
Frequency (Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
Amplitude (dB)
10k 100k
High-Resolution Mode
f = 1kHz, 0.5dBFS-
IN
32,768 Points
10 100 1k
Frequency (Hz)
0
-20
-40
-60
-80
-100
-120
-140
-160
Amplitude (dB)
10k 100k
High-Resolution Mode
f = 1kHz, 20dBFS-
IN
32,768 Points
ADS1274
ADS1278
SBAS367F –JUNE 2007–REVISED FEBRUARY 2011 www.ti.com
TYPICAL CHARACTERISTICS
At TA= +25°C, High-Speed mode, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, fCLK = 27MHz, VREFP = 2.5V, and
VREFN = 0V, unless otherwise noted.
OUTPUT SPECTRUM OUTPUT SPECTRUM
Figure 1. Figure 2.
OUTPUT SPECTRUM NOISE HISTOGRAM
Figure 3. Figure 4.
OUTPUT SPECTRUM OUTPUT SPECTRUM
Figure 5. Figure 6.
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