Texas Instruments TPS54320 User manual

User’s Guide
TPS54320 Step-Down Converter Evaluation Module User's
Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Background........................................................................................................................................................................ 2
1.2 Performance Specification Summary.................................................................................................................................2
1.3 Modifications...................................................................................................................................................................... 3
2 Test Setup and Results.......................................................................................................................................................... 4
2.1 Input / Output Connections................................................................................................................................................ 4
2.2 Efficiency............................................................................................................................................................................5
2.3 Output Voltage Load Regulation........................................................................................................................................ 6
2.4 Output Voltage Line Regulation......................................................................................................................................... 6
2.5 Load Transients..................................................................................................................................................................7
2.6 Loop Characteristics.......................................................................................................................................................... 7
2.7 Output Voltage Ripple........................................................................................................................................................ 8
2.8 Input Voltage Ripple........................................................................................................................................................... 8
2.9 Powering Up.......................................................................................................................................................................9
2.10 Thermal Characteristics................................................................................................................................................. 10
3 Board Layout.........................................................................................................................................................................11
3.1 Layout...............................................................................................................................................................................11
3.2 Estimated Circuit Area..................................................................................................................................................... 13
4 Schematic and Bill of Materials...........................................................................................................................................14
4.1 Schematic........................................................................................................................................................................ 14
4.2 Bill of Materials.................................................................................................................................................................15
5 Revision History................................................................................................................................................................... 15
List of Figures
Figure 2-1. TPS54320 Efficiency................................................................................................................................................. 5
Figure 2-2. TPS54320 Low Current Efficiency.............................................................................................................................5
Figure 2-3. TPS54320 Load Regulation...................................................................................................................................... 6
Figure 2-4. TPS54320 Line Regulation....................................................................................................................................... 6
Figure 2-5. TPS54320 Transient Response................................................................................................................................ 7
Figure 2-6. TPS54320 Loop Response....................................................................................................................................... 7
Figure 2-7. TPS54320 Output Ripple.......................................................................................................................................... 8
Figure 2-8. TPS54320 Input Ripple............................................................................................................................................. 8
Figure 2-9. TPS54320 Start-Up Relative to VIN ..........................................................................................................................9
Figure 2-10. TPS54320 Start-Up Relative to Enable...................................................................................................................9
Figure 2-11. TPS54320 Thermal Image.....................................................................................................................................10
Figure 3-1. TPS54320 Top-Side Layout.....................................................................................................................................11
Figure 3-2. TPS54320 Bottom-Side Layout...............................................................................................................................12
Figure 3-3. TPS54320 Top-Side Assembly................................................................................................................................13
Figure 4-1. TPS54320EVM-513 Schematic...............................................................................................................................14
List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................2
Table 1-2. TPS54320 Performance Specification Summary........................................................................................................2
Table 1-3. Output Voltages Available...........................................................................................................................................3
Table 2-1. EVM Connectors and Test Points............................................................................................................................... 4
Table 4-1. TPS54320 Bill of Materials........................................................................................................................................15
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
This user's guide contains background information for the TPS54320 as well as support documentation for the
TPS54320 evaluation module (HPA513). Also included are the performance specifications, the schematic, and
the bill of materials for the TPS54320.
1.1 Background
The TPS54320 dc/dc converter is designed to provide up to a 3 A output. The TPS54320 implements split
input power rails with separate input voltage inputs for the power stage and control circuitry. The power stage
input (PVIN) is rated for 1.6 V to 17 V while the control input (VIN) is rated for 4.5 to 17 V. The TPS54320
provides both inputs but is designed and tested using the PVIN connected to VIN. Rated input voltage and
output current range for the evaluation module are given in Table 1-1. This evaluation module is designed to
demonstrate the small printed-circuit-board areas that may be achieved when designing with the TPS54320
regulator. The switching frequency is externally set at a nominal 480 kHz. The high-side and low-side MOSFETs
are incorporated inside the TPS54320 package along with the gate drive circuitry. The low drain-to-source on
resistance of the MOSFETs allows the TPS54320 to achieve high efficiencies and helps keep the junction
temperature low at high output currents. The compensation components are external to the integrated circuit
(IC), and an external divider allows for an adjustable output voltage. Additionally, the TPS54320 provides
adjustable slow start, tracking and undervoltage lockout inputs. The absolute maximum input voltage is 20 V for
the TPS54320.
Table 1-1. Input Voltage and Output Current Summary
EVM Input Voltage Range Output Current Range
TPS54320 VIN = 8 V to 17 V (VIN start voltage = 6.806 V) 0 A to 3 A
1.2 Performance Specification Summary
A summary of the TPS54320 performance specifications is provided in Table 1-2. Specifications are given for
an input voltage of 12 V and an output voltage of 3.3 V, unless otherwise specified. The TPS54320 is designed
and tested for VIN = 8 V to 17 V with the VIN and PVIN pins connect together with the JP1 jumper. The ambient
temperature is 25°C for all measurements, unless otherwise noted.
Table 1-2. TPS54320 Performance Specification Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range (PVIN = VIN) 8 12 17 V
VIN start voltage 6.806 V
VIN stop voltage 4.824 V
Output voltage set point 3.3 V
Output current range VIN = 8 V to 17 V 0 3 A
Line regulation IO = 3 A, VIN = 8 V to 17 V ± 0.02 %
Load regulation VIN = 12 V, IO = 0 A to 3 A ± 0.02 %
Load transient response
IO = 0.75 A to 1.5 A Voltage change 90 mV
Recovery time 70 μs
IO = 1.5 A to 0.75 A Voltage change 80 mV
Recovery time 70 μs
Loop bandwidth VIN = 12 V, IO = 3 A 32.1 kHz
Phase margin VIN = 12 V , IO = 3 A 82 °
Input ripple voltage IO = 3 A 480 mVPP
Output ripple voltage IO = 3 A 10 mVPP
Output rise time 3.5 ms
Operating frequency 480 kHz
Maximum efficiency TPS54320EVM-513, VIN = 8 V, IO = 0.9 A 94.9 %
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1.3 Modifications
These evaluation modules are designed to provide access to the features of the TPS54320. Some modifications
can be made to this module.
1.3.1 Output Voltage Set Point
The output voltage is set by the resistor divider network of R8 and R9. R9 is fixed at 10 kΩ. To change the output
voltage of the EVM, it is necessary to change the value of resistor R8. Changing the value of R8 can change the
output voltage above 0.8 V. The value of R8 for a specific output voltage can be calculated using Equation 1.
( )
OUT
10 kΩ V - 0.8 V
R8 =
0.8 V
(1)
Table 1-3 lists the R8 values for some common output voltages. Note that VIN must be in a range so that the
minimum on-time is greater than 135 ns, and the maximum duty cycle is less than 95%. The values given in
Table 1-3 are standard values, not the exact value calculated using Equation 1.
Table 1-3. Output Voltages Available
Output Voltage
(V)
R8 Value (kΩ)
1.8 12.4
2.5 21.5
3.3 31.6
5 52.3
1.3.2 Slow Start Time
The slow start time can be adjusted by changing the value of C7. Use Equation 2 to calculate the required value
of C7 for a desired slow start time
Tss(ms) Iss( A)
C7(nF) = Vref(V)
´ m
(2)
The EVM is set for a slow start time of 3.5 msec using C7 = 0.01 μF.
1.3.3 Track In
The TPS54320 can track an external voltage during start up. The J5 connector is provided to allow connection
to that external voltage. Ratio-metric or simultaneous tracking can be implemented using resistor divider R5 and
R6. See the TPS54320 data sheet (SLVS982) for details.
1.3.4 Adjustable UVLO
The under voltage lock out (UVLO) can be adjusted externally using R1 and R2. The EVM is set for a start
voltage of 6.528 V and a stop voltage of 6.190 V using R1 = 511 kΩ and R2 = 100 kΩ. Use Equation 3 and
Equation 4 to calculate the required resistor values for different start and stop voltages.
1
æ ö -
ç ÷
è ø
æ ö
- +
ç ÷
è ø
ENFALLING
START STOP
ENRISING
ENFALLING
p h
ENRISING
V
V V
V
R1 = V
I I
V
(3)
( )
´
- + +
ENFALLING
STOP ENFALLING p h
R1 V
R2 = V V R1 I I
(4)
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1.3.5 Input Voltage Rails
The EVM is designed to accommodate different input voltage levels for the power stage and control logic. During
normal operation, the PVIN and VIN inputs are connected together using a jumper across JP1. The single input
voltage is supplied at J1. If desired, these two input voltage rails may be separated by removing the jumper
across JP1. Two input voltages, which could be at different voltages, must then be provided at both J1 and J2.
2 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54320 evaluation module. The section
also includes test results typical for the evaluation module and covers efficiency, output voltage regulation, load
transients, loop response, output ripple, input ripple, and start-up.
2.1 Input / Output Connections
The TPS54320 is provided with input/output connectors and test points as shown in Table 2-1. A power supply
capable of supplying 2 A must be connected to J1 through a pair of 20 AWG wires. The jumper across JP1 must
be in place. See Section 1.3.5 for split input voltage rail operation. The load must be connected to J3 through
a pair of 20 AWG wires. The maximum load current capability must be 3 A. Wire lengths must be minimized to
reduce losses in the wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing
a convenient ground reference. TP8 is used to monitor the output voltage with TP9 as the ground reference.
Table 2-1. EVM Connectors and Test Points
Reference Designator Function
J1 PVIN input voltage connector. (see Table 1-1 for VIN range).
J2 VIN input voltage connector. Not normally used.
J3 VOUT, 3.3 V at 3 A maximum.
J4 2-pin header for tracking output and ground.
J5 2-pin header for tracking voltage input and ground.
JP1 PVIN to VIN jumper. Normally closed to tie VIN to PVIN for common rail voltage operation.
JP2 2-pin header for enable. Connect EN to ground to disable, open to enable.
TP1 PVIN test point at PVIN connector.
TP2 GND test point at PVIN connector.
TP3 VIN test point at VIN connector.
TP4 GND test point at VIN connector.
TP5 PH test point.
TP6 Slow start / track in test point.
TP7 Test point between voltage divider network and output. Used for loop response measurements.
TP8 Output voltage test point at VOUT connector.
TP9 GND test point at VOUT connector.
TP10 PWRGD test point.
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2.2 Efficiency
The efficiency of this EVM peaks at a load current of about 0.9 A and then decreases as the load current
increases towards full load. Figure 2-1 shows the efficiency for the TPS54320 at an ambient temperature of
25°C.
60
65
70
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5 3
Load Current - A
V = 10 V
I
V = 12 V
I
V = 15 V
I
V = 17 V
I
V = 8 V
I
Efficiency - %
Figure 2-1. TPS54320 Efficiency
Figure 2-2 shows the efficiency for the TPS54320 at lower output currents below 0.20 A at an ambient
temperature of 25°C.
0 20 40 60 80 100 120 140 160 180 200
0
10
20
30
40
50
60
70
80
90
100
Efficiency - %
I - Output Current - mA
O
V = 17 V
I
V = 8 V
I
V = 15 V
I
V = 10 V
I
V = 12 V
I
Figure 2-2. TPS54320 Low Current Efficiency
The efficiency may be lower at higher ambient temperatures, due to temperature variation in the drain-to-source
resistance of the internal MOSFET.
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2.3 Output Voltage Load Regulation
Figure 2-3 shows the load regulation for the TPS54320.
0 0.5 1 1.5 2 2.5 3
I - Output Current - A
O
V = 8 V
IN
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
Load Regulation - %
V = 10 V
IN
V = 12 V
IN
V = 15 V
IN
V = 17 V
IN
Figure 2-3. TPS54320 Load Regulation
Measurements are given for an ambient temperature of 25°C.
2.4 Output Voltage Line Regulation
Figure 2-4 shows the line regulation for the TPS54320.
8 10 12 14 16
V - Input Voltage - V
I
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
Percent Deviation - %
I = 0 A
OI = 1.5 A
O
I = 3 A
O
Figure 2-4. TPS54320 Line Regulation
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2.5 Load Transients
Figure 2-5 shows the TPS54320 response to load transients. The current step is from 25% to 50% of maximum
rated load at 12 V input. Total peak-to-peak voltage variation is as shown, including ripple and noise on the
output.
I = 500 mA/div
(0.75 to 1.5 A load step)
OUT
V = 12 V
IN
t - Time - 20 s/divm
V = 50 mV/div (AC coupled)
OUT
Figure 2-5. TPS54320 Transient Response
2.6 Loop Characteristics
Figure 2-6 shows the TPS54320 loop-response characteristics. Gain and phase plots are shown for VIN of 12 V.
Load current for the measurement is 3 A.
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
100 1k 10k 100k 1M
f - Frequency - Hz
-180
-150
-120
-90
-60
-30
0
30
60
90
120
150
180
Phase
Gain
Gain - dB
Phase - deg
Figure 2-6. TPS54320 Loop Response
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2.7 Output Voltage Ripple
Figure 2-7 shows the TPS54320 output voltage ripple. The output current is the rated full load of 3 A and
VIN = 12 V. The ripple voltage is measured directly across the output capacitors with a low inductance probe.
Measuring at the output test points, TP8 and TP9, can pick up some radiated noise and give an erroneous
measurement.
V = 10 mV/div (AC coupled)
OUT
t - Time - 1 s/divm
Inductor current = 1 A/div
PH = 10 V/div
Figure 2-7. TPS54320 Output Ripple
2.8 Input Voltage Ripple
Figure 2-8 shows the TPS54320 input voltage. The output current is the rated full load of 3 A and VIN = 12 V.
The ripple voltage is measured directly across the input capacitors.
V = 200 mV/div (AC coupled)
IN
Inductor current = 1 A/div
PH = 10 V/div
t - Time - 1 s/divm
Figure 2-8. TPS54320 Input Ripple
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2.9 Powering Up
Figure 2-9 and Figure 2-10 show the start-up waveforms for the TPS54320. In Figure 2-9, the output voltage
ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor divider
network. In Figure 2-10, the input voltage is initially applied and the output is inhibited by using a jumper
at JP2 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the
enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set
value of 3.3 V. The input voltage for these plots is 12 V and the load is 1.1Ω.
V = 10 V/div
IN
EN = 2 V/div
SS/TR = 1 V/div
V = 2 V/div
OUT
t - Time - 2 ms/div
Figure 2-9. TPS54320 Start-Up Relative to VIN
V = 10 V/div
IN
EN = 2 V/div
SS/TR = 1 V/div
V = 2 V/div
OUT
t - Time - 2 ms/div
Figure 2-10. TPS54320 Start-Up Relative to Enable
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2.10 Thermal Characteristics
This section shows a thermal image of the TPS54320 running at 12 V input and 3 A load. there is no air flow
and the ambient temperature is 25°C. The peak temperature of the IC (59.5°C) is well below the maximum
recommended operating condition listed in the data sheet of 150°C.
Figure 2-11. TPS54320 Thermal Image
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