Texas Instruments ADS1282 User manual

4th-Order
DS
Modulator
Programmable
Digital Filter
SPI
Interface
Calibration
Control
CLK
AVDD
AVSS
DVDD
DGND
Over-Range
Modulator Output
ADS1282
DOUT
DIN
DRDY
SCLK
SYNC
RESET
PWDN
3
PGA
MUX
Input 1
Input 2
VREFN VREFP
VCOM
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
ADS1282 High-Resolution Analog-To-Digital Converter
1 Features 3 Description
The ADS1282 is an extremely high-performance,
1• High Resolution: single-chip analog-to-digital converter (ADC) with an
130-dB SNR (250 SPS) integrated, low-noise programmable gain amplifier
• High Accuracy: (PGA) and two-channel input multiplexer (mux). The
THD: –122 dB ADS1282 is suitable for the demanding needs of
INL: 0.5 ppm energy exploration and seismic monitoring
environments.
• Low-Noise PGA
• Two-Channel Input Mux The converter uses a fourth-order, inherently stable,
delta-sigma (ΔΣ) modulator that provides outstanding
• Inherently-Stable Modulator with Fast Responding noise and linearity performance. The modulator is
Overrange Detection used either in conjunction with the on-chip digital
• Flexible Digital Filter: filter, or can be bypassed for use with post
Sinc + FIR + IIR (Selectable) processing filters.
Linear or Minimum Phase Response The flexible input MUX provides an additional
Programmable High-Pass Filter external input for measurement, as well as internal
Selectable FIR Data Rates: 250 SPS to 4 kSPS self-test connections. The PGA features outstanding
• Filter Bypass Option low noise (5 nV/√Hz) and high input impedance,
• Low Power Consumption: 25 mW allowing easy interfacing to geophones and
hydrophones over a wide range of gains.
Shutdown: 10 μW
• Offset and Gain Calibration Engine The digital filter provides selectable data rates from
250 to 4000 samples per second (SPS). The high-
• SYNC Input pass filter (HPF) features an adjustable corner
• Analog Supply: frequency. On-chip gain and offset scaling registers
Unipolar (+5 V) or Bipolar (±2.5 V) support system calibration.
• Digital Supply: 1.8 V to 3.3 V The synchronization input (SYNC) can be used to
synchronize the conversions of multiple ADS1282s.
2 Applications The SYNC input also accepts a clock input for
• Energy Exploration continuous alignment of conversions from an external
source.
• Seismic Monitoring
• High-Accuracy Instrumentation Together, the amplifier, modulator, and filter dissipate
25 mW. The ADS1282 is available in a compact
TSSOP-28 package and is fully specified from –40°C
to +85°C, with a maximum operating range to
+125°C.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
4 Ordering Information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at ti.com.
5 Specifications
5.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted).
ADS1282, ADS1282H UNIT
AVDD to AVSS –0.3 to +5.5 V
AVSS to DGND –2.8 to +0.3 V
DVDD to DGND –0.3 to +3.9 V
Input current 100, momentary mA
Input current 10, continuous mA
Analog input voltage AVSS – 0.3 to AVDD + 0.3 V
Digital input voltage to DGND –0.3 to DVDD + 0.3 V
Maximum junction temperature +150 °C
Operating temperature range –40 to +125 °C
Storage temperature range –60 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
5.2 Electrical Characteristics
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz,
VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, and fDATA = 1000SPS, unless otherwise
noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale input voltage VIN = (AINP – AINN) ±VREF/(2 × PGA) V
Absolute input range AINP or AINN AVSS + 0.7 AVDD – 1.25 V
PGA input voltage noise density 5 nV/√Hz
Chop on 1 GΩ
Differential input impedance Chop off 100 GΩ
Common-mode input impedance 100 MΩ
Input bias current 1 nA
Crosstalk f = 31.25Hz –135 dB
MUX on-resistance 30 Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range AVSS + 0.4 AVDD – 0.4 V
PGA differential output impedance 600 Ω
Output impedance tolerance ±10%
External bypass capacitance 10 100 nF
Modulator differential input impedance 55 kΩ
AC PERFORMANCE
Signal-to-noise ratio(2) SNR 120 124 dB
PGA = 1...16 –122 –114
Total harmonic distortion(3) THD PGA = 32 –117 –110 dB
PGA = 64 –115
Spurious-free dynamic dB
SFDR 123
range
DC PERFORMANCE
Resolution No missing codes 31 Bits
FIR filter mode 250 4000 SPS
Data rate fDATA Sinc filter mode 8000 128,000 SPS
Integral nonlinearity (INL)(4) Differential input 0.00005 0.0004 % FSR(5)
Offset error 50 200 μV
Offset error after calibration(6) Shorted input 1 μV
Offset drift 0.02 μV/°C
Gain error(7) –1.5% –1.0% –0.5%
Gain error after calibration(6) 0.0002%
PGA = 1 2 ppm/°C
Gain drift PGA = 16 9 ppm/°C
Gain matching(8) 0.3% 0.8%
Common-mode rejection fCM = 60Hz(9) 95 110 dB
AVDD, AVSS 80 90
Power-supply rejection fPS = 60Hz(9) dB
DVDD 90 115
(1) fCLK = system clock.
(2) VIN = 20mVDC/PGA; see Table 1.
(3) VIN = 31.25Hz, –0.5dBFS.
(4) Best-fit method.
(5) FSR: Full-scale range = ±VREF/(2 × PGA).
(6) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
(7) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
(8) Gain match relative to PGA = 1.
(9) fCM is the input common-mode frequency. fPS is the power-supply frequency.
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: ADS1282

ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
Electrical Characteristics (continued)
Limit specifications at –40°C to +85°C. Typical specifications at +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK (1) = 4.096MHz,
VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, CAPN – CAPP = 10nF, PGA = 1, and fDATA = 1000SPS, unless otherwise
noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE INPUTS
(AVDD – AVSS)
Reference input voltage (VREF = VREFP – VREFN) 0.5 5 V
+ 0.2
Negative reference input VREFN AVSS – 0.1 VREFP – 0.5 V
Positive reference input VREFP VREFN + 0.5 AVDD + 0.1 V
Reference input impedance 85 kΩ
DIGITAL FILTER RESPONSE
Passband ripple ±0.003 dB
Passband (–0.01dB) 0.375 × fDATA Hz
Bandwidth (–3dB) 0.413 × fDATA Hz
High-pass filter corner 0.1 10 Hz
Stop band attenuation(10) 135 dB
Stop band 0.500 × fDATA Hz
Minimum phase filter(11) 5/fDATA
Group delay s
Linear phase filter 31/fDATA
Minimum phase filter 62/fDATA
Settling time (latency) s
Linear phase filter 62/fDATA
DIGITAL INPUT/OUTPUT
VIH 0.8 × DVDD DVDD V
VIL DGND 0.2 × DVDD V
VOH IOH = 1mA 0.8 × DVDD V
VOL IOL = 1mA 0.2 × DVDD V
Input leakage 0 < VDIGITAL IN < DVDD ±10 μA
Clock input fCLK 1 4.096 MHz
Serial clock rate fSCLK fCLK/2 MHz
POWER SUPPLY
AVSS –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 V
DVDD 1.65 3.6 V
Normal operation 4.5 6.5 |mA|
AVDD, AVSS current Standby mode 1 15 |μA|
Power-down mode 1 15 |μA|
Normal operation 0.6 0.8 mA
Modulator mode 0.1 mA
DVDD current Standby mode 25 50 μA
Power-down mode(12) 1 15 μA
Normal operation 25 35 mW
Power dissipation Standby mode 90 250 μW
Power-down mode 10 125 μW
(10) Input frequencies in the range of NfCLK/512 ± fDATA/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency
ranges intermodulation = 120dB, typ.
(11) At dc; see Figure 44.
(12) CLK input stopped.
4Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

SCLK
DIN
DOUT
tSCLK tSPWH
tSCDL
tDIST
tDIHD
tSPWL
tSCDL
tDOHD
tDOPD
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
6 Timing Diagram
6.1 Timing Requirements
At TA= –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted.
PARAMETER DESCRIPTION MIN MAX UNITS
tSCLK SCLK period 2 16 1/fCLK
tSPWH, L SCLK pulse width, high and low(1) 0.8 10 1/fCLK
tDIST DIN valid to SCLK rising edge: setup time 50 ns
tDIHD Valid DIN to SCLK rising edge: hold time 50 ns
tDOPD SCLK falling edge to valid new DOUT: propagation delay(2) 100 ns
tDOHD SCLK falling edge to DOUT invalid: hold time 0 ns
Final SCLK rising edge of command to first SCLK rising edge for register read/write
tSCDL 24 1/fCLK
data. (Also between consecutive commands.)
(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.
(2) Load on DOUT = 20pF || 100kΩ.
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: ADS1282

CLK
SCLK
DRDY
DOUT
DIN
DGND
MCLK
M1
M0
SYNC
MFLAG
DGND
CAPN
CAPP
BYPAS
DGND
DVDD
DGND
RESET
PWDN
VREFP
VREFN
AVSS
AVDD
AINN1
AINP1
AINN2
AINP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS1282
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
7 Pin Configuration and Functions
PW Package
TSSOP-28
(Top View)
Pin Functions
NAME NO. FUNCTION DESCRIPTION
CLK 1 Digital input Master clock input
SCLK 2 Digital input Serial clock input
DRDY 3 Digital output Data ready output: read data on falling edge
DOUT 4 Digital output Serial data output
DIN 5 Digital input Serial data input
Modulator clock output; if in modulator mode:
MCLK 7 Digital I/O MCLK: Modulator clock output
Otherwise, the pin is an unused input (must be tied).
Modulator data output 1; if in modulator mode:
M1 8 Digital I/O M1: Modulator data output 1
Otherwise, the pin is an unused input (must be tied).
Modulator data output 0; if in modulator mode:
M0 9 Digital I/O M0: Modulator data output 0
Otherwise, the pin is an unused input (must be tied).
SYNC 10 Digital input Synchronize input
MFLAG 11 Digital output Modulator Over-Range flag: 0 = normal, 1 = modulator over-range
DGND 6, 12, 25, 27 Digital ground Digital ground, pin 12 is the key ground point
CAPN 13 Analog PGA outputs: Connect 10nF capacitor from CAPP to CAPN
CAPP 14 Analog PGA outputs: Connect 10nF capacitor from CAPP to CAPN
AINP2 15 Analog input Positive analog input 2
AINN2 16 Analog input Negative analog input 2
AINP1 17 Analog input Positive analog input 1
AINN1 18 Analog input Negative analog input 1
AVDD 19 Analog supply Positive analog power supply
AVSS 20 Analog supply Negative analog power supply
VREFN 21 Analog input Negative reference input
VREFP 22 Analog input Positive reference input
PWDN 23 Digital input Power-down input, active low
RESET 24 Digital input Reset input, active low
DVDD 26 Digital supply Digital power supply: +1.8V to +3.3V
BYPAS 28 Analog Sub-regulator output: Connect 1μF capacitor to DGND
6Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

0 50
Frequency (Hz)
0
-20
-40
-60
-80
-180
Amplitude (dB)
100 150 500250 350 450200 300 400
-100
-120
-140
-160
8192-Point FFT
20mV
SNR = 124.2dB
DC
10 20
Input Frequency (Hz)
-
-
-
-
-
-
-
100
105
110
115
120
125
130
Total Harmonic Distortion (dB)
30 40 10060 8050 70 90
V = 0.5dBFS
IN -
THD Limited by
Signal Generator
PGA = 1
PGA = 8
0 50
Frequency (Hz)
0
-20
-40
-60
-80
-180
Amplitude (dB)
100 150 500250 350 450200 300 400
-100
-120
-140
-160
8192-Point FFT
V = 0.5dBFS, 31.25Hz
PGA = 16
THD = 122.4dB
IN -
-
0 50
Frequency (Hz)
0
-20
-40
-60
-80
-180
Amplitude (dB)
100 150 500250 350 450200 300 400
-100
-120
-140
-160
8192-Point FFT
Shorted Input
SNR = 124.0dB
0 50
Frequency (Hz)
0
-20
-40
-60
-80
-180
Amplitude (dB)
100 150 500250 350 450200 300 400
-100
-120
-140
-160
8192-Point FFT
V = 0.5dBFS, 31.25Hz
PGA = 1
THD = 124.0dB
IN -
-
0 50
Frequency (Hz)
0
-20
-40
-60
-80
-180
Amplitude (dB)
100 150 500250 350 450200 300 400
-100
-120
-140
-160
8192-Point FFT
V = 20dBFS, 31.25Hz
PGA = 1
THD = 120.1dB
IN -
-
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
8 Typical Characteristics
At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,
CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.
Figure 1. Output Spectrum Figure 2. Output Spectrum
Figure 3. Output Spectrum Figure 4. Output Spectrum
Figure 5. Output Spectrum Figure 6. THD vs Input Frequency
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: ADS1282

0.5 1.0
f (MHz)
CLK
125
124
123
122
121
120
119
Signal-to-Noise Ratio (dB)
1.5 2.0 4.53.02.5 3.5 4.0
V = 20mV
Data Rate = f /4096
IN DC
CLK
0.5 1.0
f (MHz)
CLK
-110
115
120
125
130
-
-
-
-
Total Harmonic Distortion (dB)
1.5 2.0 4.53.02.5 3.5 4.0
PGA = 8
V = 31.25Hz, 0.5dBFS
Data Rate = f /4096
IN
CLK
-
0 1
V (V)
REF
130
125
120
115
110
105
100
Signal-to-Noise Ratio (dB)
2 3 5.554
PGA = 1
PGA = 8
0 1
V (V)
REF
-110
115
120
125
130
-
-
-
-
Total Harmonic Distortion (dB)
2 3 654
PGA = 1
PGA = 8
-55 -35
Temperature ( C)°
126
125
124
123
122
121
120
Signal-to-Noise Ratio (dB)
-15 5 12545 8525 65 105
V = 20mV
IN DC
-55 -35
Temperature ( C)°
-110
115
120
125
130
-
-
-
-
Total Harmonic Distortion (dB)
-15 5 12545 8525 65 105
PGA = 8
V = 31.25Hz, 0.5dBFS
IN -
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
Typical Characteristics (continued)
At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,
CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.
Figure 7. SNR vs Temperature Figure 8. THD vs Temperature
Figure 9. SNR vs Reference Voltage Figure 10. THD vs Reference Voltage
Figure 11. SNR vs Clock Frequency Figure 12. THD vs Clock Frequency
8Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

0 50
Frequency (Hz)
0
20
40
60
80
100
120
140
160
180
-
-
-
-
-
-
-
-
-
Amplitude (dB)
100 150 500200 250 300 350 400 450
Shorted Input
8192-Point FFT
Adjacent Channel V = 0.5dBFS, 31.25Hz
IN -
-55 -35
Temperature ( C)°
30
25
20
15
10
Power (mW)
-15 5 12525 45 65 85 105
-100 -75
Input Amplitude (% Full-Scale)
4
3
2
1
0
1
2
3
4
-
-
-
-
Integral Nonlinearity (ppm)
-50 -25 1000 25 50 75
PGA = 8 PGA = 32
PGA = 2
-55 -35
Temperature ( C)°
4
3
2
1
0
Integral Nonlinearity (ppm)
-15 5 12525 45 65 85 105
10 100
Power-Supply Frequency (Hz)
140
120
100
80
60
40
20
0
Power-Supply Rejection (dB)
1k 10k 1M100k
DVDD
AVSS
AVDD
10 100
Input Frequency (Hz)
130
120
110
100
90
80
70
Common-Mode Rejection (dB)
1k 10k 1M100k
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
Typical Characteristics (continued)
At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,
CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.
Figure 13. CMR vs Input Frequency Figure 14. Power-Supply Rejection vs Frequency
Figure 15. INL vs Input Amplitude Figure 16. INL vs Temperature
Figure 17. Crosstalk Output Spectrum Figure 18. Power vs Temperature
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: ADS1282

0.50
0.46
Gain Error (%)
8
6
4
2
0
Occurrences
0.42
0.38
0.02
0.34
0.30
0.26
0.18
0.22
0.14
Worst-Case Gain Match Relative PGA = 1 (25 Units)
0.10 0.06
-15
-14
Gain Drift (ppm/ C)°
90
80
70
60
50
40
30
20
10
0
Occurrences
-13
-12
5
-11
-10
-9
PGA = 1, 2, 4
PGA = 8, 64
-7
-8
-6
25 Units Based on +20 C Intervals
Over the Range of 40 C to +85 C
°
° °-
PGA = 32
PGA = 16
4
3
2
1
0
-5 -4
-3 -2
-1
-0.10
-0.08
Offset Drift ( V/ C)m °
90
80
70
60
50
40
30
20
10
0
Occurrences
-0.06
-0.04
0.10
-0.02
0
0.02
PGA = 8
PGA =1
0.06
0.04
0.08
25 Units Based on
+20 C Intervals
Over the Range of
40 C to +85 C
°
° °-
-1.2 -1.1
Gain Error (%)
10
8
6
4
2
0
Occurrences
-1.0 -0.9 -0.3-0.8 -0.7 -0.6
25 Units
-0.4-0.5
1.0 1.5
f (MHz)
CLK
30
25
20
15
10
5
0
Power (mW)
2.0 2.5 4.53.0 3.5 4.0
-100 -80
Offset ( V)m
30
25
20
15
10
5
0
Occurrences
-60 -40 100-20 0 20
25 Units
PGA = 8
PGA = 1
806040
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
Typical Characteristics (continued)
At +25°C, AVDD = +2.5V, AVSS = –2.5V, fCLK = 4.096MHz, VREFP = +2.5V, VREFN = –2.5V, DVDD = +3.3V, PGA = 1,
CAPN – CAPP = 10nF, and fDATA = 1000SPS, unless otherwise noted.
Figure 19. Power vs Clock Frequency Figure 20. Offset Histogram
Figure 21. Gain Error Histogram Figure 22. Offset Drift Histogram
Figure 23. Gain Drift Histogram Figure 24. Gain Match Histogram
10 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

4th-Order
DS
Modulator
Programmable
Digital Filter
Serial
Interface
Calibration
Control
AINP1
CAPN CAPP
AVSS
CLK DVDD
DGND
DIN
DOUT
MCLK
DRDY
SCLK
AINN1
VREFN
M0 M1
VREFP
ADS1282
AINN2
AINP2
Over-Range
Detection
BYPAS
LDO
PGA
MUX
400W
AVDD + AVSS
400W
2
+1.8V
(Digital core)
300W
300W
RESET
PWDN
SYNC
AVDD
MFLAG
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
9 Overview
The ADS1282 is a high-performance analog-to-digital Gain and offset registers scale the digital filter output
converter (ADC) intended for energy exploration, to produce the final code value. The scaling feature
seismic monitoring, chomatography, and other can be used for calibration and sensor gain matching.
exacting applications. The converter provides 24- or The output data word is provided as either a 24-bit
32-bit output data in data rates from 250SPS to word or a full 32-bit word, allowing complete
4000SPS. Figure 25 shows the block diagram of the utilization of the inherently high resolution.
ADS1282. The SYNC input resets the operation of both the
The two-channel input MUX allows five digital filter and the modulator, allowing
configurations: Input 1; Input 2; Input 1 and Input 2 synchronization conversions of multiple ADS1282
shorted together; shorted with 400Ωtest; and devices to an external event. The SYNC input
common-mode test. The input MUX is followed by a supports a continuously-toggled input mode that
continuous time PGA, featuring very low noise of accepts an external data frame clock locked to the
5nV/√Hz. The PGA is controlled by register settings, conversion rate.
allowing gains of 1 to 64. The RESET input resets the register settings and
The inherently-stable, fourth-order, delta-sigma also restarts the conversion process. The PWDN
modulator measures the differential input signal input sets the device into a micro-power state. Note
VIN = (AINP – AINN) PGA against the differential that register settings are not retained in PWDN mode.
reference VREF = (VREFP – VREFN). A digital output Use the STANDBY command in its place if it is
(MFLAG) indicates that the modulator is in overload desired to retain register settings (the quiescent
as a result of an overdrive condition. The modulator current in the Standby mode is slightly higher).
output is available directly on the MCLK, M0, and M1 Noise-immune Schmitt-trigger and clock-qualified
output pins. The modulator connects to an on-chip inputs (RESET and SYNC) provide increased
digital filter that provides the output code readings. reliability in high-noise environments. The serial
The digital filter consists of a variable decimation rate, interface is used to read conversion data, in addition
fifth-order sinc filter followed by a variable phase, to reading from and writing to the configuration
decimate-by-32, finite-impulse response (FIR) low- registers.
pass filter with programmable phase, and then by an
adjustable high-pass filter for dc removal of the output
reading. The output of the digital filter can be taken
from the sinc, the FIR low-pass, or the infinite impulse
response (IIR) high-pass sections.
Figure 25. ADS1282 Block Diagram
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: ADS1282

SNR = 20log FSRRMS
NRMS
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
The device features unipolar and bipolar analog 9.2 Noise Performance
power supplies (AVDD and AVSS, respectively) for The ADS1282 offers outstanding noise performance
input range flexibility and a digital supply accepting (SNR). SNR depends on the data rate, the PGA
1.8V to 3.3V. The analog supplies may be set to +5V setting. As the bandwidth is reduced by decreasing
to accept unipolar signals (with input offset) or set the data rate, the SNR improves correspondingly.
lower in the range of ±2.5V to accept true bipolar Similarly, as the PGA gain is increased, the SNR
input signals (ground referenced). decreases. Table 1 summarizes the noise
An internal sub-regulator is used to supply the digital performance versus data rate and PGA setting.
core from DVDD. The BYPAS pin (pin 28) is the sub-
regulator output and requires a 1μF capacitor for 9.3 Input-Referred Noise
noise reduction. BYPAS should not be used to drive The input-referred noise is related to SNR by
external circuitry. Equation 1:
9.1 ADS1282H
The Hversion of the ADS1282 has an improved input
stage compared to the base version ADS1282. The where:
ADS1282H design is optimized for use with high
impedance sensors, such as hydrophones. The FSRRMS = Full-scale range RMS = VREF/(2 × √2 ×
ADS1282H is recommended when interfacing to PGA)
hydrophone sensors and can also be used for low- NRMS = Noise RMS (input-referred) (1)
impedance, geophone sensors as well. The base
version ADS1282 should only be used with low- 9.4 Idle Tones
impedance geophone sensors, where the associated
external terminating resistance is < 50kΩ(per The ADS1282 modulator incorporates an internal
resistor). dither signal that randomizes the idle tone energy.
Low-level idle tones may still be present, typically
–137dB below full-scale. The low-level idle tones can
be shifted out of the passband with an external offset
= 20mV/PGA. See the Application Information section
for the recommended offset circuit.
Table 1. Signal-to-Noise Ratio (dB)(1)
PGA
DATA RATE
(SPS) 1 2 4 8 16 32 64
250 130 130 129 128 125 119 114
500 127 127 126 125 122 116 111
1000 124 124 123 122 119 113 108
2000 121 121 120 119 116 111 106
4000 118 118 117 116 113 108 103
(1) VIN = 20mVDC/PGA.
12 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

500W
500W
RLOAD
Input 1
Input 2
ADS1282
AVSS + 0.7V < (AINN or AINP) < AVDD 1.25V-
Total Harmonic Distortion (dB)
R ( )W
LOAD
0
-
-
-
-
-
-
-
20
40
60
80
100
120
140
0.1k 1k 10k 10M100k 1M
PGA = 1
PGA = 2
PGA = 64
PGA = 32
PGA = 16
PGA = 8
PGA = 4
S1
S2
S3
S4
S5
S6
AINP1
AINP2
AINN2
AINN1
S7
(+)
(-)
To PGA
AVDD + AVSS
2
400W
400W
AVSS
AVDD
AVDD
AVSS
ESD Diodes
ESD Diodes
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
9.5 Analog Inputs and Multiplexer Analog Inputs and Multiplexer (continued)
A diagram of the input multiplexer is shown in Table 2. Multiplexer Modes
Figure 26.MUX[2:0] SWITCHES DESCRIPTION
ESD diodes protect the multiplexer inputs. If either AINP1 and AINN1 connected to
000 S1, S5preamplifier
input is taken below AVSS – 0.3V or above AVDD + AINP2 and AINN2 connected to
0.3V, the ESD protection diodes may turn on. If these 001 S2, S6preamplifier
conditions are possible, external Schottky clamp Preamplifier inputs shorted together
diodes and/or series resistors may be required to limit 010 S3, S4through 400Ωinternal resistors
the input current to safe values (see the Absolute AINP1, AINN1 and AINP2, AINN2
011 S1, S5, S2, S6
Maximum Ratings table). connected together and to the preamplifier
External short, preamplifier inputs shorted
Also, overdriving one unused input may affect the 100 S6, S7to AINN2 (common-mode test)
conversions of the other input. If overdriven inputs
are possible, it is recommended to clamp the signal The typical on-resistance (RON) of the multiplexer
with external Schottky diodes. switch is 30Ω. When the multiplexer is used to drive
an external load on one input by a signal generator
on the other input, on-resistance and on-resistance
amplitude dependency can lead to measurement
errors. Figure 27 shows THD versus load resistance
and amplitude. Note that THD improves with high-
impedance loads and with lower amplitude drive
signals. The data are measured with the circuit from
Figure 28 with MUX[2:0] = 011.
Figure 26. Analog Inputs and Multiplexer Figure 27. THD Versus External Load and Signal
Magnitude (PGA) (see Figure 28)
The specified input operating range of the PGA is
shown in Equation 2:
(2)
Absolute input levels (input signal level and common-
mode level) should be maintained within these limits
for best operation.
The multiplexer connects one of the two external
differential inputs to the preamplifier inputs, in
addition to internal connections for various self-test
modes. Table 2 summarizes the multiplexer
configurations for Figure 26.Figure 28. Driving an External Load Through the
Mux
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: ADS1282

AVSS + 0.4V < (CAPN or CAPP) < AVDD 0.4V-
Gain Control
PGA[2:0] Bits
MUX (+)
MUX ( )-
CHOP
Chopping Control CHOP Bit
AVSS
CAPP
300W
300W
A1
A2
AVDD
CAPN
(55k , typ
Modulator
Effective
Impedance
W)
10nF
10
Frequency (Hz)
100
10
1
PGA Noise (nV/ )ÖHz
100 1k
PGA CHOP Off
PGA CHOP On
f =
P
1
6.3 600 C´ ´
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
9.6 PGA (Programmable Gain Amplifier) PGA (Programmable Gain
Amplifier) (continued)
The PGA of the ADS1282 is a low-noise, continuous-
time, differential-in/differential-out CMOS amplifier.
The gain is programmable from 1 to 64, set by
register bits, PGA[2:0]. The PGA differentially drives
the modulator through 300Ωinternal resistors. A C0G
capacitor (10nF typical) must be connected to CAPP
and CAPN to filter modulator sampling glitches. The
external capacitor also serves as an anti-alias filter.
The corner frequency is given in Equation 3:
(3)
Referring to Figure 29, amplifiers A1and A2are
chopped to remove the offset, offset drift, and the 1/f
noise. Chopping moves the effects to fCLK/128 (8kHz),
which is safely out of the passband. Chopping can be
disabled by setting the CHOP register bit = 0. When Figure 30. PGA Noise
chopping is disabled, the input impedance of the PGA
increases substantially (100GΩ). As shown in
Figure 30, chopping maintains flat noise density; if The PGA has programmable gains from 1 to 64.
chopping is disabled, however, it results in a rising 1/f Table 3 shows the register bit setting for the PGA and
noise profile. resulting full-scale differential range.
Table 3. PGA Gain Settings
DIFFERENTIAL
INPUT RANGE
PGA[2:0] GAIN (V)(1)
000 1 ±2.5
001 2 ±1.25
010 4 ±0.625
011 8 ±0.312
100 16 ±0.156
101 32 ±0.078
110 64 ±0.039
(1) VREF = 5V.
The specified output operating range of the PGA is
shown in Equation 4:(4)
Figure 29. PGA Block Diagram PGA output levels (signal plus common-mode) should
be maintained within these limits for best operation.
14 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

Y[n] = 3M0[n 2] 6M0[n 3] + 4M0[n 4]
+ 9(M1[n] 2M1[n 1] + M1[n 2])
- - - -
- - -
2nd-Order
2nd-Stage
DS
2nd-Order
1st-Stage
DS
Analog Input (V )
IN
4th-Order Modulator
MCLK
M0
M1
fCLK/4
Magnitude (dB)
Frequency (Hz)
0
-20
-40
-60
-80
-100
-180
1 10 100 100k
1k 10k
-120
-140
-160
1Hz Resolution
V = 20mV
IN DC
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
9.7 ADC Modulator (continued)
The ADC block of the ADS1282 is composed of two appears at the chopping frequency (fCLK/512 = 8kHz).
sections: a high-accuracy modulator and a The component at 5.8kHz is the tone frequency,
programmable digital filter. shifted out of band by an external 20mV/PGA offset.
The frequency of the tone is proportional to the
9.8 Modulator applied dc input and is given by PGA × VIN/0.003 (in
kHz).
The high-performance modulator is an inherently-
stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as
Figure 31 shows. It shifts the quantization noise to a
higher frequency (out of the passband) where digital
filtering can easily remove it. The modulator can be
filtered either by the on-chip digital filter or by use of
post-processing filters.
Figure 32. Modulator Output Spectrum
9.9 Modulator Over-Range
Figure 31. Fourth-Order Modulator The ADS1282 modulator is inherently stable, and
therefore, has predictable recovery behavior resulting
The modulator first stage converts the analog input from an input overdrive condition. The modulator
voltage into a pulse-code modulated (PCM) stream. does not exhibit self-resetting behavior, which often
When the level of differential analog input (AINP – results in an unstable output data stream.
AINN) is near one-half the level of the reference
voltage 1/2 × (VREFP – VREFN), the ‘1’ density of The ADS1282 modulator outputs a 1s density data
the PCM data stream is at its highest. When the level stream at 90% duty cycle with the positive full-scale
of the differential analog input is near zero, the PCM input signal applied (10% duty cycle with the negative
‘0’ and ‘1’ densities are nearly equal. At the two full-scale signal). If the input is overdriven past 90%
extremes of the analog input levels (+FS and –FS), modulation, but below 100% modulation (10% and
the ‘1’ density of the PCM streams is approximately 0% for negative overdrive, respectively), the
+90% and +10%, respectively. modulator remains stable and continues to output the
1s density data stream. The digital filter may or may
The modulator second stage produces a '1' density not clip the output codes to +FS or –FS, depending
data stream designed to cancel the quantization on the duration of the overdrive. When the input
noise of the first stage. The data streams of the two returns to the normal range from a long duration
stages are then combined before the digital filter overdrive (worst case), the modulator returns
stage, as shown in Equation 5.immediately to the normal range, but the group delay
of the digital filter delays the return of the conversion
(5) result to within the linear range (31 readings for linear
phase FIR). 31 additional readings (62 total) are
M0[n] represents the most recent first-stage output required for completely settled data.
while M0[n – 1] is the previous first-stage output.
When the modulator output is enabled, the digital If the inputs are sufficiently overdriven to drive the
filter shuts down to save power. modulator to full duty cycle, all 1s or all 0s, the
modulator enters a stable saturated state. The digital
The modulator is optimized for input signals within a output code may clip to +FS or –FS, again depending
4kHz passband. As Figure 32 shows, the noise on the duration. A small duration overdrive may not
shaping of the modulator results in a sharp increase always clip the output code. When the input returns to
in noise above 6kHz. The modulator has a chopped
input structure that further reduces noise within the
passband. The noise moves out of the passband and
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: ADS1282

MFLAG
Pin
+100
(AINP AINN)-
-100
0 Time
V (% of Full-Scale)
IN
fMOD/2
MFLAG
Pin
100% FS
AINN
AINP
P
Q
IABSI
å
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
Modulator Over-Range (continued) 9.11 Modulator Over-Range Detection
(MFLAG)
the normal range, the modulator requires up to 12 The ADS1282 has a fast-responding over-range
modulator clock cycles (fMOD) to exit saturation and detection that indicates when the differential input
return to the linear region. The digital filter requires an exceeds 100% or –100% full-scale. The threshold
additional 62 conversions for fully settled data (linear tolerance is ±2.5%.The MFLAG output asserts high
phase FIR). when in an over-range condition. As Figure 33 and
In the extreme case of over-range, either input is Figure 34 illustrate, the absolute differential input is
overdriven, exceeding the voltage of either analog compared to 100% of range. The output of the
supply voltage plus an internal ESD diode drop. The comparator is sampled at the rate of fMOD/2, yielding
internal diodes begin to conduct and the signal on the the MFLAG output. The minimum MFLAG pulse width
input is clipped. When the input overdrive is removed, is fMOD/2.
the diodes recover quickly. Keep in mind that the
input current must be limited to 100mA peak or 10mA
continuous if an overvoltage condition is possible.
9.10 Modulator Input Impedance
The modulator samples the buffered input voltage
with an internal capacitor to perform conversions. The
charging of the input sampling capacitor draws a
transient current from the PGA output. The average
value of the current can be used to calculate an Figure 33. Modulator Over-Range Block Diagram
effective input impedance of REFF = 1/(fMOD × CS).
Where:
fMOD = Modulator sample frequency (CLK / 4)
CS= Input sampling capacitor (17pF, typ)
The resulting modulator input impedance for CLK =
4.096MHz is 55kΩ. The modulator input impedance
and the PGA output resistors result in a systematic
gain error of –1%. CScan vary ±20% over production
lots, affecting the gain error.
Figure 34. Modulator Over-Range Flag Operation
16 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

CLK
SYNC
MCLK(1)
M0
M1
tMCD0, 1
tSCSU
tCSHD
tCMD
tSYMD
ESD
Diodes
ESD
Diodes
11.5pF R = 85kW
(f = 1.024MHz)
EFF
MOD
AVDD
AVSS
VREFP
VREFN
R =
EFF f C´
MOD X
1
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
9.12 Modulator Output Mode 9.13 Voltage Reference Inputs
(VREFP, VREFN)
The modulator digital stream output is accessible
directly, bypassing and disabling the internal digital The voltage reference for the ADS1282 is the
filter. The modulator output mode is activated by differential voltage between VREFP and VREFN:
setting the CONFIG0 register bits FILTR[1:0] = 00. VREF = VREFP – VREFN. The reference inputs use a
Pins M0 and M1 then become the modulator data structure similar to that of the analog inputs with the
outputs and the MCLK becomes the modulator clock circuitry of the reference inputs shown in Figure 36.
output. When not in the modulator mode, these pins The average load presented by the switched
are inputs and must be tied. capacitor reference input can be modeled with an
effective differential impedance of REFF = tSAMPLE/CIN
The modulator output is composed of three signals: (tSAMPLE = 1/fMOD). Note that the effective impedance
one output for the modulator clock (MCLK) and two of the reference inputs loads the external reference.
outputs for the modulator data (M0 and M1). The
modulator clock output rate is fMOD (fCLK / 4).
Synchronization resets the MCLK phase, as shown in
Figure 35. The SYNC input is latched on the rising
edge of CLK. The MCLK resets and the next rising
edge of MCLK occurs three or five CLK periods later,
as shown in Figure 35.
The modulator output data are two bits wide, which
must be merged together before being filtered. Use
the time domain equation of Equation 5 to merge the
data outputs.
Figure 36. Simplified Reference Input Circuit
(1) MCLK = fCLK / 4.
Figure 35. Modulator Mode Timing
Table 4. Modulator Output Timing For Figure 35
PARAMETER DESCRIPTION MIN TYP MAX UNIT
tMCD0, 1 MCLK rising edge to M0, M1 valid propagation delay(1) 100 ns
CLK rising edge to MCLK rising edge reset time (after
tCMD 3 1/fCLK
synchronization)
tCSHD CLK to SYNC hold time to not latch on CLK edge 10 ns
tSCSU SYNC to CLK setup time to latch on CLK edge 10 ns
tSYMD SYNC to stable bit stream 16 1/fMOD
(1) Load on M0 and M1 = 20pF || 100kΩ.
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADS1282

Sinc Filter
(Decimate by
8 to 128)
Coefficient Filter
(FIR)
(Decimate by 32)
High-Pass Filter
(IIR)
Filter
MUX To Output Register
From Modulator
Direct Modulator
Bit Stream
30
3
CAL
Block
Code
Clip 31
Filter Mode
(Register Select)
H(Z) = 1 Z-
-N
N(1 Z-)
-1
5
AVSS 300mV < (VREFP or VREFN) < AVDD + 300mV-
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
The ADS1282 reference inputs are protected by ESD Digital Filter (continued)
diodes. In order to prevent these diodes from turning Table 5. Digital Filter Selection
on, the voltage on either input must stay within the
range shown in Equation 6:FILTR[1:0] BITS DIGITAL FILTERS SELECTED
00 Bypass; modulator output mode
01 Sinc
10 Sinc + FIR
(6) Sinc + FIR + HPF
11
Note that the minimum valid input for VREFN is (low-pass and high-pass)
AVSS – 0.1V and maximum valid input for VREFP is
AVDD + 0.1V. 9.14.1 Sinc Filter Stage (Sinx/X)
A high-quality +5V reference voltage is necessary for The sinc filter is a variable decimation rate, fifth-order,
achieving the best performance from the ADS1282. low-pass filter. Data are supplied to this section of the
Noise and drift on the reference degrade overall filter from the modulator at the rate of fMOD (fCLK/4).
system performance, and it is critical that special care The sinc filter attenuates the high-frequency noise of
be given to the circuitry generating the reference the modulator, then decimates the data stream into
voltages in order to achieve full performance. See the parallel data. The decimation rate affects the overall
Application Information section for reference data rate of the converter; it is set by the DR[2:0]
recommendations. register bits, as shown in Table 6.
9.14 Digital Filter Equation 7 shows the scaled Z-domain transfer
function of the sinc filter.
The digital filter receives the modulator output and
decimates the data stream. By adjusting the amount
of filtering, tradeoffs can be made between resolution
and data rate: filter more for higher resolution, filter
less for higher data rate.
The digital filter is comprised of three cascaded filter Where:
stages: a variable-decimation, fifth-order sinc filter; a N = decimation ratio (7)
fixed-decimation FIR, low-pass filter (LPF) with
selectable phase; and a programmable, first-order, Table 6. Sinc Filter Data Rates (CLK = 4.096MHz)
high-pass filter (HPF), as shown in Figure 37.
DECIMATION SINC DATA RATE
The output can be taken from one of the three filter DR[2:0] REGISTER RATIO (N) (SPS)
blocks, as Figure 37 shows. To implement the digital 000 128 8,000
filter completely off-chip, select the filter bypass
setting (modulator output). For partial filtering by the 001 64 16,000
ADS1282, select the sinc filter output. For complete 010 32 32,000
on-chip filtering, activate both the sinc and FIR 011 16 64,000
stages. The HPF can then be included to remove dc 100 8 128,000
and low frequencies from the data. Table 5 shows the
filter options.
Figure 37. Digital Filter and Output Code Processing
18 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282

Output
FIR Stage 2
Decimate by 2
FIR Stage 1
Decimate by 2
Sinc
Filter
FIR Stage 4
Decimate by 2
FIR Stage 3
Decimate by 4
Linear
Minimum
PHASE Select
Coefficients
0 1 2
Normalized Frequency (f /f )
IN DATA
0
-20
-40
-60
-80
-100
-120
-140
Gain (dB)
3 4 5
Gain (dB)
Normalized Frequency (f /f )
IN DATA
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0 0.05 0.10 0.20
0.15
½ ½H(f) =
5
sin p ´N f
fMOD
N sin p ´ f
fMOD
ADS1282
www.ti.com SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015
Equation 8 shows the frequency domain transfer
function of the sinc filter.
(8)
where:
N = decimation ratio (see Table 6)
The sinc filter has notches (or zeroes) that occur at
the output data rate and multiples thereof. At these
frequencies, the filter has zero gain. Figure 38 shows Figure 39. Sinc Filter Roll-Off
the frequency response of the sinc filter and
Figure 39 shows the roll-off of the sinc filter. 9.14.2 FIR Stage
The second stage of the ADS1282 digital filter is an
FIR low-pass filter. Data are supplied to this stage
from the sinc filter. The FIR stage is segmented into
four sub-stages, as shown in Figure 40. The first two
sub-stages are half-band filters with decimation ratios
of 2. The third sub-stage decimates by 4 and the
fourth sub-stage decimates by 2. The overall
decimation of the FIR stage is 32. Note that two
coefficient sets are used for the third and fourth
sections, depending on the phase selection. Table 34
(in the Appendix section at the end of this document)
lists the FIR stage coefficients. Table 7 lists the data
rates and overall decimation ratio of the FIR stage.
Table 7. FIR Filter Data Rates
Figure 38. Sinc Filter Frequency Response DECIMATION FIR DATA RATE
DR[2:0] REGISTER RATIO (N) (SPS)
(N = 32) 000 4096 250
001 2048 500
010 1024 1000
011 512 2000
100 256 4000
Figure 40. FIR Filter Sub-Stages
Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: ADS1282

0 5 10
Time Index (1/f )
DATA
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-0.2
Amplitude (dB)
15 20 25 30 35 40 45 50 55 60 65
Linear Phase Filter
Minimum Phase Filter
0 0.1 0.2
Normalized Input Frequency (f /f )
IN DATA
20
0
-
-
-
-
-
-
-
-
20
40
60
80
100
120
140
160
Magnitude (dB)
1.00.3 0.4 0.5 0.6 0.7 0.8 0.9
0 0.05
Normalized Input Frequency (f /f )
IN DATA
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
-
-
-
-
Magnitude (mdB)
0.10 0.15 0.20 0.400.25 0.30 0.35
ADS1282
SBAS418I –SEPTEMBER 2007–REVISED MARCH 2015 www.ti.com
As shown in Figure 41, the FIR frequency response back (or alias) into the passband and cause errors. A
provides a flat passband to 0.375 of the data rate low-pass signal filter reduces the effect of aliasing.
(±0.003dB passband ripple). Figure 42 shows the Often, the RC low-pass filter provided by the PGA
transition from passband to stop band. output resistors and the external capacitor connected
to CAPP and CAPN provides sufficient signal
attenuation.
9.15 Group Delay and Step Response
The FIR block is implemented as a multi-stage FIR
structure with selectable linear or minimum phase
response. The passband, transition band, and stop
band responses of the filters are nearly identical but
differ in the respective phase responses.
9.15.1 Linear Phase Response
Linear phase filters exhibit constant delay time versus
input frequency (that is, constant group delay). Linear
phase filters have the property that the time delay
from any instant of the input signal to the same
instant of the output data is constant and is
Figure 41. FIR Passband Magnitude Response independent of the signal nature. This filter behavior
(fDATA = 500Hz) results in essentially zero phase error when analyzing
multi-tone signals. However, the group delay and
settling time of the linear phase filter are somewhat
larger than the minimum phase filter, as shown in
Figure 43.
Figure 42. FIR Transition Band Magnitude
Response
Although not shown in Figure 42, the passband Figure 43. FIR Step Response
response repeats at multiples of the modulator
frequency (NfMOD – f0and NfMOD + f0, where N = 1, 2,
etc. and f0= passband). These image frequencies, if
present in the signal and not externally filtered, fold
20 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ADS1282