Texas Instruments HPA070 User manual

User’s Guide
1
TPS40055-Based Design Converts
12-V Bus to 1.8 V at 15 A (HPA070)
User’s Guide

2
EVM IMPORTANT NOTICE
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Copyright 2004, Texas Instruments Incorporated

3
DYNAMIC WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 VDC to 14 VDC.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
If there are questions concerning the input range, please contact a TI field representative prior to connecting
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Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM
output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 50°C. The EVM
is designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated

SLUU186 − March 2004
4TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
TPS40055-Based Design Converts 12-V Bus to
1.8 V at 15 A (HPA070)
Mark Dennis System Pow
er
Contents
1 Introduction 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Features 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Schematic 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Component Selection 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Test Setup 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Test Results and Performance Data 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 EVM Assembly Drawing and PCB Layout 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 List of Materials 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 References 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction
In many modern electronic applications there is a growing demand for circuits to convert a12-V bus to digital
voltages as low as, but not limited to 1.8 V. The current requirements can range from below 1 A to over 15 A.
For high-efficiency and small circuit size the TPS40055 wide-input synchronous buck controller can be used
to provide the necessary control and drive functions to implement these converters. The TPS40055EVM−001
operates at 300 kHz and delivers 1.8 V at 15 A with efficiency over 90% for much of the load range, and a full
load efficiency of 88%.
The TPS40055 synchronous buck controller offers a variety of user programmable functions such as operating
frequency, soft-start time, voltage feed-forward, high-side current limit, and external loop compensation. This
controller also provides a regulated 10-V bias voltage which supplies onboard drivers for the N-channel switch
and synchronous rectifier MOSFETs, utilizing adaptive gate drive logic to prevent cross conduction of the power
MOSFETs.[1]
2 Features
The specification of this design is as follows:
D92% peak efficiency at 6 A
D88% peak efficiency at 15 A
D1.8V output at 15 A
DVIN range from 10 VDC to 14 VDC
DSmall circuit size 1.4” x 2.5” SMT design, components on single side
DLine/load regulation < 0.5%
DHigh-frequency 300-kHz operation
DTransient deviation 60 mV with 10-A load step

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TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
3 Schematic
++
Figure 1. TPS40055EVM−001 (HPA070) Schematic

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6TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
4 Component Selection
4.1 TPS40055 Device Selection
The TPS4005x family of parts offers a range of output current configurations including source only (TPS40054),
source/sink (TPS40055), or source/sink with VOUT prebias (TPS40057). In this converter the TPS40055 with
source/sink capability is selected. This serves to maintain continuous inductor ripple current all the way to zero
load to improve the small signal loop response by preventing the inductor current from transitioning to the
discontinuous current mode.
The TPS4005x family is packaged in TI’s PWP PowerPAD thermally enhanced package which should be
soldered to the PCB using standard solder flow techniques. The PowerPADtechnology uses a thermally
conductive epoxy to attach the integrated circuit die to the leadframe die pad, which is exposed on the bottom
of the completed package. The PWP PowerPAD package has a θJC = 2°C/W which helps keep the junction
temperature rise relatively low even with the power dissipation inherent in the onboard MOSFET drivers. This
power loss is proportional to switching frequency, drive voltage, and the gate charge needed to enhance the
N-channel MOSFETs. Effective heat removal allows the use of ultra-small packaging while maintaining high
component reliability.
The technical brief, PowerPAD Thermally Enhanced Package[2] contains more information on the PowerPAD
package.
4.2 Frequency of Operation
The clock oscillator frequency for the TPS40055 is programmed with a single resistor from RT (pin 2) to signal
ground. The following equation (1) from the datasheet allows selection of RT in kΩfor a given switching
frequency in kHz.
RT+R2 +1
fSW 17.82 10*6*23 (kW)
For 300-kHz operation, R2 is selected to be 165 kΩ.
For a particular operating frequency, the PWM ramp time must be programmed via the resistor RKFF connected
to VIN. Also, the selection of RKFF programs the VIN voltage at which the circuit starts operation. This prevents
the circuit from starting at low voltages, which can lead to current flow larger than desired. RKFF is programmed
using equation (2).
RKFF +R6 +ǒVIN(min) *3.5Ǔ ǒ58.14 RT)1340Ǔ(kW)
Where VIN(min) is the minimum startup input voltage, and RTis in kΩ. Note that internal tolerances have been
incorporated into this equation, so the actual VIN(min) of the input voltage should be used. For an oscillator
frequency of 300-kHz, the RKFF value of 71.5 kΩis selected.
(1)
(2)

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TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
4.3 UVLO Circuitry
The user programmable UVLO built into the TPS4005x provides hysteresis for transients shorter than a total
count of seven cycles. If the input voltage to the converter can be slowly rising around the minimum VIN range,
external hysteresis can be incorporated to prevent multiple on/off cycles during startup or shutdown. These
on/off cycles are a result of line impedance external to the EVM causing VIN to the module to drop when under
load, which causes the programmable UVLO threshold to be crossed repetitively.
In this converter, C1 and D1 are added to form a peak detector from the lower gate drive which is only active
when the converter is operating. This provides a bias source to deliver hysteresis current from the peak detector
voltage to the lower KFF voltage of 3.5 V, enabling the designer to alter the programmable UVLO shutdown
point. The bias is not present during startup, so the circuit starts as expected from the RKFF calculation.
In this application, R4 is selected to provide a hysteresis current of 20% IKFF. R4 can be calculated from equation
(3).
RHYS +R4 +RKFF ǒVPD *3.5Ǔ
0.2 ǒVIN(min) *3.5Ǔ
where
DVPD is the voltage on the peak detector
DVIN(min) is the desired start voltage used in the determination of RKFF
In a typical case, VPD = 8V, and R4 is found to be 247 kΩ, and a standard value of 243kΩis selected. Testing
shows the startup voltage to be 9.2 V, and the shutdown voltage to be 8.5 V.
4.4 Inductance Value
The output inductor L1 value used in the circuit of Figure 2 was selected from equation (4).
L+VOUT
f IRIPPLE 1*VOUT
VIN(min)
in which IRIPPLE is usually chosen to be in the range between 10% and 40% of IOUT. With IRIPPLE = 20% of
IOUT(max) there is a ripple current of 3 A, and the inductance value is 1.7 µH.
4.5 Input capacitor selection
Bulk input capacitor selection is based on allowable input voltage ripple and required RMS current carrying
capability. In typical buck converter applications, the converter is fed from an upstream power converter with
its own output capacitance. In this converter, ceramic capacitors capable of meeting circuit requirements are
provided onboard. For this power level, input voltage ripple of approximately 250 mV is reasonable, and the
minimum capacitance is calculated in (5).
CIN +I Dt
DV+I VO
DV VIN fS+15 A 1.8 V
0.25 V 10 V 300 kHz +36 mF
Also consider the RMS current rating required for the input capacitors (6).
i^IOUT D
Ǹ+IOUT VOUT
VIN
Ǹ+15 1.8
10
Ǹ+6.4 A
To meet this requirement with the smallest cost and size two 22 µF, 16 V, X5R ceramic capacitors (C12, C14)
are installed on the board. In the 1812 case, the parts are able to carry approximately 4 ARMS each. These
capacitors function as power bypass components and should be located close to the MOSFET packages to
keep the high-frequency current flow in a small, tight loop.
(3)
(4)
(5)
(6)

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8TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
4.6 Output Capacitor Selection
Selection of the output capacitor is based on many application variables, including function, cost, size, and
availability. The minimum allowable output capacitance is determined by the amount of inductor ripple current
and the allowable output ripple, as given in equation (7).
COUT(min) +IRIPPLE
8 f VRIPPLE +3A
8 300 kHz 15 mV +83 mF
In this design, COUT(min) is 83 µF with VRIPPLE=15 mV to allow for some margin. However, this only affects the
capacitive component of the ripple voltage, and the final value of capacitance is generally influenced by ESR
and transient considerations. The voltage component due to the capacitor ESR.
CESR vVRIPPLE
IRIPPLE +15 mA
3A +5mW
An additional consideration in the selection of the output inductor and capacitance value can be derived from
examining the transient voltage overshoot which can be initiated with a load step from full load to no load. By
equating the inductive energy with the capacitive energy the equation (9) can be derived:
COvL I2
V2+
L ǒǒIOHǓ2*ǒIOLǓ2Ǔ
ǒVfǓ2*ǒViǓ2+1.7 mH (15 A)
ǒ(1.9 V)2*(1.8 V)2Ǔ+1034 mF
where
•IOH = full load current
•IOL = no load current
•Vf= allowed transient voltage rise
•Vi= initial voltage
For compactness while maintaining transient response capability, two 470-µF POSCAP capacitors (C16, C17)
are fitted in parallel. The total ESR of these capacitors is approximately 5 mΩ. An additional 47-µF, 6.3-V ceramic
capacitor C15 is placed in parallel with the POSCAPs to help suppress high frequency noise generated by the
fast current transitions as the current switches between the input and output circuits during each switching cycle.
4.7 MOSFET selection
Proper MOSFET selection is essential to optimize circuit efficiency. To operate with high current it is important
to choose a package which allows the generated heat to be removed from the package as easily as possible.
Various MOSFETs with a package similar to the SO−8 footprint are considered for this application, and devices
with reduced junction-case thermal impedance are selected.
For the upper switch Q1, a Hitachi HAT2168H MOSFET with low gate charge (typically 27 nC at 10 V) and with
an RDS(on) of 6 mΩis selected to keep the switching losses to a minimum. The low-side rectifier switch Q2 was
chosen as a Hitachi HAT2167H, which has slightly more gate charge (43 nC at 10 V) but lower RDS(on) = 4.2
mΩto minimize conduction losses. A schottky diode, D2, is placed across Q2 in this high current design to carry
some of the high circulating current during short circuit conditions.
(7)
(8)
(9)

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TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
4.8 Short Circuit Protection
The TPS40055 implements short circuit protection by comparing the voltage across the topside MOSFET while
it is ON to a voltage developed across RLIM due to an internal current source of 10 µA inside pin 16. Both of these
voltages are negative with respect to VIN. From the datasheet equation, RLIM is defined as:
RLIM +R9 +IOC RDS(on) (max)
1.12 ISINK +VOS ISINK +(W)
where
•IOC is the overcurrent set point equal to the DC output current plus one-half the inductor ripple current
•VOS is the overcurrent comparator offset, and Isink is the current into ILIM (pin 16).
Using worst case tolerances the value of RLIM should be maximized to ensure that the converter can deliver full
rated current under all conditions. In a worst case condition, RLIM=R9 and
RLIM +(15 A )1.5 A) (7.9 mW 1.45)
1.12 8.65 mA)*30 mV 8.65 mA+16.0 kW
The standard value of 16.2 kΩwas selected. This ensures that we can deliver a minimum of 15 A before current
limit is activated. There is also a small capacitor, C7, placed in parallel with R9 to filter the signal.
4.9 Snubber Component Selection
Initially, the junction of Q1, Q2, and L1 was ringing at a frequency near 100 MHz with a peak voltage near 30
V. This was due to the extremely fast switching speed of the MOSFETs and the lack of any cross−conduction.
C13 was added to shunt the high-frequency ringing to ground and the peak voltage is now below 25 V.
4.10 Compensation Components
The TPS40055 uses voltage mode control with feed-forward in conjunction with a high-frequency error amplifier
to implement closed loop control. The power circuit L-C double pole corner frequency fCoccurs at 3.8 kHz, and
the output capacitor ESR zero is located at approximately 38 kHz. The feedback compensation network is
implemented to provide two zeroes and three poles. The first pole is placed at the origin to improve DC
regulation.
The first zero is placed at 2.8 kHz, just below the L-C corner frequency.
fZ1 +1
2p R5 C5
The second zero is selected to be coincident with the L-C corner frequency of 3.8 kHz,
fZ2 +1
2p (R7 )R8) C6
The second pole is placed near the ESR zero frequency at 37 kHz.
fP1 +1
2p R5 ǒC4 C5
C4)C5Ǔ
and the third pole is placed at 150 kHz, which is one-half the switching frequency.
fP2 +1
2p R8 C6
(10)
(11)
(12)
(13)
(14)
(15)

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10 TPS40055-Based Design Converts 12-V Bus to 1.8 V at 15 A (HPA070)
5 Test Setup
Figure 2 illustrates the basic test setup needed to evaluate the TPS40055EVM−001.
5.1 DC Input Source
The input voltage source should be capable of supplying between 10 VDC and 14 VDC and rated for at least 4
A of current. For best results the input leads should be made with a wire of 18AWG or larger.
5.2 Output Load
The output load can be either an electronic load or a resistive load configured to draw between 0 A and 15 A.
The output leads should be made with a wire of 16AWG or larger diameter wire. Monitor the output voltage on
the PCB by connecting a voltmeter to TP9 and TP10 to prevent voltage drops through PCB traces and the output
terminal block which can lead to substantial measurement errors.
5.3 Oscilloscope Probe Test Jacks
An oscilloscope probe test jack (TP8) has been included to allow monitoring the ourput voltage ripple.
5.4 Fan
There is no cover to prevent the user from probing the internal circuit nodes. There are components that can
get hot to the touch (above 60°C) in normal operation. A small fan delivering more than 15 cfm should be used
when operating at and near full load.
+
−
+−
Fan
VIN
10 V to 14 V VIN Test Points
TP1 = VIN(+)
TP2 = VIN(−)
VOUT Test Points
TP9 = VOUT(+)
TP10 = VOUT(−)
VLOAD
1.8 V / 15 A
Figure 2. Test Setup