Texas Instruments LM5157 Q1 Series User manual

LM5157x-Q1 2.2-MHz Wide VIN 50-V Boost/SEPIC/Flyback Converter with Dual
Random Spread Spectrum
1 Features
• AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C TA
•Functional Safety-Capable
–Documentation available to aid functional safety
system design
• Suited for wide operating range for car battery
applications
– 2.9-V to 45-V input operating range
– 48-V maximum output (50-V abs max)
– Minimum boost supply voltage of 1.5 V when
BIAS ≥ 2.9 V
– Input transient protection up to 50 V
– Minimized battery drain
• Low shutdown current (IQ ≤ 2.6 µA)
• Low operating current (IQ ≤ 700 µA)
• Small solution size and low cost
– Maximum switching frequency up to 2.2 MHz
– 16-pin QFN package (3 mm × 3 mm) with
wettable flanks
– Integrated error amplifier allows primary-side
regulation without optocoupler (flyback)
– Minimized undershoot during cranking (start-
stop application)
– Accurate current limit (see the Device
Comparison Table)
• EMI mitigation
– Selectable dual random spread spectrum
– Lead-less package
• Higher efficiency with low-power dissipation
– 45-mΩ RDSON switch
– Fast switching, small switching loss
• Avoid AM band interference and crosstalk
– Optional clock synchronization
– Dynamically programmable wide switching
frequency from 100 kHz to 2.2 MHz
• Integrated protection features
– Constant current limiting over input voltage
– Selectable hiccup mode overload protection
– Programmable line UVLO
– OVP protection
– Thermal shutdown
• Accurate ±1% accuracy feedback reference
• Adjustable soft start
• PGOOD indicator
• Create a custom design using the LM5157x-Q1
with the WEBENCH® Power Designer
2 Applications
•Battery-powered wide input boost, SEPIC, flyback
converter
• Automotive voltage stabilizer in SEPIC
•Automotive start-stop application
•Automotive emergency call application/backup
battery booster
•High voltage LiDAR power supply
•Automotive LED bias supply
•Multiple-output flyback without optocoupler
• Holdup capacitor charger
•Audio amplifier power supply
• Piezo driver/motor driver bias supply
3 Description
The LM5157x-Q1 device is a wide input range, non-
synchronous boost converter with integrated 50-V,
6.5-A (LM5157-Q1) or 50-V, 4.33-A (LM51571-Q1)
power switch.
The device can be used in boost, SEPIC, and flyback
topologies. The device can start up from a single-cell
battery with a minimum of 2.9 V. It can operate with
the input supply voltage as low as 1.5 V if the BIAS
pin is greater than 2.9 V.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
LM5157-Q1 WQFN (16) 3.00 mm × 3.00 mm
LM51571-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VLOAD
VSUPP LY
Optional
BIAS SW
AGND
FB
COMP
SS
RT
UVLO
VCC
PGND MODE
PGOOD
Typical SEPIC Application
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 2
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings ....................................... 6
8.2 ESD Ratings .............................................................. 6
8.3 Recommended Operating Conditions ........................7
8.4 Thermal Information ...................................................7
8.5 Electrical Characteristics ............................................7
8.6 Typical Characteristics.............................................. 10
9 Detailed Description......................................................13
9.1 Overview................................................................... 13
9.2 Functional Block Diagram......................................... 14
9.3 Feature Description...................................................14
9.4 Device Functional Modes..........................................26
10 Application and Implementation................................ 27
10.1 Application Information........................................... 27
10.2 Typical Application.................................................. 27
10.3 System Examples................................................... 30
11 Power Supply Recommendations..............................34
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Examples.................................................... 36
13 Device and Documentation Support..........................37
13.1 Device Support....................................................... 37
13.2 Documentation Support.......................................... 37
13.3 Receiving Notification of Documentation Updates..37
13.4 Support Resources................................................. 38
13.5 Trademarks.............................................................38
13.6 Electrostatic Discharge Caution..............................38
13.7 Glossary..................................................................38
14 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2020) to Revision A (March 2021) Page
• Changed the LM51571-Q1 device status from Advance Information to Production Data.................................. 1
5 Description (continued)
The BIAS pin operates up to 45 V (50-V absolute maximum) for automotive load dump. The switching frequency
is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes
AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the
power supply, the device provides a selectable Dual Random Spread Spectrum, which reduces the EMI over a
wide frequency range.
The device features an accurate peak current limit over the input voltage, which avoids overdesigning the power
inductor. Low operating current and pulse-skipping operation improve efficiency at light loads.
The device has built-in protection features such as overvoltage protection, line UVLO, thermal shutdown, and
selectable hiccup mode overload protection. Additional features include low shutdown IQ, programmable soft
start, precision reference, power-good indicator, and external clock synchronization.
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6 Device Comparison Table
DEVICE OPTION MINIMUM PEAK CURRENT LIMIT MAXIMUM SW VOLTAGE
LM5157-Q1 6.5 A 48 V (50-V abs max)
LM51571-Q1 4.33 A
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7 Pin Configuration and Functions
EP
VCC
COMP
PGND NC
SW
SS
BIAS
RT
FB
EN/UVLO/SYNC
SW
PGOOD
SW
AGND
MODE
PGND 1
2
3
4
5 6 7
14
8
13
16 15
12
11
10
9
Figure 7-1. 16-Pin WQFN With Wettable Flanks RTE Package (Top View)
Table 7-1. Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1, 16 PGND P Power ground pin. Source connection of the internal N-channel power MOSFET
2 VCC P Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver.
Connect a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor from this pin to PGND.
3 BIAS P Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
4 PGOOD O Power-good indicator. An open-drain output that goes low if FB is below the undervoltage threshold
(VUVTH). Connect a pullup resistor to the system voltage rail.
5 RT I Switching frequency setting pin. The switching frequency is programmed by a single resistor
between RT and AGND.
6UVLO/
SYNC/EN I
Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN).
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be
programmed by connecting this pin to the supply voltage through a voltage divider. If a
programmable UVLO is used, connect the low-side UVLO resistor to AGND. This pin must not be left
floating. Connect to the BIAS pin if not used.
External synchronization clock input pin. The internal clock can be synchronized to an external clock
by applying a negative pulse signal into the pin.
7 AGND G Analog ground pin. Connect to the analog ground plane through a wide and short path.
8 COMP O Output of the internal transconductance error amplifier. Connect the loop compensation components
between this pin and AGND.
9 FB I Inverting input of the error amplifier. Connect a voltage divider to set output voltage in boost, SEPIC,
or primary-side regulated flyback topologies. Connect the low-side feedback resistor close to AGND.
10 SS I
Soft-start time programming pin. An external capacitor and an internal current source set the ramp
rate of the internal error amplifier reference during soft start. Connect the ground connection of the
capacitor to AGND.
11 MODE I
MODE = 0 V or connect to AGND during initial power up. Hiccup mode protection is disabled and
spread spectrum is disabled.
MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is enabled and spread spectrum is enabled.
MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is enabled and spread spectrum is disabled.
MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is disabled and spread spectrum is enabled.
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Table 7-1. Pin Functions (continued)
PIN TYPE(1) DESCRIPTION
NO. NAME
12, 13,
14 SW Switch pin. Drain connection of the internal N-channel power MOSFET
15 NC — No internal electrical contact. Optionally connect to PGND for improved thermal conductivity.
— EP — Exposed pad of the package. The exposed pad must be connected to AGND and the large ground
copper plane to decrease thermal resistance.
(1) G = Ground, I = Input, O = Output, P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
MIN MAX UNIT
Input
BIAS to AGND –0.3 50
V
UVLO to AGND –0.3 VBIAS + 0.3
SS, RT to AGND(2) –0.3 3.8
FB to AGND –0.3 4.0
MODE to AGND –0.3 3.8
PGND to AGND –0.3 0.3
Output
VCC to AGND –0.3 5.8(3)
V
PGOOD to AGND(4) –0.3 18
COMP to AGND(5) –0.3
SW to AGND (DC) –0.3 50
SW to AGND (6 ns transient) –4.0
Junction temperature, TJ (6) –40 150 °C
Storage temperature, Tstg –55 150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) This pin is not specified to have an external voltage applied.
(3) Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.
(4) The maximum current sink is limited to 1 mA when VPGOOD > VBIAS.
(5) This pin has an internal max voltage clamp which can handle up to 1.6 mA.
(6) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.2 ESD Ratings
VALUE UNIT
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2 ±2000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
All pins ±500
Corner pins ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range(1)
MIN NOM MAX UNIT
VSUPPLY Boost converter input (when BIAS ≥ 2.9 V) 1.5 45 V
VLOAD Boost converter output VSUPPLY 48(2) V
VBIAS BIAS input(3) 2.9 45 V
VUVLO UVLO input 0 45 V
VFB FB input 0 4.0 V
ISW Switch current 0 See note(4) A
fSW Typical switching frequency 100 2200 kHz
fSYNC Synchronization pulse frequency 100 2200 kHz
TJOperating junction temperature(5) –40 150 °C
(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.
(2) Boost converter output can be up to 48 V, but the SW pin voltage should be less than or equal to 50 V during transient.
(3) BIAS pin operating range is from 2.9 V to 45 V when VCC is supplied from the internal VCC regulator. When the VCC pin is directly
connected to the BIAS pin, the device requires minimum 2.85 V at the BIAS pin to start up, and the BIAS pin operating range is from
2.75 V to 5.5 V after starting up.
(4) Maximum switch currrent is limited by pre-programmed peak current limit (ILIM) , and is ensured when TJ < TTSD
(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.4 Thermal Information
THERMAL METRIC(1)
LM5157x-Q1
UNITRTE(QFN)
16 PINS
RθJA Junction-to-ambient thermal resistance (LM5157EVM-BST) 32.7 °C/W
RθJA Junction-to-ambient thermal resistance 45.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.3 °C/W
RθJB Junction-to-board thermal resistance 20.0 °C/W
ΨJT Junction-to-top characterization parameter (LM5157EVM-BST) 0.6 °C/W
ΨJT Junction-to-top characterization parameter 0.8 °C/W
ΨJB Junction-to-board characterization parameter (LM5157EVM-BST) 14.8 °C/W
ΨJB Junction-to-board characterization parameter 20.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS) BIAS shutdown current VBIAS = 12 V, VUVLO = 0 V 2.6 5 μA
IOPERATING(BIAS) BIAS operating current VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF,
RT = 220 kΩ 700 775 μA
VCC REGULATOR
VVCC-REG VCC regulation VBIAS = 8 V, IVCC = 18 mA 4.66 4.9 5.14 V
VVCC-
UVLO(RISING)
VCC UVLO threshold VCC rising 2.75 2.8 2.85 V
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC UVLO hysteresis VCC falling 0.1 V
ENABLE
VEN(RISING) Enable threshold EN rising 0.4 0.52 0.7 V
VEN(FALLING) Enable threshold EN falling 0.33 0.49 0.63 V
VEN(HYS) Enable hysteresis EN falling 0.03 V
UVLO/SYNC
VUVLO(RISING) UVLO/SYNC threshold UVLO rising 1.425 1.5 1.575 V
VUVLO(FALLING) UVLO/SYNC threshold UVLO falling 1.370 1.45 1.520 V
VUVLO(HYS) UVLO/SYNC threshold hysteresis UVLO falling 0.05 V
IUVLO UVLO hysteresis current VUVLO = 1.6 V 4 5 6 μA
MODE, SPREAD SPECTRUM
FSW modulation (upper limit) 7.8%
FSW modulation (lower limit) –7.8%
SS
ISS Soft-start current 9 10 11 μA
SS pulldown switch RDSON 50 Ω
PULSE WIDTH MODULATION
fsw1 Switching frequency RT = 220 kΩ 85 100 115 kHz
fsw2 Switching frequency RT = 49.3 kΩ 388 440 492 kHz
fsw3 Switching frequency RT = 9.09 kΩ 1980 2200 2420 kHz
tON(MIN) Minimum on time RT = 9.09 kΩ 80 ns
DMAX1 Maximum duty cycle limit RT = 9.09 kΩ 80% 85% 90%
DMAX2 Maximum duty cycle limit RT = 220 kΩ 90% 93% 96%
RT regulation voltage 0.5 V
CURRENT LIMIT
ILIM Internal MOSFET current limit LM5157 6.5 7.5 8.5 A
Internal MOSFET current limit LM51571 4.33 5 5.67 A
HICCUP MODE PROTECTION
Hiccup enable cycles 64 Cycles
Hiccup timer reset cycles 8 Cycles
ERROR AMPLIFIER
VREF FB reference 0.99 1 1.01 V
Gm Transconductance 2 mA/V
COMP sourcing current VCOMP = 1.2 V 180 μA
COMP clamp voltage COMP rising (VUVLO = 2.0 V) 2.5 2.8 V
COMP clamp voltage COMP falling 1 1.1 V
ACS ΔVCOMP/ΔISW 0.095
OVP
VOVTH Overvoltage threshold FB rising (referece to VREF) 107% 110% 113%
Overvoltage threshold FB falling (referece to VREF) 105%
PGOOD
PGOOD pulldown switch RDSON 1-mA sinking 70 Ω
VUVTH Undervoltage threshold FB falling (referece to VREF) 87% 90% 93%
Undervoltage threshold FB rising (referece to VREF) 95%
POWER SWITCH
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
rDS(ON) Internal MOSFET on-resistance VBIAS = 12 V 45 90 mΩ
VBIAS = 3.5 V 47 95 mΩ
Leakage current VSW = 12 V 1200 nA
THERMAL SHUTDOWN
TTSD Thermal shutdown threshold Temperature rising 175 °C
Thermal shutdown hysteresis 15 °C
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8.6 Typical Characteristics
Figure 8-1. BIAS Shutdown Current vs VBIAS Figure 8-2. BIAS Shutdown Current vs
Temperature
Figure 8-3. BIAS Operating Current vs Temperature Figure 8-4. VVCC vs VBIAS
Figure 8-5. VVCC vs IVCC Figure 8-6. ISS vs Temperature
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Figure 8-7. EN Threshold vs Temperature Figure 8-8. UVLO Threshold vs Temperature
Figure 8-9. FB Reference vs Temperature Figure 8-10. Frequency vs RT Resistance
Figure 8-11. Frequency vs Temperature Figure 8-12. Current Limit Threshold vs
Temperature
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Figure 8-13. Peak Current Limit vs Duty Cycle
Figure 8-14. Internal MOSFET Drain Source On-
state Resistance vs Temperature
Figure 8-15. Minimum On Time vs Frequency Figure 8-16. Maximum Duty Cycle Limit vs
Frequency
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9 Detailed Description
9.1 Overview
The LM5157x-Q1 device is a wide input range, non-synchronous boost converter that uses peak-current-mode
control. The device can be used in boost, SEPIC, and flyback topologies.
The device can start up from a single-cell battery with a minimum of 2.9 V. It can operate with input supply
voltage as low as 1.5 V if the BIAS pin is greater than 2.9 V. The internal VCC regulator also supports BIAS pin
operation up to 45 V (50-V absolute maximum) for automotive load dump. The switching frequency is
dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes
AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the
power supply, the device provides an optional dual random spread spectrum, which reduces the EMI over a wide
frequency span.
The device features an accurate current limit over the input voltage range. Low operating current and pulse
skipping operation improve efficiency at light loads.
The device also has built-in protection features such as overvoltage protection, line UVLO, and thermal
shutdown. Selectable hiccup mode overload protection protects the converter during prolonged current limit
conditions. Additional features include the following:
• Low shutdown IQ
• Programmable soft start
• Precision reference
• Power good indicator
• External clock synchronization
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9.2 Functional Block Diagram
BIAS
VCC
VLOAD
VSUPP LY
VCC
Regula tor
BIAS
VCC_EN
VCC
UVLO
VCC_OK
FB
CIN COUT
LM
RLOAD
D1
MODE
VCS
S Q
Q
R
S Q
Q
R
S Q
Q
R
Clock Gen erator
Spread Spectrum
AGND PGND
Clock_Syn c
+
±
+
±
+
±
+
±
+
±
+
±
ICS
ILIM
VCS
PWM
Comparator
C/L Comparator
+
±
+
±
+
±
RCOMP
CCOMP
RT
COMP
FB
SS
+
VREF
ISS
Hiccup
Mode
IUVLO
EN
/UVLO
/SYNC
+
±
+
±
+
±
+
±
+
±
+
±
VEN
VCC_EN
SYNC
Detector Clock_Sync
TSD
VCC_OK
Ready
VSUPP LY
VUVLO
CSS
RUVLOT
RUVLOB
RFBT
RFBB
CVCC
RT
SW
-+Gain
= ACS
FB
PGOOD
+
±
+
±
+
±
+
±
+
±
+
±
VOVTH
VUVTH
OVP
ICS
Gm
1.1V+VSLOPE
AGND
MODE
Selection
MODE
Selection
RVCC
9.3 Feature Description
9.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
The device has a dual-level EN/UVLO circuit. During power on, if the BIAS pin voltage is greater than 2.7 V and
the UVLO pin voltage is between the enable threshold (VEN) and the UVLO threshold (VUVLO) for more than 1.5
µs (see Section 9.3.6 for more details), the device starts up and an internal configuration starts. The device
typically requires a 90-µs internal start-up delay before entering standby mode. In standby mode, the VCC
regulator and RT regulator are operational, the SS pin is grounded, and there is no switching at the SW pin.
IUVLO
EN
/UVLO
/SYNC
+
±
+
±
VEN
VCC_EN
VSUPPLY
VUVLO
RUVLOT
RUVLOB
RUN
Figure 9-1. Line UVLO and Enable
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When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a soft-start
sequence starts if the VCC voltage is greater than VCC UV threshold (VVCC-UVLO). UVLO hysteresis is
accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched
on or off. When the UVLO pin voltage exceeds the UVLO threshold, the UVLO hysteresis current source is
enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO
threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin
voltage is less than the enable threshold (VEN), the device enters shutdown mode after a 40-µs (typical) delay
with all functions disabled.
UVLO
VCC
SS
VLOAD
SW
2.7 V
VEN
VVCC-UVLO
VUVLO
VREF
SS
1 V =VLOAD(TARGET)
VLOAD
Shutdown
TSS
UVLO should be greater than
VEN more than 1.5 µs to start-up
1.5 µs
> 3 cycles
SS is grounded
with 2 cycles
delay
90-µs (typical)
internal start-up delay
BIAS
= VSUPPLY
Figure 9-2. Boost Start-Up Waveforms Case 1: Start-Up by VCC UVLO, UVLO Toggle After Start-Up
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UVLO
VCC
SS
VLOAD
2.7 V
SS
1 V =VLOAD(TARGET)
VLOAD
Shutdown
TSS
UVLO should be greater than
0.55 V more than 1.5 µs to start-up
1.5 µs
> 40us(typical)
SS is grounded
with 2 cycles
delay
90-µs (typical)
internal start-up delay
BIAS
= VSUPPLY
90us (typical)
internal start-up delay
VEN
VVCC-UVLO
VUVLO
VREF
SW
Figure 9-3. Boost Start-Up Waveforms Case 2: Start-Up by VCC UVLO, EN Toggle After Start-Up
The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5 V
(typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be
calculated as shown in Equation 1 and Equation 2.
UVLO(FALLING)
SUPPLY(ON) SUPPLY(OFF)
UVLO(RISING)
UVLOT
UVLO
V
V V
V
RI
u 
(1)
where
• VSUPPLY(ON) is the desired start-up voltage of the converter
• VSUPPLY(OFF) is the desired turn-off voltage of the converter
UVLO(RISING) UVLOT
UVLOB
SUPPLY(ON) UVLO(RISING)
V R
RV V
u

(2)
A UVLO capacitor (CUVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during
start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an
additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the 5-
μA hysteresis current turns on.
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VSUPPLY
RUVLOT
RUVLOB
RUVLOS
CUVLO
IUVLO
EN/UVLO/SYNC
+
±
VUVLO
RUN
Figure 9-4. Line UVLO using Three UVLO Resistors
Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.
9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device has an internal wide input VCC regulator that is sourced from the BIAS pin. The wide input VCC
regulator allows the BIAS pin to be connected directly to supply voltages from 2.9 V to 45 V (transient protection
up to 50 V).
The VCC regulator turns on when the device is in standby or run mode. When the BIAS pin voltage is below the
VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin voltage
is greater than the VCC regulation target, the VCC regulator provides a 5-V supply (typical) for the device and
the internal N-channel MOSFET driver.
The VCC regulator sources current into the capacitor connected to the VCC pin. Connect a 5-Ω resistor in series
with a 1-µF ceramic bypass capacitor from this pin to PGND.
The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost
converter output or from an external power supply as shown in Figure 9-5. Also, this configuration allows the
device to handle more power when VSUPPLY is less than 5 V. Practical minimum supply voltage after start-up is
decided by the maximum duty cycle limit (DMAX).
VLOAD
VSUPP LY
Option al
BIAS SW
AGND
FB
COMP
SS
RT
UVLO
VCC
PGND MODE
PGOOD
VLOAD
Figure 9-5. Decrease the Minimum Operating Voltage After Start-Up
In flyback topology, the internal power dissipation of the device can be decreased by supplying the BIAS using
an additional transformer winding, especially in PSR flyback. In this configuration, the external BIAS supply
voltage (VAUX) must be greater than the regulation target of the external LDO, and the BIAS pin voltage must
always be greater than 2.9 V.
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VSUPP LY
BIAS SW
AGND
FB
COMP
SS
RT
UVLO
VCC
PGND MODE
PGOOD
<11V
VAUX =1 2V
VAUX
VLOAD =12V
Optional
Figure 9-6. External BIAS Supply (PSR Flyback)
9.3.3 Soft Start (SS Pin)
The soft-start feature helps the converter gradually reach the steady state operating point, thus reducing start-up
stresses and surges. The device regulates the FB pin to the SS pin voltage or the internal reference, whichever
is lower.
At start-up, the internal 10-μA soft-start current source (ISS) turns on after the VCC voltage exceeds the VCC UV
threshold. The soft-start current gradually increases the voltage on an external soft-start capacitor connected to
the SS pin. This results in a gradual rise of the output voltage. The SS pin is pulled down to ground by an
internal switch when the VCC is less than VCC UVLO threshold, the UVLO is less than the UVLO threshold,
during hiccup mode off time or thermal shutdown.
In boost topology, soft-start time (tSS) varies with the input supply voltage. The soft-start time in boost topology is
calculated as shown in Equation 3.
§ ·
u 
¨ ¸
© ¹
SS SUPPLY
SS
SS LOAD
C V
t 1
I V
(3)
In SEPIC topology, the soft-start time (tSS) is calculated as follows.
SS
SS
SS
C
t
I
(4)
TI recommends choosing the soft-start time long enough so that the converter can start up without going into an
overcurrent state. See Section 9.3.11 for more detailed information.
Figure 9-7 shows an implementation of primary side soft start in flyback topology.
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FB COMP
SS
Figure 9-7. Primary-Side Soft Start in Flyback
Figure 9-8 shows an implementation of secondary side soft-start in flyback topology.
VLOAD
Secondary Side
Soft-start
Figure 9-8. Secondary-Side Soft-Start in Flyback
9.3.4 Switching Frequency (RT Pin)
The switching frequency of the device can be set by a single RT resistor connected between the RT and the
AGND pins. The resistor value to set the RT switching frequency (fRT) is calculated as shown in Equation 5.
10
T
RT(TYPICAL)
2.21 10
R 955
f
u

(5)
The RT pin is regulated to 0.5 V by the internal RT regulator when the device is enabled.
9.3.5 Dual Random Spread Spectrum - DRSS (MODE Pin)
The device provides a digital spread spectrum which reduces the EMI of the power supply over a wide frequency
range. This function is enabled by a single resistor (37.4 kΩ or 100 kΩ) between the MODE pin and the AGND
pin or by programming the MODE pin voltage (370 mV or greater than 1.0 V) during initial power up. When the
spread spectrum is enabled, the internal modulator dithers the internal clock. When an external synchronization
clock is applied to the SYNC pin, the internal spread spectrum is disabled. DRSS (a) combines a low frequency
triangular modulation profile (b) with a high frequency cycle-by-cycle random modulation profile (c). The low
frequency triangular modulation improves performance in lower radio frequency bands (for example, AM band),
while the high frequency random modulation improves performance in higher radio frequency bands (for
example, FM band). In addition, the frequency of the triangular modulation is further modulated randomly to
reduce the likelihood of any audible tones. In order to minimize output voltage ripple caused by spread
spectrum, duty cycle is modified on a cycle-by-cycle basis to maintain a nearly constant duty cycle when
dithering is enabled (see Figure 9-9).
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Spread Spectrum
ON
0.156 x fSW
fSW (a) Low + High Frequency
Random Modulation
(b) Low Frequency
Random Modulation
(c) High Frequency
Random Modulation
Spread Spectrum
OFF
Frequency
Figure 9-9. Dual Random Spread Spectrum
9.3.6 Clock Synchronization (UVLO/SYNC/EN Pin)
The switching frequency of the device can be synchronized to an external clock by pulling down the EN/UVLO/
SYNC pin. The internal clock of the device is synchronized at the falling edge, but ignores the falling edge input
during the forced off time, which is determined by the maximum duty cycle limit. The external synchronization
clock must pull down the EN/UVLO/SYNC pin voltage below VUVLO(FALLING). The duty cycle of the pulldown
pulse is not limited, but the minimum pulldown pulse width must be greater than 150 ns. The minimum pullup
pulse width must be greater than 250 ns. Figure 9-10 shows an implementation of the remote shutdown function.
The UVLO pin can be pulled down by a discrete MOSFET or an open-drain output of an MCU. In this
configuration, the device stops switching immediately after the UVLO pin is grounded, and the device shuts
down 40 µs (typical) after the UVLO pin is grounded.
UVLO/SYNC
VSUPPLY
MCU
SHUTDOWN
Figure 9-10. UVLO and Shutdown
Figure 9-11 shows an implementation of shutdown and clock synchronization functions together. In this
configuration, the device immediately stops switching when the UVLO pin is grounded, and the device shuts
down if the fSYNC stays in high logic state for longer than 40 µs (typical). UVLO is in low logic state for more than
40 µs (typical). The device runs at fSYNC if clock pulses are provided after the device is enabled.
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