Texas Instruments TLC5510 User manual

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
1
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
features
D Analog Input Range
– TLC5510 ...2VFull Scale
– TLC5510A ...4VFull Scale
D 8-Bit Resolution
D Integral Linearity Error
±0.75 LSB Max (25°C)
±1 LSB Max (–20°C to 75°C)
D Differential Linearity Error
±0.5 LSB Max (25°C)
±0.75 LSB Max (–20°C to 75°C)
D Maximum Conversion Rate
20 Mega-Samples per Second
(MSPS) Max
D 5-V Single-Supply Operation
D Low Power Consumption
TLC5510 . . . 127.5 mW Typ
TLC5510A . . . 150 mW Typ
(includes reference resistor dissipation)
D TLC5510 is Interchangeable With Sony
CXD1175
applications
D Digital TV
D Medical Imaging
D Video Conferencing
D High-Speed Data Conversion
D QAM Demodulators
description
TheTLC5510andTLC5510AareCMOS,8-bit,20
MSPS analog-to-digital converters (ADCs) that
utilizeasemiflasharchitecture.TheTLC5510and
TLC5510A operate with a single 5-V supply and
typically consume only 130 mW of power.
Included is an internal sample-and-hold circuit,
parallel outputs with high-impedance mode, and
internal reference resistors.
The semiflash architecture reduces power
consumption and die size compared to flash
converters. By implementing the conversion in a
2-step process, the number of comparators is
significantly reduced. The latency of the data
output valid is 2.5 clocks.
The TLC5510 uses the three internal reference
resistors to create a standard, 2-V, full-scale
conversion range using VDDA. Only external jumpers are required to implement this option and eliminates the
need for external reference resistors. The TLC5510A uses only the center internal resistor section with an
externallyapplied4-Vreferencesuchthata4-Vinputsignalcanbeused.Differentiallinearityis0.5LSBat25°C
and a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications include
a differential gain of 1% and differential phase of 0.7 degrees.
The TLC5510 and TLC5510A are characterized for operation from –20°C to 75°C.
AVAILABLE OPTIONS
PACKAGE
MAXIMUM FULL SCALE
TATSSOP (PW) SOP (NS)
(TAPE AND REEL ONLY)
MAXIMUM
FULL
-
SCALE
INPUT VOLTAGE
20°Cto75°C
TLC5510IPW TLC5510INSLE 2 V
–
20°C
to
75°C
– TLC5510AINSLE 4 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1994 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
DGND
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
VDDD
CLK
DGND
REFB
REFBS
AGND
AGND
ANALOG IN
VDDA
REFT
REFTS
VDDA
VDDA
VDDD
PW OR NS PACKAGE†
(TOP VIEW)
†Availableintapeandreelonlyand ordered
astheshownintheAvailableOptionstable
below.

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
2POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
functional block diagram
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit) Lower Data
Latch
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit)
Upper Sampling
Comparators
(4-Bit)
Upper Encoder
(4-Bit)
Upper Data
Latch
Clock
Generator
OE
D1(LSB)
D2
D3
D4
D5
D6
D7
D8(MSB)
CLK
REFB
REFT
REFBS
AGND
AGND
ANALOG IN
VDDA
REFTS
270 Ω
NOM
80 Ω
NOM
320 Ω
NOM
Resistor
Reference
Divider
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
VDDA
AGND
ANALOG IN
EQUIVALENT OF EACH DIGITAL INPUT
VDDD
DGND
OE, CLK
EQUIVALENT OF EACH DIGITAL OUTPUT
VDDD
DGND
D1–D8

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
3
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 20, 21 Analog ground
ANALOG IN 19 I Analog input
CLK 12 I Clock input
DGND 2, 24 Digital ground
D1–D8 3–10 O Digital data out. D1 = LSB, D8 = MSB
OE 1 I Output enable. When OE = low, data is enabled. When OE = high, D1–D8 is in high-impedance state.
VDDA 14, 15, 18 Analog supply voltage
VDDD 11, 13 Digital supply voltage
REFB 23 I Reference voltage in bottom
REFBS 22 Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected to
ground.
REFT 17 I Reference voltage in top
REFTS 16 Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected to
VDDA.
absolute maximum ratings†
Supply voltage, VDDA, VDDD 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, VREFT, VREFB AGND to VDDA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range, VI(ANLG) AGND to VDDA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, VI(DGTL) DGND to VDDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, VO(DGTL) DGND to VDDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stressesbeyondthoselistedunder “absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings only,and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
VDDA–AGND 4.75 5 5.25
V
Supply voltage VDDD–AGND 4.75 5 5.25
V
AGND–DGND –100 0 100 mV
Reference input voltage (top), Vref(T)‡TLC5510A VREFB+2 4 V
Reference input voltage (bottom), Vref(B)‡TLC5510A 0 VREFT–4 V
Analog input voltage range, VI(ANLG) VREFB VREFT V
High-level input voltage, VIH 4 V
Low-level input voltage, VIL 1 V
Pulse duration, clock high, tw(H) (see Figure 1) 25 ns
Pulse duration, clock low, tw(L) (see Figure 1) 25 ns
‡The reference voltage levels for the TLC5510 are derived through an internal resistor divider between VDDA and ground and therefore are not
derived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, the
reference voltage is externally applied across the center divider resistor.

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
4POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electricalcharacteristicsatVDD=5V,VREFT=2.5V,VREFB=0.5V,f(CLK)=20MHz,TA=25°C(unless
otherwise noted)
digital I/O
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
IIH High-level input current VDD = MAX, VIH = VDD 5
µA
IIL Low-level input current VDD = MAX, VIL = 0 5µ
A
IOH High-level output current OE = GND, VDD = MIN, VOH = VDD–0.5 V –1.5
mA
IOL Low-level output current OE = GND, VDD = MIN, VOL = 0.4 V 2.5
mA
IOZH High-level high-impedance-state
output leakage current OE = VDD, VDD = MAX VOH = VDD 16
µA
IOZL Low-level high-impedance-state
output leakage current OE = VDD, VDD = MIN VOL = 0 16 µ
A
†Conditions marked MIN or MAX are as stated in recommended operating conditions.
power
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
IDD Supply current f(CLK) = 20 MHz, National Television System Committee (NTSC)
ramp wave input, reference resistor dissipation is separate 18 27 mA
If
Reference voltage current
TLC5510 Vref = REFT –REFB = 2 V 5.2 7.5 10.5 mA
I
ref
Reference
voltage
current
TLC5510A Vref = REFT –REFB = 4 V 10.4 15 21 mA
†Conditions marked MIN or MAX are as stated in recommended operating conditions.
static performance
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
Self-bias (1), at REFB
Short REFB to REFBS
Short REFT to REFTS
0.57 0.61 0.65
Self-bias (2), REFT –REFB
Short
REFB
to
REFBS
,
Short
REFT
to
REFTS
1.9 2.02 2.15 V
Self-bias (3), at REFT Short REFB to AGND, Short REFT to REFTS 2.18 2.29 2.4
Rref Reference voltage resistor Between REFT and REFB 190 270 350 Ω
CiAnalog input capacitance VI(ANLG) = 1.5 V + 0.07 Vrms 16 pF
TLC5510
f
(CLK)
= 20 MHz, TA= 25°C±0.4 ±0.75
Integral nonlinearity (INL)
TLC5510
(CLK) ,
VI= 0.5 V to 2.5 V TA= –20°C to 75°C±1
Integral
nonlinearity
(INL)
TLC5510A
f
(CLK)
= 20 MHz, TA= 25°C±0.4 ±0.75
TLC5510A
(CLK) ,
VI= 0 to 4 V TA= –20°C to 75°C±1
LSB
TLC5510
f
(CLK)
= 20 MHz, TA= 25°C±0.3 ±0.5
LSB
Differential nonlinearity (DNL)
TLC5510
(CLK) ,
VI= 0.5 V to 2.5 V TA= –20°C to 75°C±0.75
Differential
nonlinearity
(DNL)
TLC5510A
f
(CLK)
= 20 MHz, TA= 25°C±0.3 ±0.5
TLC5510A
(CLK) ,
VI= 0 to 4 V TA= –20°C to 75°C±0.75
EZS
Zero scale error
TLC5510 Vref = REFT –REFB = 2 V –18 –43 –68 mV
E
ZS
Zero
-
scale
error
TLC5510A Vref= REFT –REFB = 4 V –36 –86 –136 mV
EFS
Full-scale error
TLC5510 Vref = REFT –REFB = 2 V –20 0 20 mV
EFS
Full
-
scale
error
TLC5510A Vref = REFT –REFB = 4 V –40 0 40 mV
†Conditions marked MIN or MAX are as stated in recommended operating conditions.

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
5
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
operatingcharacteristicsatVDD=5V,VREFT=2.5V,VREFB=0.5V,f(CLK)=20MHz,TA=25°C(unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
Maximum conversion rate
TLC5510
fI= 1 kHz ram
pVI(ANLG) = 0.5 V –2.5 V 20 MSPS
f
conv
Maximum
conversion
rate
TLC5510A
f
I=
1
-
kHz
ramp
VI(ANLG) = 0 V –4 V 20 MSPS
BW Analog input bandwidth At –1 dB 14 MHz
td(D) Digital output delay time CL≤10 pF (see Note 1 and Figure 1) 18 30 ns
Differential gain NTSC 40 Institute of Radio En
g
ineers (IRE) 1%
Differential phase
g()
modulation wave, fconv = 14.3 MSPS 0.7 degrees
tAJ Aperture jitter time 30 ps
td(s) Sampling delay time 4 ns
ten Enable time, OE↓to valid data CL= 10 pF 5 ns
tdis Disable time, OE↑to high impedance CL= 10 pF 7 ns
In
p
ut tone = 1 MHz
TA= 25°C 45
Input
tone
=
1
MHz
Full range 43
In
p
ut tone = 3 MHz
TA= 25°C 45
S
p
urious free dynamic range (SFDR)
Input
tone
=
3
MHz
Full range 46
dB
Spurious
free
dynamic
range
(SFDR)
In
p
ut tone = 6 MHz
TA= 25°C 43
dB
Input
tone
=
6
MHz
Full range 42
In
p
ut tone = 10 MHz
TA= 25°C 39
Input
tone
=
10
MHz
Full range 39
SNR
Signal to noise ratio
TA= 25°C 46
dB
SNR
Signal
-
to
-
noise
ratio
Full range 44
dB
NOTE 1: CLincludes probe and jig capacitance.
NN+1 N+2
N+3 N+4
N–3N–2N–1NN+1
td(D)
CLK (clock)
ANALOG IN
(input signal)
D1–D8
(output data)
tw(H) tw(L)
td(s)
Figure 1. I/O Timing Diagram

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
6POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
functional description
The TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each.
AsshowninFigure2,inputvoltageVI(1)issampledwiththefallingedgeofCLK1totheuppercomparatorsblock
andthelower comparatorsblock(A),S(1). Theuppercomparators blockfinalizesthe upperdataUD(1) withthe
rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown
in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.
InputvoltageVI(2) issampledwith thefallingedge ofCLK2.UD(2) isfinalizedwiththerisingedgeofCLK3, and
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears with
the rising edge of CLK5.
VI(1) VI(2) VI(3) VI(4)
CLK1 CLK2 CLK3 CLK4
S(1) C(1) S(2) C(2) S(3) C(3) S(4) C(4)
S(1) H(1) C(1) S(3) H(3) C(3)
H(0) C(0) S(2) H(2) C(2) S(4) H(4)
LD(–2)
OUT(–2) OUT(–1) OUT(0) OUT(1)
ANALOG IN
(sampling points)
CLK (clock)
Upper Comparators Block
Upper Data
Lower Reference Voltage
Lower Comparators Block (A)
Lower Data (A)
Lower Comparators Block (B)
Lower Data (B)
D1–D8 (data output)
UD(0)
RV(0)
UD(1)
RV(1)
UD(2)
RV(2)
UD(3)
RV(3)
LD(–1)
LD(0)
LD(1)
LD(2)
CLK5
Figure 2. Internal Functional Timing Diagram

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
7
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
internal referencing
TLC5510
ThethreeinternalresistorsshownwithVDDAcangeneratea2-Vreferencevoltage.Theseresistorsarebrought
out on VDDA, REFTS, REFT, REFB, REFBS, and AGND.
To use the internally generated reference voltage, terminal connections should be made as shown in Figure 3.
This connection provides the standard video 2-V reference for the nominal digital output.
R1
320 Ω NOM
Rref
270 Ω NOM
R2
80 Ω NOM
VDDA
(analog supply)
REFTS
REFT
REFB
REFBS
AGND
TLC5510
16
17
22
21
23
18
Figure 3. External Connections for a 2-V Analog Input Span Using the Internal-Reference Resistor Divider
TLC5510A
Forananaloginputspanof4V,4VissuppliedtoREFT,andREFBisgroundedandterminalconnectionsshould
be made as shown in Figure 4. This connection provides the 4-V reference for the nominal zero to full-scale
digital output with a 4 Vpp analog input at ANALOG IN.
R1
320 Ω NOM
Rref
270 Ω NOM
R2
80 Ω NOM
REFTS
REFT
REFB
REFBS
AGND
TLC5510A
16
17
22
21
23
18
4 V
VDDA
(analog supply)
Figure 4. External Connections for 4-V Analog Input Span

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
8POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
functional operation
The output code change with input voltage is shown in Table 1.
Table 1. Functional Operation
INPUT SIGNAL
STEP
DIGITAL OUTPUT CODE
INPUT
SIGNAL
VOLTAGE
STEP
MSB LSB
Vref(B) 255 0 0 0 0 0 0 0 0
•• • •••••••
• • • •••••••
•128 0 1111111
•127 1 0000000
• • • •••••••
• • • •••••••
Vref(T) 0 1 1 1 1 1 1 1 1
APPLICATION INFORMATION
The following notes are design recommendations that should be used with the device.
D External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D RFbreadboardingorprinted-circuit-board(PCB)techniquesshouldbeusedthroughouttheevaluationand
production process. Breadboards should be copper clad for bench evaluation.
D SinceAGNDandDGNDareconnectedinternally,thegroundleadinmustbekeptasnoisefreeaspossible.
A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and
digital ground plane should be used on PCB layouts when additional logic devices are used. The AGND
and DGND terminals of the device should be tied to the analog ground plane.
D VDDA to AGND and VDDD to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively,
andplacedascloseaspossibletotheaffecteddeviceterminals.Aceramic-chipcapacitorisrecommended
for the 0.01-µF capacitor. Care should be exercised to ensure a solid noise-free ground connection for the
analog and digital ground terminals.
D VDDA, AGND, and ANALOG IN should be shielded from the higher frequency terminals, CLK and D0–D7.
When possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB for
shielding.
D In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Ωor less within the analog frequency range of interest.

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
9
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
APPLICATION INFORMATION
C1
D1
C3
C4
C5
C6
C2
C11
C9
C7
C8
C10
C12
R5
R4 R2
R1
Q1
D3
D2
TP3
R3
C11
FB2
FB3
FB7
FB1
VREF
ADJ
TP1
J1
VDDD
VDDA
VDDA
REFTS
REFT
VDDA
ANALOG IN
AGND
AGND
REFBS
REFB
DGND
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
CLK
VDDD
D8 (MSB)
D7
D6
D5
D4
D3
D2
D1 (LSB)
DGND
OE
TLC5510
AVDD
5 V Clock
Output
Enable
DVDD
5 V
Video
Input
JP2JP1
JP4JP3
–5 V
NOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes D2 and D3
which compensate for D1 and Q1 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference.
LOCATION DESCRIPTION
C1, C3–C4, C6–C12 0.1-µF capacitor
C2 10-pF capacitor
C5 47-µF capacitor
FB1, FB2, FB3, FB7 Ferrite bead
Q1 2N3414 or equivalent
R1, R3 75-Ω resistor
R2 500-Ω resistor
R4 10-kΩ resistor, clamp voltage adjust
R5 300-Ω resistor, reference-voltage fine adjust
Figure 5. TLC5510 Evaluation and Test Schematic

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L –SEPTEMBER 1994 –REVISED JUNE 2003
10 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
APPLICATION INFORMATION
C1
D1
C3
C5
C6
C2
C11 C9
C7
C8
C4
R5
R4 R2
R1
Q1
R3
C11
FB2
FB3
FB7
FB1
VREF
ADJ
TP1
J1
VDDD
VDDA
VDDA
REFTS
REFT
VDDA
ANALOG IN
AGND
AGND
REFBS
REFB
DGND
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
CLK
VDDD
D8 (MSB)
D7
D6
D5
D4
D3
D2
D1 (LSB)
DGND
OE
TLC5510A
AVDD
5 V Clock
Output
Enable
DVDD
5 V
Video
Input
–5 V
NOTE A: R5 allows adjustment of the reference voltage to 4 V. R4 adjusts for the desired Q1 quiescent operating point.
LOCATION DESCRIPTION
C1, C3–C4, C6–C11 0.1-µF capacitor
C2 10-pF capacitor
C5 47-µF capacitor
FB1, FB2, FB3, FB7 Ferrite bead
Q1 2N3414 or equivalent
R1, R3 75-Ω resistor
R2 500-Ω resistor
R4 10-kΩ resistor, clamp voltage adjust
R5 300-Ω resistor, reference-voltage fine adjust
Figure 6. TLC5510A Evaluation and Test Schematic