Texas Instruments THS1031 User manual

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
1
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
D 10-Bit Resolution, 30 MSPS
Analog-to-Digital Converter
D Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital
Clamp
– Differential
D Built-In Programmable Gain Amplifier
(PGA)
D Differential Nonlinearity: ±0.3 LSB
D Signal-to-Noise: 56 dB
D Spurious Free Dynamic Range: 60 dB
D Adjustable Internal Voltage Reference
D Straight Binary/2s Complement Output
D Out-of-Range Indicator
D Power-Down Mode
description
The THS1031 is a CMOS, low-power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 3 V to 5.5 V. The THS1031 has been designed to give circuit developers flexibility. The
analoginputtotheTHS1031canbeeithersingle-endedordifferential.Thisdevicehasabuilt-inclampamplifier
whoseclampinputlevelcanbedrivenfromanexternaldcsourceorfromaninternalhigh-precision10-bitdigital
clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR for small
signals.TheTHS1031providesawideselectionofvoltagereferencestomatchtheuser’sdesignrequirements.
For more design flexibility, the internal reference can be bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the application. The out-of-range output indicates any
out-of-range condition in THS1031’s input signal. The format of digital output can be coded in either unsigned
binary or 2s complement.
The speed, resolution, and single-supply operation of the THS1031 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allowsdc restorationofvideo signaland issuitable forvideo applications.Thespeed andresolution ideallysuit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders.AwideinputvoltagerangebetweenREFBSandREFTSallowstheTHS1031tobeappliedinboth
imaging and communications systems.
The THS1031C is characterized for operation from 0°C to 70°C, while the THS1031I is characterized for
operation from –40°C to 85°C.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
T
A28-TSSOP (PW) 28-SOIC (DW)
0°C to 70°C THS1031CPW THS1031CDW
–40°C to 85°C THS1031IPW THS1031IDW
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
DVDD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
OVR
DGND
AVDD
AIN
VREF
REFBS
REFBF
MODE
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
2POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
functional block diagram
DAC
10-Bit
Clamp 10 Control
Register
ADC
Core
Output
Buffer
10
PGA
3
Sample
and
Hold DAC
Internal
Reference
Buffer
A
B
Clamp
Amplifier
VBG GND
Timing
Circuit
Power Down
WR
I/O(0–9)
OVR
OE
CLKVREFREFSENSE
CLAMPIN
CLAMP
AIN
REFTS
REFBS
MODE
REFTF
REFBF
ORG

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
3
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 1 I Analog ground
AIN 27 I Analog input
AVDD 28 I Analog supply
CLAMP 19 I High to enable clamp mode, low to disable clamp mode
CLAMPIN 20 I Connect to an external analog clamp reference input.
CLK 15 I Clock input
DGND 14 I Digital ground
DVDD 2 I Digital driver supply
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
3
4
5
6
7
8
9
10
11
12
I/O
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
MODE 23 I Mode input
OE 16 I High to 3-state the data bus, low to enable the data bus
OVR 13 O Out-of-range indicator
REFBS 25 I Reference bottom sense
REFBF 24 I Reference bottom decoupling
REFSENSE 18 I Reference sense
REFTF 22 I Reference top decoupling
REFTS 21 I Reference top sense
VREF 26 I/O Internal and external reference
WR 17 I Write strobe

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
4POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range: AVDD to AGND, DVDD to DGND –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to DGND –0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AVDD to DVDD –6.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode input voltage range, MODE to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage input range, REFTF, REFTB, REFTS, REFBS to AGND –0.3 V to AVDD + 0.3 V. . . . . . .
Analog input voltage range, AIN to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VREF to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference output voltage range, VREF to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input voltage range, CLK to AGND –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, digital input to DGND –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital output voltage range, digital output to DGND –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stressesbeyondthoselistedunder“absolutemaximumratings”maycause permanentdamagetothedevice.Theseare stressratingsonly,and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MIN NOM MAX UNIT
High level in
p
ut voltage VIH
Clock input 0.8 ×AVDD
V
High
-
level
input
voltage
,
V
IH All other inputs 0.8 ×DVDD
V
Low-level in
p
ut voltage VIL
Clock input 0.2 ×AVDD
V
Low
-
level
in ut
voltage
,
VIL
All other inputs 0.2 ×DVDD
V
analog inputs
MIN NOM MAX UNIT
Analog input voltage, VI(AIN) (PGA = 1x, top, bottom, or external reference mode) REFBS REFTS V
Reference input voltage, VI(VREF) 1 2 V
Clamp input voltage, VI(CLAMPIN) 0.1 AVDD–0.1 V
power supply
MIN NOM MAX UNIT
Su
pp
ly voltage
Maximum sam
p
ling rate = 30 MSPS
AVDD 3 3.3 5.5
V
Supply
voltage
Maximum
sampling
rate
=
30
MSPS
DVDD 3 3.3 5.5
V
REFTS, REFBS reference voltages (MODE = AVDD)
PARAMETER MIN NOM MAX UNIT
REFTS Reference input voltage (top) 1AVDD V
REFBS Reference input voltage (bottom) 0AVDD–1 V
Differential input voltage (REFTS –REFBS) 1 2 V
Switched input capacitance on REFTS or REFBS 0.6 pF
sampling rate and resolution
PARAMETER MIN NOM MAX UNIT
fsSample frequency 5 30 MHz
Resolution 10 Bits

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
5
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
fs= 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference,
PGA = 1X, TA= Tmin to Tmax (unless otherwise noted)
analog inputs
PARAMETER MIN TYP MAX UNIT
VI(AIN) Analog input voltage REFBS REFTS V
CISwitched sampling input capacitance 1.2 pF
BW Full power bandwidth (–3 dB) 150 MHz
Ilkg DC leakage current (input = ±FS) 100 µA
VREF reference voltages
PARAMETER MIN TYP MAX UNIT
Internal 1-V reference voltage (REFSENSE = VREF) 0.95 1 1.05 V
Internal 2-V reference voltage (REFSENSE = AVSS) 1.90 2 2.10 V
External reference voltage (REFSENSE = AVDD) 1 2 V
Reference input resistance (REFSENSE = AVDD, MODE = AVDD/2) 18 kΩ
REFTF, REFBF reference voltages
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Differential input voltage (REFTF –REFBF) 1 2 V
In
p
ut common mode voltage (REFTF + REFBF)/2
AVDD = 3 V 1.3 1.5 1.7
V
Input
common
mode
voltage
(REFTF
+
REFBF)/2
AVDD = 5 V 2 2.5 3
V
VREF=1V
AVDD = 3 V 2
V
REFTF voltage (MODE = AVDD)
VREF
=
1
V
AVDD = 5 V 3
V
REFTF
voltage
(MODE
=
AV
DD
)
VREF=2V
AVDD = 3 V 2.5
V
VREF
=
2
V
AVDD = 5 V 3.5
V
VREF=1V
AVDD = 3 V 1
V
REFBF voltage (MODE = AVDD)
VREF
=
1
V
AVDD = 5 V 2
V
REFBF
voltage
(MODE
=
AV
DD
)
VREF=2V
AVDD = 3 V 0.5
V
VREF
=
2
V
AVDD = 5 V 1.5
V
Input resistance between REFTF and REFBF 680 Ω

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
6POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
fs= 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference,
PGA = 1X, TA= Tmin to Tmax (unless otherwise noted) (continued)
dc accuracy
PARAMETER MIN TYP MAX UNIT
INL Integral nonlinearity (see Note 1) ±1±2 LSB
DNL Differential nonlinearity (see Note 2) ±0.3 ±1 LSB
Offset error (see Note 3) 0.4 2 %FSR
Gain error (see Note 4) 1.4 3.5 %FSR
Missing code No missing code assured
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs1/2 LSB beforethe first codetransition.The full-scale pointis defined asa level 1/2LSB beyond thelast code transition.The
deviation is measured from the center of each particular code to the true straight line between these two endpoints.
2. AnidealADCexhibitscodetransitionsthatareexactly1LSBapart.DNListhedeviationfromthisidealvalue.Thereforethismeasure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level –first transition level) ÷ (2 n–2)). Using this definition for DNL separates the effects of gain andoffset
error. A minimum DNL better than –1 LSB ensures no missing codes.
3. Offset error is defined as the difference in analog input voltage –between the ideal voltage and the actual voltage –that will switch
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
4. Gain error is defined as the difference in analog input voltage –between the ideal voltage and the actual voltage –that will switch
the ADC output from code 1022 to code1023. The ideal voltage level is determined bysubtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (1024).
dynamic performance (ADC and PGA)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 3.5 MHz 8.2 9
ENOB
Effective number of bits
f = 3.5 MHz, AVDD = 5 V 8.8
Bits
ENOB
Effective
number
of
bits
f = 15 MHz 7.7
Bits
f = 15 MHz, AVDD = 5 V 7.64
f = 3.5 MHz 55 60
SFDR
S
p
urious free dynamic range
f = 3.5 MHz, AVDD = 5 V 63
dB
SFDR
Spurious
free
dynamic
range
f = 15 MHz 48
dB
f = 15 MHz, AVDD = 5 V 52.4
f = 3.5 MHz –58.2 –54.7
THD
Total harmonic distortion
f = 3.5 MHz, AVDD = 5 V –68.7
dB
THD
Total
harmonic
distortion
f = 15 MHz –47
dB
f = 15 MHz, AVDD = 5 V –51.9
f = 3.5 MHz 51.2 56
SNR
Signal to noise ratio
f = 3.5 MHz, AVDD = 5 V 55
dB
SNR
Signal
-
to
-
noise
ratio
f = 15 MHz 53
dB
f = 15 MHz, AVDD = 5 V 49.3
f = 3.5 MHz 51.1 56
SINAD
Signal to noise and distortion
f = 3.5 MHz, AVDD = 5 V 55
dB
SINAD
Signal
-
to
-
noise
and
distortion
f = 15 MHz 48.1
dB
f = 15 MHz, AVDD = 5 V 47.7

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
7
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, AVDD = 3 V, DVDD = 3 V,
fs= 30 MSPS/50% duty cycle, MODE = AVDD, 2-V input span from 0.5 V to 2.5 V, external reference,
PGA = 1X, TA= Tmin to Tmax (unless otherwise noted) (continued)
PGA
PARAMETER MIN TYP MAX UNIT
Gain range (linear scale) 0.5 4 V/V
Gain step size (linear scale) 0.5 V/V
Gain error from nominal 3%
Number of control bits 3 Bits
clamp amplifier and clamp DAC
PARAMETER MIN TYP MAX UNIT
Resolution 10 Bits
DAC output range REFBF REFTF V
DAC differential nonlinearity –1 1 LSB
DAC integral nonlinearity ±1 LSB
Clamping analog output voltage range 0.1 AVDD–0.1 V
Clamping analog output voltage error –40 40 mV
clock
PARAMETER MIN TYP MAX UNIT
tcClock cycle 33 ns
tw(CKH) Pulse duration, clock high 15 16.5 ns
tw(CKL) Pulse duration, clock high 15 16.5 ns
td(o) Clock to data valid, delay time 25 ns
Pipeline latency 3 Cycles
td(AP) Aperture delay time 4 ns
Aperture uncertainty (jitter) 2 ps
timing
PARAMETER MIN TYP MAX UNIT
td(DZ) Output disable to Hi-Z output, delay time 0 20 ns
td(DEN) Output enable to output valid, delay time 0 20 ns
td(OEW) Output disable to write enable, delay time 12 ns
td(WOE) Write disable to output enable, delay time 12 ns
tw(WP) Write pulse duration 15 ns
tsu Input data setup time 5 ns
thInput data hold time 5 ns
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Operating supply current AVDD = 3 V, MODE = AGND 30.6 45 mA
PD
Power dissi
p
ation
AVDD = DVDD = 3 V 94 135
mW
P
D
Power
dissipation
AVDD = DVDD = 5 V 160
mW
PD(STBY) Standby power AVDD = DVDD = 3 V, MODE = AGND 3 5 mW

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
8POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
See Note A
WE
OE
I/O Input OutputOutput Hi-Z Hi-Z
tw(WP)
td(OEW) td(WOE)
td(DEN) tsu
th td(DZ)
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Write Timing Diagram
See
Note A
NOTE A: All timing measurements are based on 50% of edge transition.
Analog Input
Input Clock
Digital Output
Sample 1
Sample 2 Sample 3
Sample 4 Sample 5
tc
t(CKH) tw(CKL)
td(o)
Pipeline Latency
Sample 1 Sample 2
Figure 2. Digital Output Timing Diagram

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
9
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
82
84
86
88
90
92
94
96
5 1015202530
POWER DISSIPATION
vs
SAMPLING FREQUENCY
fs–Sampling Frequency –MHz
AVDD = DVDD = 3 V
fi= 3.5 MHz
TA= 25°C
Power Dissipation –mW
Figure 3
7
7.5
8.0
8.5
9.0
9.5
10.0
–40 –15 10 35 60 85
EFFECTIVE NUMBER OF BITS
vs
TEMPERATURE
TA–Temperature –°C
AVDD = DVDD = 3 V
fi= 3.5 MHz
fs= 30 MSPS
Effective Number of Bits
Figure 4

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
10 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
7
7.5
8.0
8.5
9.0
9.5
10.0
5 1015202530
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY
Effective Number of Bits
fs–Sampling Frequency –MSPS
AVDD = DVDD = 3 V
fi= 3.5 MHz
TA= 25°C
Figure 5
7
7.5
8.0
8.5
9.0
9.5
10.0
5 1015202530
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY
Effective Number of Bits
fs–Sampling Frequency –MSPS
AVDD = 5 V,
DVDD = 3 V
fi= 3.5 MHz
TA= 25°C
Figure 6

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
11
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
7.00
7.50
8.00
8.50
9.00
9.50
10.00
5 1015202530
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY
Effective Number of Bits
fs–Sampling Frequency –MSPS
AVDD = DVDD= 5 V,
fi= 3.5 MHz
TA= 25°C
Figure 7
–1
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
1.0
0 128 256 384 512 640 768 896 1024
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
Input Code
DNL –Differential Nonlinearity –LSB
AVDD = 3 V, DVDD = 3 V
fs= 30 MSPS
Figure 8

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
12 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
0 128 256 384 512 640 768 896 1024
INTEGRAL NONLINEARITY
vs
INPUT CODE
Input Code
INL –Integral Nonlinearity –LSB
AVDD = 3 V
DVDD = 3 V
fs= 30 MSPS
Figure 9
–140
–120
–100
–80
–60
–40
–20
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
FFT
vs
FREQUENCY
f –Frequency –MHz
AVDD = 3 V
DVDD = 3 V
fi= 3.5 MHz,
–1 dBFS
FFT –dB
0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15
Figure 10

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
13
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Theanalog input AIN is sampled in the sample-and-hold unit,the output of which goes to a programmable gain
amplifier (PGA). The PGA feeds the ADC core, where the process of analog to digital conversion is performed
against ADC reference voltages, REFTF and REFBF.
Connecting the MODE pin to one of three voltages, AGND, AVDD or AVDD/2 sets up operating configurations.
The three settings open or close internal switches to select one of the three basic methods of ADC reference
generation.
Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the
internal reference buffer (IRB) or may be fed from completely external sources. Where the reference buffer is
employed,the user can choosetodrive it from theonboardreference generator (ORG),ormay useanexternal
voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and
REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user.
The THS1031 offers a clamp function for dc restoration of ac-coupled signals. The clamp voltage may be set
digitally via the 10-bit clamp DAC or by the analog level applied to the CLAMPIN input.
The ADC core drives out through output buffers to the I/O pins I/O0 to I/O9. The output buffers can be disabled
by the OE pin. Control input data on I/O0 to I/O9 can then be written, by pulses on WR, to the control registers.
These registers control clamp operation, output format (unsigned binary or twos complement), the PGA gain
setting and the device power down function.
A single-ended, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is
sampled on the rising edge of CLK, and corresponding data is output after the following third rising edge.
Theuser-chosenoperating configurationand referencevoltagesdeterminewhatinputsignalvoltage rangethe
THS1031 can handle.
The following sections explain:
D Theinternalsignalflowofthedevice,andhowtheinputsignalspanisrelatedtotheADCreferencevoltages;
D The ways in which the ADC reference voltages can be buffered internally, or externally applied;
D How to set the onboard reference generator output, if required, and several examples of complete
configurations.
D Subsequent sections explain the clamp function and digital controls, followed by more detailed application
information.
signal processing chain (sample and hold, PGA, ADC)
Figure 11 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
Sample
and
Hold
1
–1/2
–1/2
ADC
Core
VP+
VP–
PGA
VQ+
VQ–
REFTF
REFBF
AIN
REFTS
REFBS
Figure 11. Analog Input Signal Flow

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
14 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
sample-and-hold
The analog input signal AIN is applied to the AIN pin, either dc-coupled, ac-coupled, or ac-coupled with dc
restoration using the THS1031 clamp circuit.
The differential sample and hold processes AIN with respect to the voltages applied to the REFTS and REFBS
pins, to give a differential output VP+ –VP–= VP given by:
VP = AIN –VM
Where:
VM +
(REFTS ) REFBS)
2
For single-ended input signals, VM is a constant voltage; usually the AIN mid-scale input voltage. However if
MODE= AVDD/2then REFTS and REFBScanbe connected together tooperate with AIN asacomplementary
pair of differential inputs (see Figures 15 and 16).
programmable gain amplifier
VP is amplified by the PGA and fed into the ADC as a differential voltage VQ+–VQ–= VQ
VQ = Gain ×VP = Gain ×[AIN –VM]
The default PGA gain at power up is 1, but can be programmed from 0.5 to 4.0 via the control register.
analog-to-digital converter
In all operating configurations, VQ is digitized against ADC reference voltages REFTF and REFBF, full-scale
values of VQ being given by
VQFS )+ )
(REFTF * REFBF)
2
VQFS *+ *
(REFTF * REFBF)
2
VQ voltages outside the range VQFS–to VQFS+ lie outside the conversion range of the ADC. Attempts to
convertout-of-rangeinputsaresignalledtotheapplicationbydrivingtheOVRoutputpinhigh.VQvoltagesless
than VQFS–give ADC output code 0. VQ voltages greater than VQFS+ give output code 1023.
complete system
Combining equations 1 to 3, the analog full-scale input voltages at AIN which give VQFS+ and VQFS–at the
PGA output are:
AIN + FS )+ VM )
(REFTF * REFBF)
(2 Gain)
and
AIN + FS *+ VM *
(REFTF * REFBF)
(2 Gain)
The analog input span (voltage range) that lies within the ADC conversion range is:
Input span + [(FS ) ) * (FS * )] + (REFTF * REFBF) ń Gain
(1)
(2)
(3)
(4)
(5)
(6)

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
15
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
complete system (continued)
TheREFTFandREFBFvoltagedifferenceandthegainsetsthedeviceinputrange.Thenextsectionsdescribe
in detail the various methods available for setting voltages REFTF and REFBF to obtain the desired input span
and device performance.
ADC reference generation
The THS1031 has three primary modes of ADC reference generation, selected by the voltage level applied to
the MODE pin.
ConnectingtheMODEpinto AGNDgivesfullexternalreferencemode.Inthismode,the usersuppliestheADC
reference voltages directly to pins REFTF and REFBF. This mode is used where there is need for minimum
power drain or where there are very tight tolerances on the ADC reference voltages. This mode also offers the
possibility of Kelvin connection of the reference inputs to the THS1031 to eliminate any voltage drops from
remote references that may occur in the system. Only single-ended input is possible in this mode.
Connectingthe MODEpin to AVDD/2gives differentialmode. Inthismode, the ADCreference voltages REFTF
andREFBF are generated bytheinternal reference bufferfrom thevoltageapplied to the VREFpin.This mode
is suitable for handling differentially presented inputs, which are applied to the AIN and REFTS/REFBS pins.
Aspecialcase of differentialmode is center span mode,inwhich user applies a single-ended signal to AIN and
applies the mid-scale input voltage (VM) to the REFTS and REFBS pins.
Connecting the MODE pin to AVDD gives top/bottom mode. In this mode, the ADC reference voltages REFTF
andREFBFaregeneratedbytheinternalreferencebufferfrom the voltages applied to the REFTS and REFBS
pins. Only single-ended input is possible in top/bottom mode.
Table 1. Typical Set of Reference Connections
REFERENCE MODE MODE REFSENSE VREF
VOLTAGE REFTS, REFBS ANALOG INPUT FIGURES
External AVSS AVDD Disabled
Reference buffer powered
down, reference voltage pro-
vided directly by REFTS and
REFBS
Single-ended 12, 13, 14
VREF 1 V
E t ll t REFTS
Internal
AVDD/2
AGND 2 V Externally connect REFTS
to REFBS This
p
air then
Differential or
15 16 17
Internal
AVDD/2
External
divider 1 + Ra/Rb (see Figure 22)
to
REFBS
.
This
air
then
forms AIN–to the ADC. center span
15
,
16
,
17
External (through internal
reference buffer) AVDD Disabled REFTS = VMID + (VFS+ –Single-ended
Out
p
ut of VREF can be
AVDD
VREF 1 V VFS–) ×Gain/2
18 19
Out ut
of
VREF
can
be
externally tied to REFTS or
AV
DD AGND 2 V REFBS = V
MID
–
(
V
FS+
–
(
top-bottom
18
,
19
REFBS to provide one of the
reference voltages External
divider 1 + Ra/Rb (see Figure 22)
REFBS
VMID
(VFS+
VFS–) ×Gain/2
(to bottom
mode)

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
16 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
full external reference mode (mode = AGND)
Sample
and
Hold
1
–1/2
–1/2
ADC
Core
PGA
REFTF
REFBF
AIN+
REFTS
REFBS
Internal
Reference
Buffer
Figure 12. ADC Reference Generation, MODE = AGND
When MODE is connected to AGND, the internal reference buffer is powered down, its inputs and outputs
disconnected, and REFTS and REFBS internally connected to REFTF and REFBF respectively. These nodes
areconnected by the userto external sources toprovidethe ADC reference voltages.Theinternal connections
are designed for use in kelvin connection mode (Figure 14). When using external reference mode as shown
in Figure 13, REFTS must be shorted to REFTF and REFBS must be shorted to REFBF externally. The mean
of REFTF and REFBF must be equal to AVDD/2 (see Figure 13).
AIN
REFTS
REFBS
REFTF
REFBF
REFSENSE
MODE
AVDD
+FS
–FS
+ [(FS+) –(FS–)] ×
0.1 µF10 µF
0.1 µF
0.1 µF
AVDD
2
AVDD
2
DC SOURCE = GAIN
2
–[(FS+) –(FS–)] ×
AVDD
2
DC SOURCE = GAIN
2
Figure 13. Full External Reference Mode
Itis alsopossible to useREFTS andREFBSas senselinesto drivethe REFTF andREFBF lines(Kelvinmode)
to overcome any voltage drops within the system (see Figure 14).

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
17
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
full external reference mode (mode = AGND) (continued)
AIN
REFTS
REFBS
REFTF
REFBF
REFSENSE
MODE
AVDD
+FS
–FS
0.1 µF10 µF
_
+
_
+
0.1 µF
0.1 µF
AVDD
2
+ [(FS+) –(FS–)] ×
AVDD
2
REFT = GAIN
2
–[(FS+) –(FS–)] ×
AVDD
2
REFB = GAIN
2
Figure 14. Full External Reference With Kelvin Connections
differential mode (mode = AVDD/2)
Sample
and
Hold
1
–1/2
–1/2
ADC
Core
PGA
REFTF =
REFBF =
AIN+
REFTS
REFBS
Internal
Reference
Buffer
VREF
AGND
AVDD + VREF
2
AVDD –VREF
2
AIN–
Figure 15. ADC Reference Generation, MODE = AVDD/2
When MODE = AVDD/2, the internal reference buffer is enabled, its outputs internally switched to REFTF and
REFBF and inputs internally switched to VREF and AGND as shown in Figure 15. The REFTF and REFBF
voltages are centered on AVDD/2 by the internal reference buffer and the voltage difference between REFTF
and REFBF equals the voltage at VREF. The internal REFTS to REFBS and REFTF to REFBF switches are
open in this mode, allowing REFTS and REFBS to form the AIN–to the sample and hold.
Depending on the connection of the REFSENSE pin, the voltage on VREF may be externally driven, or set to
an internally generated voltage of 1 V, 2 V, or an intermediate voltage (see the onboard reference generator
configuration).

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
18 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
differential mode (mode = AVDD/2) (continued)
AIN
REFTS
REFBS
REFTF
REFBF
REFSENSE
MODE
+FS
–FS
0.1 µF10 µF
0.1 µF
0.1 µF
VREF
+FS
–FS
AIN+
AIN–
AVDD
2
Figure 16. Differential Input Mode, 1-V Reference Span
AIN
REFTS
REFBS
REFTF
REFBF REFSENSE
MODE
+FS
–FS
0.1 µF10 µF
0.1 µF
0.1 µF
VM
_
+
VM
DC SOURCE = VM
AVDD
2
Figure 17. Center Span Mode, 2-V Reference Span

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
19
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
top/bottom mode (MODE = AVDD)
Sample
and
Hold
1
–1/2
–1/2
ADC
Core
PGA
REFTF = AVDD + (REFTS –REFBS)
AIN+
REFTS
REFBS
Internal
Reference
Buffer
REFBF = AVDD –(REFTS –REFBS)
2
2
Figure 18. ADC Reference Generation Mode = AVDD
ConnectingMODEtoAVDDenablestheinternalreferencebuffer.ItsinputsareinternallyswitchedtotheREFTS
and REFBS pins and its outputs internally switched to pins REFTF and REFBF. The internal connections
(REFTS to REFTF) and (REFBS to REFBF) are broken.
To matchthe signal span tothe full ADC inputspan, the voltage differencebetweenREFTSandREFBSshould
be REFTS –REFBS = [(FS+) –(FS–)] ×Gain, with the average of the REFTS and REFBS voltages being the
AIN midscale voltage, VM.
Typically, REFSENSE is tied to AVDD to disable the ORG output to VREF (as in Figure 19), but the user can
choose to use the ORG output to VREF as either REFTS or REFBS.
AIN
REFTS
REFBS
REFTF
REFBF
REFSENSE
MODE
AVDD
+FS
–FS
DC SOURCE = VM + [(FS+) –(FS–)] ×
DC SOURCE =VM –[(FS+) –(FS–)] ×
0.1 µF10 µF
0.1 µF
0.1 µF
GAIN
2
GAIN
2
Figure 19. ADC Reference Generation Mode = AVDD

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E –NOVEMBER 1999 –REVISED MARCH 2002
20 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
onboard reference generator configuration
The onboard reference generator (ORG) can supply a supply-voltage-independent and temperature-
independent voltage on pin VREF.
External connections to REFSENSE control the ORG’s output to the VREF pin as shown in Table 2.
Table 2. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION ORG OUTPUT TO VREF REFER TO:
VREF pin 1 V Figure 20
AGND 2 V Figure 21
External divider junction (1 + RA/RB)Figure 22
AVDD Open circuit Figure 23
REFSENSE = AVDD powers the ORG down, saving power when the ORG function is not required.
If MODE = AVDD/2, the voltage on VREF determines the ADC reference voltages:
REFTF +
AVDD
2
)
VREF
2
REFBF +
AVDD
2
*
VREF
2
REFTF * REFBF + VREF
_
+
_
+
VBG
Internal
Reference
Buffer
Mode =
REFSENSE
0.1 µF 1 µF
Tantalum
AGND
VREF = 1 V
AVDD
2
Figure 20. 1-V VREF Using ORG
(7)