Texas Instruments MSP430FG47x User manual

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DLow Supply-Voltage Range: 1.8 V to 3.6 V
DUltra-Low Power Consumption:
Active Mode: 262 Aat1MHz,2.2V
Standby Mode: 1.1 A
Off Mode (RAM Retention): 0.1 A
DFive Power-Saving Modes
DWake-Up From Standby Mode in
Less Than 6 s
D16-Bit RISC Architecture,
125-ns Instruction Cycle Time
D16-Bit Sigma-Delta Analog-to-Digital (A/D)
Converter With Internal Reference and Five
Differential Analog Inputs
DDual 12-Bit Digital-to-Analog (D/A)
Converter
DDual Configurable Operational Amplifiers
D16-Bit Timer_A With Three
Capture/Compare Registers
D16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
DTwo Universal Serial Communication
Interfaces (USCI)
USCI_A0
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
USCI_B0
-- I 2C
-- Synchronous SPI
DIntegrated LCD Driver With Contrast
Control for Up to 128 Segments
DBrownout Detector
DBasic Timer With Real-Time Clock Feature
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DOn-Chip Comparator
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DBootstrap Loader
DOn-Chip Emulation Module
DMSP430FG47x Family Members Include
MSP430FG477: 32KB+256B Flash Memory
2KB RAM
MSP430FG478: 48KB+256B Flash Memory
2KB RAM
MSP430FG479: 60KB+256B Flash Memory
2KB RAM
DAvailable in 113-Ball BGA (ZQW) and
80-Pin QFP (PN) Packages (see Available
Options)
DFor Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 s.
The MSP430FG47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time clock,
a high performance 16-bit sigma-delta A/D converter, dual 12-bit D/A converters, two configurable operational
amplifiers, two universal serial communication interface, 48 I/O pins, and a liquid crystal display driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
AVAILABLE OPTIONS†
T
PACKAGED DEVICES‡
TAPLASTIC 113-BALL BGA (ZQW) PLASTIC 80-PIN QFP (PN)
-- 4 0 Cto85C
MSP430FG477IZQW
MSP430FG478IZQW
MSP430FG479IZQW
MSP430FG477IPN
MSP430FG478IPN
MSP430FG479IPN
†For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
-- MSP--FET430UIF (USB)
-- MSP--FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
-- MSP--FET430U80 (PN package)
DProduction Programmer
-- MSP--GANG430

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430FG47xIZQW
Note: For terminal assignments, see the MSP430xG47x Terminal Functions table.
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
L1
M1
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
L2
M2
A3 A4 A5 A6 A7 A8 A9 A10
E5 E6 E7 E8
A11
B11
C11
D11
E11
F11
G11
H11
J11
K11
L11
M11
A12
B12
C12
D12
E12
F12
G12
H12
J12
K12
L12
M12M3 M4 M5 M6 M7 M8 M9 M10
L3 L4 L5 L6 L7 L8 L9 L10
B3 B4 B5 B6 B7 B8 B9 B10
H5 H6 H7 H8
D4 D5 D6 D7 D8 D9
E4
F4
G4
H4
F5
G5
F8
G8
E9
F9
G9
H9
C3
J4 J5 J6 J7 J8 J9

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430FG47xIPN
80-pin
IPN PACKAGE
(TOP VIEW)
DVCC1 60
59
80 79
P6.3/A1+/OA1O P6.4/A1-/OA1FB P6.5/OA0I2 (SW0B) P6.6/OA1I1 (SW1A)
P6.7/OA1I2/SVSIN (SW1B)
XIN
XOUT
VREF
GND
P2.6/CAOUT/S2
P2.7/S3
P4.7/S4
P4.6/S5
P4.5/S6
P4.0/S11
S12
S13
S14 S15 S17 S18 S19
P5.0/S20 P5.1/S21
S22
P3.2/UCB0SOMI/UCB0SCL/S27
P3.1/UCB0SIMO/UCB0SDA/S26
P3.0/UCB0STE/UCA0CLK
P5.7/R03
DVCC2
DVSS1
DVSS2 P6.2/OA0I1 (SW0A)
P6.1/A0-/OA0FB P6.0/A0+/OA0O
RST/NMI TCK TMS TDI/TCLK TDO/TDI
P5.6/LCDREF/R13
78 77 76 75 74 73 72 71 70 69 68 67 66 65
58
57
56
55
54
53
52
51
50
49
48
47
46
45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
64 63 62 61
37
S23
38 39 40
44
43
42
41
P4.4/S7
P4.3/S8
P4.2/S9
P4.1/S10 17
18
19
20
P3.7/S31
P3.6/S30
P3.5/S29
P3.4/S28
P3.3/UCB0CLK/UCA0STE
S24 S25
COM0
P5.2/COM1 P5.3/COM2 P5.4/COM3
P2.5/UCA0RXD/UCA0SOMI P2.4/UCA0TXD/UCA0SIMO P2.3/TB2
P2.2/TB1
P2.1/TB0/S0
P2.0/TA2/S1
P1.7/CA1/A2+
P1.6/CA0/A2-/OA0I0/DAC0
P1.5/TACLK/ACLK/A3+
P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1
P1.3/TBOUTH/SVSOUT/A4+/OA1I3 (SW1C)
P1.2/TA1/A4-/OA0I3 (SW0C)
P1.1/TA0/MCLK/OA1RFB
P1.0/TA0/OA0RFB
AVCC
AVSS
LCDCAP/R33
P5.5/R23
XT2OUT XT2IN
S16
GND

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
Oscillators
FLL+
Brownout
Protection
SVS,
SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15-Bit
Timer_A3
3 CC
Registers
CPU
64kB
incl. 16
Registers
EEM
JTAG
Interface
OA0, OA1
2 OpAmps
Basic
Timer &
Real-
Time
Clock
LCD_A
128
Segments
1,2,3,4
Mux
Timer_B3
3 CC
Registers,
Shadow
Reg
SD16_A
with
Buffer
1 Channel
Sigma-
Delta A/D
Converter
Comparator
_A
AVCC AVSS P1.x/P2.x
2x8
P3.x/P4.x
P5.x/P6.x
4x8
SMCLK
ACLK
MDB
MAB
DAC12
12-Bit
2
Channels
Voltage
Out
Ports
P1/P2
2x8 I/O
Interrupt
capability
XIN/
XT2IN
22
XOUT/
XT2OUT
RAM
2kB
2kB
2kB
Flash
60kB
48kB
32kB
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
Ports
P3/P4
P5/P6
4x8 I/O

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 80
PIN
113
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
AVCC 52 F12 Analog supply voltage, positive terminal.
AVSS 53 E12 Analog supply voltage, negative terminal.
DVCC1 1A1 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS1 79 A3 Digital supply voltage, negative terminal. Supplies all digital parts.
DVCC2 80 A2 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS2 78 B2
B3 Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TA0/
OA0RFB 58 C11 I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Range switch to OA0 output
BSL transmit
P1.1/TA0/MCLK/
OA1RFB 57 C12 I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0B input, compare: Out0 output
MCLK signal output
Range switch to OA1 output
BSL receive
P1.2/TA1/A4--/
OA0I3 (SW0C) 56 D11 I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
SD16 negative analog input A4
OA0, analog input I3
P1.3/TBOUTH/
SVSOUT/A4+/
OA1I3 (SW1C)
55 D12 I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB2
SVS comparator output
SD16 positive analog input A4
OA1, analog input I3
P1.4/TBCLK/
SMCLK/A3--/
OA1I0/DAC1
54 E11 I/O
General-purpose digital I/O pin/
Timer_B, clock signal TBCLK input
SMCLK signal output
SD16 negative analog input A3
OA1, analog input I0
DAC12.1 output
P1.5/TACLK/
ACLK/A3+ 51 F11 I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
SD16 positive analog input A3
P1.6/CA0/A2--/
OA0I0/DAC0 50 G12 I/O
General-purpose digital I/O pin
Comparator_A input 0
SD16 negative analog input A2
OA0, analog input I0
DAC12.0 output
P1.7/CA1/A2+ 49 G11 I/O
General-purpose digital I/O pin
Comparator_A input 1
SD16 positive analog input A2
P2.0/TA2/S1 4C2
C3 I/O
General-purpose digital I/O pin
Timer_A, capture: CCI2A/B input, compare: Out2 output
LCD segment output 1
P2.1/TB0/S0 3C1 I/O
General-purpose digital I/O pin
Timer_B, capture: CCI0A/B input, compare: Out0 output
LCD segment output 0

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 80
PIN
113
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
P2.2/TB1 2B1 I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output
P2.3/TB2 77 B4 I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output
P2.4/UCA0TXD/
UCA0SIMO 76 A4 I/O General-purpose digital I/O pin USCIA transmit data output in UART mode, slave data in/master out in SPI mode
P2.5/UCA0RXD/
UCA0SOMI 75 D4 I/O General-purpose digital I/O pin USCI A0 receive data input in UART mode, slave data out/master in in SPI mode
P2.6/CAOUT/S2 5D1 I/O
General-purpose digital I/O pin
Comparator_A output
LCD segment output 2
P2.7/S3 6D2 I/O General-purpose digital I/O pin
LCD segment output 3
P3.0/UCB0STE/
UCA0CLK 41 M12 I/O General-purpose digital I/O pin USCI B0 slave transmit enable/USCI A0 clock input/output
P3.1/UCB0SIMO/
UCB0SDA/S26 42 L12 I/O
General-purpose digital I/O pin
USCI B0 slave in/master out in SPI mode, SDA I2CdatainI
2C mode
LCD segment output 26
P3.2/UCB0SOMI/
UCB0SCL/S27 43 K11 I/O
General-purpose digital I/O pin
USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
LCD segment output 27
P3.3/UCB0CLK/
UCA0STE 44 K12 I/O General-purpose digital I/O USCI B0 clock input/output, USCI A0 slave transmit enable
P3.4/S28 45 J11 I/O General-purpose digital I/O pin
LCD segment output 28
P3.5/S29 46 J12 I/O General-purpose digital I/O pin
LCD segment output 29
P3.6/S30 47 H11 I/O General-purpose digital I/O pin
LCD segment output 30
P3.7/S31 48 H12 I/O General-purpose digital I/O pin
LCD segment output 31
P4.0/S11 18 K2 I/O General-purpose digital I/O pin
LCD segment output 11
P4.1/S10 17 K1 I/O General-purpose digital I/O pin
LCD segment output 10
P4.2/S9 16 J2 I/O General-purpose digital I/O pin
LCD segment output 9
P4.3/S8 15 J1 I/O General-purpose digital I/O pin
LCD segment output 8
P4.4/S7 14 H2 I/O General-purpose digital I/O pin
LCD segment output 7
P4.5/S6 13 H1 I/O General-purpose digital I/O pin
LCD segment output 6
P4.6/S5 12 G2 I/O General-purpose digital I/O pin
LCD segment output 5
P4.7/S4 11 G1 I/O General-purpose digital I/O pin
LCD segment output 4

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 80
PIN
113
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
COM0 33 L8 OCommon output, COM0--3 are used for LCD backplanes
P5.0/S20 27 L5 I/O General-purpose digital I/O pin
LCD segment output 20
P5.1/S21 28 M5 I/O General-purpose digital I/O pin
LCD segment output 21
P5.2/COM1 34 M8 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.3/COM2 35 L9 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.4/COM3 36 M9 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
LCDCAP/R33 37 J9 I/O Capacitor connection for LCD charge pump
input port of most positive analog LCD level (V4)
P5.5/R23 38 M10 I/O General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)
P5.6/LCDREF/
R13 39 L10 I/O General-purpose digital I/O pin
External LCD reference voltage input
input port of the third most positive analog LCD level (V3 or V2)
P5.7/R03 40 M11 I/O General-purpose digital I/O pin
input port of the fourth most positive analog LCD level (V1)
P6.0/A0+/OA0O 67 B8 I/O
General-purpose digital I/O pin
SD16 positive analog input A0
OA0, output
P6.1/A0--/OA0FB 66 B9 I/O
General-purpose digital I/O pin
SD16 positive negative input A0
OA0, analog input feedback
P6.2/OA0I1
(SW0A) 65 A9 I/O General-purpose digital I/O pin OA0, analog input I1
P6.3/A1+/OA1O 64 D9 I/O
General-purpose digital I/O pin
SD16 positive analog input A1
OA1, output
P6.4/A1--/OA1FB 63 A10 I/O
General-purpose digital I/O pin
SD16 positive negative input A1
OA1, analog input feedback
P6.5/OA0I2
(SW0B) 62 B10 I/O General-purpose digital I/O pin OA0, analog input I2
P6.6/OA1I1
(SW1A) 61 A11 I/O General-purpose digital I/O pin OA1, analog input I1
P6.7/OA1I2/
SVSIN (SW1B) 59 B12 I/O
General-purpose digital I/O pin
OA1, analog input I2
SVS input
S12 19 L1 OLCD segment output 12
S13 20 M1 OLCD segment output 13
S14 21 M2 OLCD segment output 14
S15 22 M3 OLCD segment output 15
S16 23 L3 OLCD segment output 16

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 80
PIN
113
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
S17 24 L4 OLCD segment output 17
S18 25 M4 OLCD segment output 18
S19 26 J4 OLCD segment output 19
S22 29 L6 OLCD segment output 22
S23 30 M6 OLCD segment output 23
S24 31 L7 OLCD segment output 24
S25 32 M7 OLCD segment output 25
GND 7E2 Ground. It is used to shield the oscillator. See Note 1.
XIN 8E1 IInput port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9F1 OOutput port for crystal oscillator XT1. Standard or watch crystals can be connected.
GND 10 F2 Ground. It is used to shield the oscillator. See Note NO TAG.
VREF 60 A12 OInput for an external reference voltage/internal reference voltage output
RST/NMI 74 B5 IReset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).
TCK 73 A5 ITest clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader
start.
TDI/TCLK 71 A6 ITest data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI 70 B7 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 72 B6 ITest mode select. TMS is used as an input port for device programming and test.
XT2OUT 68 A8 OOutput terminal of crystal oscillator XT2
XT2IN 69 A7 IInput port for crystal oscillator XT2
Reserved NA B11,
D6, D7,
D8, E4,
E5, E6,
E7, E8,
E9, F4,
F5, F8,
F9, G4,
G5,G8,
G9, H4,
H5, H6,
H7, H8,
H9, J5,
J6, J7,
J8, L2,
L11
BGA package unused balls. Connection to DVSS/AVSS recommended.
NOTE 1: It is recommended to connect GND externally to DVss.

General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16--bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats, and Table 2 lists the address
modes.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register FFMOV Rs,Rd MOV R10,R11 R10 —> R11
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)
Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)
Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)
Indirect
autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11 R10 + 2—> R10
Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)
NOTE: S = source D = destination

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
-- All clocks are active
DLow-power mode 0 (LPM0)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- FLL+ loop control remains active
DLow-power mode 1 (LPM1)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- FLL+ loop control is disabled
DLow-power mode 2 (LPM2)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator remains enabled
-- ACLK remains active
DLow-power mode 3 (LPM3)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- ACLK remains active
DLow-power mode 4 (LPM4)
-- CPU is disabled
-- ACLK is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- Crystal oscillator is stopped

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power--up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out--of--Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset 0xFFFE 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2 and 4)
(Non)maskable
(Non)maskable
(Non)maskable
0xFFFC 14
Timer_B3 TBCCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13
Timer_B3 TBCCR1 CCIFG1 ... TBCCR3 CCIFG3,
TBIFG (see Notes 1 and 2) Maskable 0xFFF8 12
Comparator_A CAIFG Maskable 0xFFF6 11
Watchdog Timer+ WDTIFG Maskable 0xFFF4 10
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Notes 1 and 5)
Maskable 0xFFF2 9
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 1 and 6)
Maskable 0xFFF0 8
SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0xFFEE 7
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2) Maskable 0xFFEA 5
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4
DAC12 DAC12_0IFG, DAC12_1IFG Maskable 0xFFE6 3
Maskable 0xFFE4 2
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1
Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. Access and key violations, KEYV and ACCVIFG.
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address76543210
00h ACCVIE NMIIE OFIE WDTIE
rw--0 rw--0 rw--0 rw--0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE Oscillator fault enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address76543210
01h BTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0 rw--0
UCA0RXIE USCI_A0 receive interrupt enable
UCA0TXIE USCI_A0 transmit interrupt enable
UCB0RXIE USCI_B0 receive interrupt enable
UCB0TXIE USCI_B0 transmit interrupt enable
BTIE Basic timer interrupt enable

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt flag register 1 and 2
Address76543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw--0 rw--(0) rw--(1) rw--1 rw--(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault.
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG Power-on interrupt flag. Set on VCC power-up.
NMIIFG Set via RST/NMI pin.
Address76543210
03h BTIFG UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw--0 rw--1 rw--0 rw--1 rw--0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG USCI_B0 transmit interrupt flag
BTIFG Basic Timer1 interrupt flag
Legend rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1):
SFR bit is not present in device

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
memory organization
MSP430FG477 MSP430FG478 MSP430FG479
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh to 0FFE0h
0FFFFh to 08000h
48KB
0FFFFh to 0FFE0h
0FFFFh to 04000h
60KB
0FFFFh to 0FFE0h
0FFFFh to 01100h
Information memory Size
Flash
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Boot memory Size
ROM
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
RAM Size 2KB
09FFh to 0200h
2KB
09FFh to 0200h
2KB
09FFh to 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL FUNCTION PN PACKAGE PINS ZQW PACKAGE PINS
Data Transmit 58 - P1.0 C11 - P1.0
Data Receive 57 - P1.1 C12 - P1.1
flash memory (Flash)
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
DSegment A might contain calibration data. After reset, segment A is protected against programming or
erasing. It can be unlocked, but care should be taken not to erase this segment if this calibration data is
required.
DFlash content integrity check with marginal read modes.

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system in the MSP430FG47x is supported by the FLL+ module, which includes support for a
32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency
crystal oscillator (XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is
designed to meet the requirements of both low system cost and low power consumption. The FLL+ features
digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on
clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented, ports P1 through P6.
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year
correction.
LCD_A driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore, it is possible to control the level of the LCD voltage and, thus, contrast in software.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER DE
V
ICE INPUT MODULE INPUT MODULE MODULE
O
U
T
P
U
T
OUTPUT PIN NUMBER
PN ZQW
D
E
V
I
C
E
I
N
P
U
T
SIGNAL
M
O
D
U
L
E
I
N
P
U
T
NAME
M
O
D
U
L
E
BLOCK OUTPUT
SIGNAL PN ZQW
P1.5 -- 51 F11 TACLK TACLK
ACLK ACLK
T
i
m
e
r
N
A
SMCLK SMCLK Timer N
A
P1.5 -- 51 F11 TAINCLK INCLK
P1.0 -- 58 C11 TA0 CCI0A P1.0 -- 58 C11
P1.1 -- 57 C12 TA0 CCI0B
C
C
R
0
T
A
0
P1.1 -- 57 C12
DVSS GND CCR0 T
A
0
DVCC VCC
P1.2 -- 56 D11 TA1 CCI1A P1.2 -- 56 D11
CAOUT (internal) CCI1B
C
C
R
1
T
A
1
DVSS GND CCR1 T
A
1
DVCC VCC
P2.0 -- 4 C2 TA2 CCI2A P2.0 -- 4 C2
ACLK (internal) CCI2B
C
C
R
2
T
A
2
DVSS GND CCR2 T
A
2
DVCC VCC

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3 SIGNAL CONNECTIONS
INPUT PIN NUMBER DE
V
ICE INPUT MODULE INPUT MODULE MODULE
O
U
T
P
U
T
OUTPUT PIN NUMBER
PN ZQW
D
E
V
I
C
E
I
N
P
U
T
SIGNAL
M
O
D
U
L
E
I
N
P
U
T
NAME
M
O
D
U
L
E
BLOCK OUTPUT
SIGNAL PN ZQW
P1.4 -- 54 E11 TBCLK TBCLK
ACLK ACLK
SMCLK SMCLK Timer NA
P1.4 -- 54 E11 TBCLK
(See Note 1)
INCLK
P2.1 -- 3 C1 TB0 CCI0A P2.1 -- 3 C1
P2.1 -- 3 C1 TB0 CCI0B
C
C
R
0
T
B
0
VSS GND CCR0 TB0
VCC VCC
P2.2 -- 2 B1 TB1 CCI1A P2.2 -- 2 B1
P2.2 -- 2 B1 TB1 CCI1B
C
C
R
1
T
B
1
VSS GND CCR1 TB1
VCC VCC
P2.3 -- 77 B4 TB2 CCI2A P2.3 -- 77 B4
ACLK (internal) CCI2B
C
C
R
2
T
B
2
VSS GND CCR2 TB2
VCC VCC
NOTE 1: The inversion of TBCLK is done inside the module.
universal serial communication interfaces (USCIs) (USCI_A0, USCI_B0)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin), I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART and IrDA.
USCI_B0 provides support for SPI (3 pin or 4 pin) and I2C.
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SD16_A
The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and a reference generator. In addition to external analog inputs, an internal VCC sense and
temperature sensor are also available.
DAC12
The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 may be used in 8-bit or 12-bit mode.
When multiple DAC12 modules are present, they may be grouped together for synchronous operation.
OA
The MSP430FG47x has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA0 SIGNAL CONNECTIONS
INPUT PIN NUMBER DEVICE
I
N
P
U
T
MODULE MODULE MODULE
O
U
T
P
U
T
OUTPUT PIN NUMBER
PN ZQW
INPUT
SIGNAL
M
O
D
U
L
E
INPUT NAME
M
O
D
U
L
E
BLOCK OUTPUT
SIGNAL PN ZQW
P1.6 -- 50 G12 OA0I0 OAxI0 P6.0 -- 67 B8
P6.2 -- 65 A9 OA0I1 OAxI1
O
A
0
O
A
0
O
U
T
O
A
0
O
P6.5 -- 62 B10 OA0I2 OAxIA O
A
0 O
A
0OUT O
A
0O
P1.2 -- 56 D11 OA0I3 OAxIB
P1.4 -- 54 E11 OA1I0 OAxI0 P6.4 -- 64 A10
P6.6 -- 61 A11 OA1I1 OAxI1
O
A
1
O
A
1
O
U
T
O
A
1
O
P6.7 -- 59 B12 OA1I2 OAxIA O
A
1 O
A
1OUT O
A
1O
P1.3 -- 55 D12 OA1I3 OAxIB

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER
SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer_B3 Capture/compare register 2 TBCCR2 0196h
T
i
m
e
r
_
B
3
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
2
Capture/compare register 1
T
B
C
C
R
2
TBCCR1
0
1
9
6
h
0194h
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
1
Capture/compare register 0
T
B
C
C
R
1
TBCCR0
0
1
9
4
h
0192h
p
/
p
g
Timer_B register TBR 0190h
_
g
Capture/compare control 2 TBCCTL2 0186h
p
p
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Capture/compare register 2 TACCR2 0176h
T
i
m
e
r
_
A
3
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
2
Capture/compare register 1
T
A
C
C
R
2
TACCR1
0
1
7
6
h
0174h
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
1
Capture/compare register 0
T
A
C
C
R
1
TACCR0
0
1
7
4
h
0172h
p
/
p
g
Timer_A register TAR 0170h
_
g
Capture/compare control 2 TACCTL2 0166h
p
p
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Flash control 4
F
l
h
l
FCTL4
F
C
T
L
01BEh
C
h
Flash control 3
F
l
a
s
h
c
o
n
t
r
o
l
2
FCTL3
F
C
T
L
2
012Ch
0
1
2
A
h
F
l
as
h
con
t
ro
l
2
Flash control 1
F
C
T
L
2
FCTL1
0
1
2
A
h
0128h
DAC12 DAC12_1 data DAC12_1DAT 01CAh
D
A
C
1
2
D
A
C
1
2
_
1
d
a
t
a
DAC12_1 control
D
A
C
1
2
_
1
D
A
T
DAC12_1CTL
0
1
C
A
h
01C2h
D
A
C
1
2
_
1
c
o
n
t
r
o
l
DAC12_0 data
D
A
C
1
2
_
1
C
T
L
DAC12_0DAT
0
1
C
2
h
01C8h
_
DAC12_0 control
_
DAC12_0CTL 01C0h
SD16_A General control SD16CTL 0100h
S
D
1
6
_
A
(see also:
P
i
h
l
i
t
h
G
e
n
e
r
a
l
c
o
n
t
r
o
l
Channel 0 control
S
D
1
6
C
T
L
SD16CCTL0
0
1
0
0
h
0102h
Peripherals with
B
y
t
e
A
c
c
e
s
s
)
C
h
a
n
n
e
l
0
c
o
n
t
r
o
l
Channel 0 conversion memory
S
D
1
6
C
C
T
L
0
SD16MEM0
0
1
0
2
h
0112h
B
yte
A
ccess
)
y
Interrupt vector word register SD16IV 0110h
OA switches Switch control register 1 SWCTL_1 00CEh
PERIPHERALS WITH BYTE ACCESS
OA switches Switch control register
Switch control register 1
SWCTL
SWCTL1
00CFh
00CEh
OA1 Operational amplifier 1 control register 1 OA1CTL1 00C3h
p
p
g
Operational amplifier 1 control register 0 OA1CTL0 00C2h
OA0 Operational amplifier 0 control register 1 OA0CTL1 00C1h
p
p
g
Operational amplifier 0 control register 0 OA0CTL0 00C0h
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 input control
Analog enable
SD16INCTL0
SD16AE
0B0h
0B7h