Texas Instruments MSP430F4152IPM User manual

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow Power Consumption
Active Mode: 220 Aat1MHz,2.2V
Standby Mode: 0.9 A
Off Mode (RAM Retention): 0.1 A
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 s
-- Internal Very Low Power,
Low-Frequency Oscillator
D16-Bit RISC Architecture,
125-ns Instruction Cycle Time
D16-Bit Timer_A With Three
Capture/Compare Registers
D16-Bit Timer_A With Five Capture/Compare
Registers
DTwo Universal Serial Communication
Interfaces (USCIs)
USCI_A0
-- Enhanced UART Supporting
Auto-Baudrate Detection
-- IrDA Encoder and Decoder
-- Synchronous SPI
USCI_B0
-- I 2 C
-- Synchronous SPI
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DIntegrated LCD Driver With Contrast
Control for Up to 144 Segments
DBasic Timer With Real Time Clock Feature
DBrownout detector
DOn-Chip Comparator for Analog Signal
Compare Function or Slope A/D
D10-Bit 200-ksps Analog-to-Digital (A/D)
Converter With Internal Reference,
Sample-and-Hold, Autoscan, and Data
Transfer Controller
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DBootstrap Loader
DOn-Chip Emulation Module
DFamily Members Include:
MSP430F4152: 16KB+256B Flash Memory
512B RAM
MSP430F4132: 8KB+256B Flash Memory
512B RAM
DAvailable in 64-Pin QFP Package and
48-Pin QFN Package (See Available
Options)
DFor Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generator that contribute to maximum code
efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 s.
The MSP430F41x2 is a microcontroller configuration with two 16-bit timers, a basic timer with a real--time clock,
a 10-bit A/D converter, a versatile analog comparator, two universal serial communication interfaces, up to 48
I/O pins, and a liquid crystal display driver.
Typical applications for this device include analog and digital sensor systems, remote controls, thermostats,
digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
AVAILABLE OPTIONS†
T
PACKAGED DEVICES‡
TAPLASTIC 64-PIN QFP (PM) PLASTIC 48-PIN QFN (RGZ)
-- 4 0 Cto85CMSP430F4152IPM
MSP430F4132IPM
MSP430F4152IRGZ
MSP430F4132IRGZ
†For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
-- MSP-FET430UIF (USB)
-- MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
-- MSP-FET430U64A (PM package)
DProduction Programmer
-- MSP-GANG430

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430F41x2IPM (QFP)
48
47
64 63
P6.1/UCB0SOMI/UCB0SCL
P6.2/UCB0SIMO/UCB0SDA
P6.3/UCB0STE/UCA0CLK/A3/CA5/VeREF-/VREF-
XIN
XOUT
P4.6/S1
P4.5/S2
P4.4/S3
P4.3/S4
P4.2/S5 P4.1/S6 P4.0/S7 P2.7/S8 P2.6/S9
P2.5/S10 P2.4/S11
P2.3/TA1.4/S12 P2.2/TA1.3/S13 P2.1/TA1.2/S14 P2.0/TA1.1/S15
P3.7/S16 P3.6/S17 P3.5/S18
P3.4/CAOUT/S19
P3.3/TA0.0/TA1CLK/S20
P3.2/TA1.4/S21
P5.7/COM0
P5.6/COM1
P5.5/COM2
P5.4/COM3
P5.3/R03
P5.2/R13/LCDREF
P5.1/R23
R33/LCDCAP
AVCC
P6.0/TA1.2/A2/CA4 P7.5/TA1.3/A1/CA3 P7.4/TA1.4/A0/CA2
RST/NMI/SBWTDIO
P7.3/TCK/S35 P7.2/TMS/S34 P7.1/TDI/TCLK/S33 P7.0/TDO/TDI/S32 P1.0/TA0.0/S31 P1.1/TA0.0/MCLK/S30
62 61 60 59 58 57 56 55 54 53 52 51 50 49
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P3.1/TA1.3/S22
P3.0/TA1.2/S23
P5.0/TA1.1/S24
P4.7/ADC10CLK/S0
P1.4/TA1.0/S27 P1.2/TA0.1/S29 P1.3/TA1.0/SVSOUT/S28
P6.4/UCB0CLK/UCA0STE/A4/CA6/VeREF+/VREF+
P6.5/UCA0RXD/UCA0SOMI/A5
64-pin
PM PACKAGE
(TOP VIEW)
P6.7/A7/CA7/SVSIN
P7.6/TA0.2/S25
TEST/SBWTCLK
P6.6/UCA0TXD/UCA0SIMO/A6
AVSS
DVCC
DVSS
P1.7/TA0CLK/CAOUT/CA1
P1.5/TA0CLK/CAOUT/S26
P1.6/ACLK/CA0

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430F41x2IRGZ (QFN)†
XIN
XOUT
P4.6/S1
P4.5/S2
P4.4/S3
P4.3/S4
P4.2/S5 P4.1/S6 P4.0/S7 P2.7/S8 P2.6/S9
P2.5/S10 P2.4/S11
P2.3/TA1.4/S12 P2.2/TA1.3/S13 P2.1/TA1.2/S14 P2.0/TA1.1/S15
P5.7/COM0
P5.6/COM1
P5.5/COM2
P5.4/COM3
P5.3/R03
P5.2/R13/LCDREF
P5.1/R23
R33/LCDCAP
AVCC
RST/NMI/SBWTDIO
P4.7/ADC10CLK/S0
TEST/SBWTCLK AVSS
DVCC
DVSS 48-pin
RGZ PACKAGE
(TOP VIEW)
36
35
48 47 46 45 44 43 42 41 40 39 38 37
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
P6.0/TA1.2/A2/CA4 P7.5/TA1.3/A1/CA3 P7.4/TA1.4/A0/CA2 P1.0/TA0.0/S31
P1.7/TA0CLK/CAOUT/CA1
P1.6/ACLK/CA0
P6.1
P6.2
P6.7/A7/CA7/SVSIN
P7.3/TCK/S35 P7.2/TMS/S34 P7.1/TDI/TCLK/S33 P7.0/TDO/TDI/S32
P3.4/CAOUT/S19
P1.1/TA0.0/MCLK/S30
P1.5/TA0CLK/CAOUT/S26
†“Not available” pins in the 48-pin package should be initialized to output direction.

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
Oscillators
FLL+
VLO
Brownout
Protection
SVS,
SVM
RST/NMI
DVCC DVSS
MCLK
Watchdog
WDT+
15--Bit
Timer _A5
5CC
Registers
CPU
64kB
incl. 16
Registers
EEM
JTAG
Interface
Basic
Timer &
Real--
Time
Clock
LCD_A
144
Segments
1,2,3,4
Mux
Comparator
_A+
AVCC AVSS P1.x/P2.x
2x8
P3.x/P4.x
2x8
SMCLK
ACLK
MDB
MAB
Ports
P1/P2
2x8 I/O
Interrupt
capability
XIN XOUT
RAM
512B
512B
Flash
16kB
8kB
USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
Ports
P3/P4
2x8 I/O
ADC10
10--bit
8 Channels
Autoscan
DTC
Timer _A3
3CC
Registers
Ports
P5/P6
2x8 I/O
P5.x/P6.x
2x8
S p y --B i --
Wire
Port
P7
1x7 I/O
1x7
P7.x
NOTE: The USCI A0 and USCI B0 cannot be used in the 48-pin package options (RGZ).

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 64
PIN
48
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
P1.0/TA0.0/S31 53 37 I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI0A input, compare: Out0 output
LCD segment output
P1.1/TA0.0/
MCLK/S30 52 36 I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI0B input
MCLK signal output
LCD segment output
P1.2/TA0.1/S29 51 -- I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI1A input, compare: Out1 output
LCD segment output
P1.3/TA1.0/
SVSOUT/S28 50 -- I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI0B input
SVS comparator output
LCD segment output
P1.4/TA1.0/S27 49 -- I/O
General-purpose digital I/O pin/
Timer1_A5, capture: CCI0A input, compare: Out0 output
LCD segment output
P1.5/TA0CLK/
CAOUT/S26 48 35 I/O
General-purpose digital I/O pin
Timer0_A3, clock signal TACLK input
Comparator_A output
LCD segment output
P1.6/ACLK/CA0 47 34 I/O
General-purpose digital I/O pin
Comparator_A input 0
ACLK signal output
P1.7/TA0CLK
CAOUT/CA1 46 33 I/O
General-purpose digital I/O pin
Timer0_A3, clock signal TACLK input
Comparator_A output
Comparator_A input 1
P2.0/TA1.1/S15 27 23 I/O
General-purpose digital I/O pin
Timer1_A5, compare: Out1 Output
LCD segment output
P2.1/TA1.2/S14 26 22 I/O
General-purpose digital I/O pin
Timer1_A5, compare: Out2 Output
LCD segment output
P2.2/TA1.3/S13 25 21 I/O
General-purpose digital I/O pin
Timer1_A5, compare: Out3 Output
LCD segment output
P2.3/TA1.4/S12 24 20 I/O
General-purpose digital I/O pin
Timer1_A5, compare: Out4 output
LCD segment output
P2.4/S11 23 19 I/O General-purpose digital I/O pin
LCD segment output
P2.5/S10 22 18 I/O General-purpose digital I/O pin
LCD segment output
P2.6/S9 21 17 I/O General-purpose digital I/O pin
LCD segment output
P2.7/S8 20 16 I/O General-purpose digital I/O pin
LCD segment output

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 64
PIN
48
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
P3.0/TA1.2/S23 35 -- I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI2A input, compare: Out2 output
LCD segment output
P3.1/TA1.3/S22 34 -- I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI3A input, compare: Out3 output
LCD segment output
P3.2/TA1.4/S21 33 -- I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI4A input, compare: Out4 output
LCD segment output
P3.3/TA0.0/
TA1CLK/S20 32 -- I/O
General-purpose digital I/O pin
Timer0_A3, compare: Out0 output
Timer1_A5, clock signal TACLK input
LCD segment output
P3.4/CAOUT/S19 31 24 I/O
General-purpose digital I/O pin
Comparator_A output
LCD segment output
P3.5/S18 30 -- I/O General-purpose digital I/O pin
LCD segment output
P3.6/S17 29 -- I/O General-purpose digital I/O pin
LCD segment output
P3.7/S16 28 -- I/O General-purpose digital I/O pin
LCD segment output
P4.0/S7 19 15 I/O General-purpose digital I/O pin
LCD segment output
P4.1/S6 18 14 I/O General-purpose digital I/O pin
LCD segment output
P4.2/S5 17 13 I/O General-purpose digital I/O pin
LCD segment output
P4.3/S4 16 12 I/O General-purpose digital I/O pin
LCD segment output
P4.4/S3 15 11 I/O General-purpose digital I/O pin
LCD segment output
P4.5/S2 14 10 I/O General-purpose digital I/O pin
LCD segment output
P4.6/S1 13 9I/O General-purpose digital I/O pin
LCD segment output
P4.7/ADC10CLK/
S0 12 8I/O
General-purpose digital I/O pin
ADC10, conversion clock
LCD segment output
P5.0/TA1.1/S24 44 -- I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI1A input, compare: Out1 output
LCD segment output
LCDCAP/R33 43 32 I/O Capacitor connection for LCD charge pump
input port of the most positive analog LCD level (V4)
P5.1/R23 42 31 I/O General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)
P5.2/LCDREF/
R13 41 30 I/O
General-purpose digital I/O pin
External LCD reference voltage input
input port of the third most positive analog LCD level (V3 or V2)

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 64
PIN
48
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
P5.3/R03 40 29 I/O General-purpose digital I/O pin
input port of the fourth most positive analog LCD level (V1)
P5.4/COM3 39 28 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.5/COM2 38 27 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.6/COM1 37 26 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P5.7/COM0 36 25 I/O General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes
P6.0/TA1.2/A2†/
CA4 63 47 I/O
General-purpose digital I/O pin
Timer1_A5, compare: Out2 output
ADC10 analog input A2†
Comparator_A input 4
P6.1/
UCB0SOMI†/
UCB0SCL†
1 1 I/O General-purpose digital I/O pin
USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode†
P6.2/
UCB0SIMO†/
UCB0SDA†
2 2 I/O General-purpose digital I/O pin
USCI B0 slave in/master out in SPI mode, SDA I2CdatainI
2C mode†
P6.3/UCB0STE/
UCA0CLK/A3/
CA5/Veref--/Vref--
3-- I/O
General-purpose digital I/O pin
USCI B0 slave transmit enable/USCI A0 clock input/output
ADC10 analog input A3 / negative reference
Comparator_A input 5
P6.4/UCB0CLK/
UCA0STE/A4/
CA6/Veref+/Vref+
4-- I/O
General-purpose digital I/O pin
USCI B0 clock input/output, USCI A0 slave transmit enable
ADC10 analog input A4/ positive reference
Comparator_A input 6
P6.5/UCA0RXD/
UCA0SOMI/A5 5-- I/O
General-purpose digital I/O pin
USCI A0 receive data input in UART mode, slave data out/master in in SPI mode
ADC10 analog input A5
P6.6/UCA0TXD/
UCA0SIMO/A6 6-- I/O
General-purpose digital I/O pin
USCI A0 transmit data output in UART mode, slave data in/master out SPI mode
ADC10 analog input A6
P6.7/A7/CA7/
SVSIN 11 7I/O
General-purpose digital I/O pin
ADC10 analog input A7
Comparator_A input 7
SVS input
P7.0/TDO/TDI/
S32
54 38 I/O General-purpose digital I/O pin
JTAG test data output terminal or test data input in programming an test
LCD segment output
P7.1/TDI/TCLK/
S33
55 39 I/O General-purpose digital I/O pin
JTAG test data input or test clock input in programming an test
LCD segment output
P7.2/TMS/S34 56 40 I/O General-purpose digital I/O pin
JTAG test mode select, input terminal for device programming and test
LCD segment output
†64-pin package devices only

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NO.
I
/
O
D
E
S
C
R
I
P
T
I
O
N
NAME 64
PIN
48
PIN
I
/
O
D
E
S
C
R
I
P
T
I
O
N
P7.3/TCK/S35 57 41 I/O General-purpose digital I/O pin
Test clock input for device programming and test
LCD segment output
P7.4/TA1.4/
A0/CA2 60 44 I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI4B input, compare: Out4 output
ADC10 analog input A0
Comparator_A input 2
P7.5/TA1.3/
A1/CA3 61 45 I/O
General-purpose digital I/O pin
Timer1_A5, capture: CCI3B input, compare: Out3 output
ADC10 analog input A1
Comparator_A input 3
P7.6/TA0.2/S25 45 -- I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI2A input, compare: Out2 output
LCD segment output
AVCC 64 48 Analog supply voltage, positive terminal
AVSS 62 46 Analog supply voltage, negative terminal
DVCC 7 3 Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS 10 6Digital supply voltage, negative terminal. Supplies all digital parts.
XOUT 9 5 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.
XIN 8 4 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
RST/NMI/
SBWTDIO
58 42 IReset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/SBWTCLK 59 43 ISelects test mode for JTAG pins on Port7. The device protection fuse is connected to TEST.
Thermal Pad NA NA NA QFN package pad (RGZ package only). Connection to DVSS is recommended.

General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5
Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register FFMOV Rs,Rd MOV R10,R11 R10 —> R11
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) —> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)
Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)
Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)
Indirect
autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11 R10+2—>R10
Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)
NOTE: S = source, D = destination

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
-- All clocks are active
DLow-power mode 0 (LPM0)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- FLL+ loop control remains active
DLow-power mode 1 (LPM1)
-- CPU is disabled
-- ACLK and SMCLK remain active
-- FLL+ loop control is disabled
DLow-power mode 2 (LPM2)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator remains enabled
-- ACLK remains active
DLow-power mode 3 (LPM3)
-- CPU is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- ACLK remains active
DLow-power mode 4 (LPM4)
-- CPU is disabled
-- ACLK is disabled
-- MCLK, FLL+ loop control, and DCOCLK are disabled
-- DCO’s dc generator is disabled
-- Crystal oscillator is stopped

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU goes
into LPM4 immediately after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out--of--Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset 0xFFFE 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 4)
(Non)maskable
(Non)maskable
(Non)maskable
0xFFFC 14
Timer_A5 TA1CCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13
Timer_A5 TA1CCR1 to TACCR4 CCIFGs,
and TAIFG (see Notes 1 and 2) Maskable 0xFFF8 12
Comparator_A+ CAIFG Maskable 0xFFF6 11
Watchdog Timer+ WDTIFG Maskable 0xFFF4 10
USCI_A0/B0 Receive
UCA0RXIFG (see Note 1),
UCB0RXIFG (SPI mode), or
UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG (I2C mode)
(see Note 1)
Maskable 0xFFF2 9
USCI_A0/B0 Transmit
UCA0TXIFG (see Note 1),
UCB0TXIFG (SPI mode), or
UCB0RXIFG and UCB0TXIFG (I2C mode)
(see Note 1)
Maskable 0xFFF0 8
ADC10 ADC10IFG (see Note 2) Maskable 0xFFEE 7
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2) Maskable 0xFFEA 5
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4
0xFFE6 3
0xFFE4 2
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1
Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. Access and key violations, KEYV and ACCVIFG.

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address76543210
00h ACCVIE NMIIE OFIE WDTIE
rw--0 rw--0 rw--0 rw--0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE Oscillator fault enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address76543210
01h BTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw--0 rw--0 rw--0 rw--0 rw--0
UCA0RXIE USCI_A0 receive interrupt enable
UCA0TXIE USCI_A0 transmit interrupt enable
UCB0RXIE USCI_B0 receive interrupt enable
UCB0TXIE USCI_B0 transmit interrupt enable
BTIE Basic timer interrupt enable

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
interrupt flag register 1 and 2
Address76543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw--0 rw--(0) rw--(1) rw--1 rw--(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG Power-on interrupt flag. Set on VCC power--up.
NMIIFG Set via RST/NMI-pin
Address76543210
03h BTIFG UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw--0 rw--1 rw--0 rw--1 rw--0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG USCI_B0 transmit interrupt flag
BTIFG Basic Timer1 interrupt flag
Legend rw:
rw-0,1:
Bit can be read and written.
Bit can be read and written. It is Reset or set by PUC.
Bit can be read and written. It is Reset or set by POR.
rw-(0,1):
SFR bit is not present in device

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
memory organization
MSP430F4152 MSP430F4132
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh -- 0FFE0h
0FFFFh -- 0C000h
8KB
0FFFFh -- 0FFE0h
0FFFFh -- 0E000h
Information memory Size
Flash
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
Boot memory Size
ROM
1KB
0FFFh -- 0C00h
1KB
0FFFh -- 0C00h
RAM Size 512B
03FFh -- 0200h
512B
03FFh -- 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the MSP430 Memory Programming User’s Guide, literature
number SLAU265.
BSL FUNCTION PM PACKAGE PINS RGZ PACKAGE PINS
Data transmit 53 -- P1.0 37 -- P1.0
Data receive 52 -- P1.1 36 -- P1.1
flash memory (Flash)
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system in the MSP430F41x2 is supported by the FLL+ module that includes support for a 32768-Hz
watch crystal oscillator, an internal very low-power low--frequency oscillator, an internal digitally-controlled
oscillator (DCO), and an 8-MHz high-frequency crystal oscillator (XT1). The FLL+ clock module is designed to
meet the requirements of both low system cost and low power consumption. The FLL+ features a digital
frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency
to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock
source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or a very
low-power LF oscillator
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are seven 8-bit I/O ports implemented—ports P1 through P7. Port P7 is a 7-bit I/O port.
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
Basic Timer1 and Real-Time Clock (RTC)
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year
correction.
LCD_A driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2--MUX, 3--MUX, and 4--MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast in software.
Timer0_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER DE
V
ICE INPUT MODULE MODULE MODULE
O
U
T
P
U
T
OUTPUT PIN NUMBER
PM RGZ
D
E
V
I
C
E
I
N
P
U
T
SIGNAL
M
O
D
U
L
E
INPUT NAME
M
O
D
U
L
E
BLOCK OUTPUT
SIGNAL PM RGZ
48 -- P1.5
46 -- P1.7
35 -- P1.5
33 -- P1.7 TA0CLK TACLK
ACLK ACLK Timer N
A
SMCLK SMCLK
T
i
m
e
r
N
A
48 -- P1.5 35 -- P1.5 TA0CLK TACLK
53 -- P1.0 37 -- P1.0 TA0.0 CCI0A 53 -- P1.0 37 -- P1.0
52 -- P1.1 36 -- P1.1 TA0.0 CCI0B
C
C
R
0
T
A
0
32 -- P3.3 --
DVSS GND CCR0 T
A
0
DVCC VCC
51 -- P1.2 -- TA0.1 CCI1A 51 -- P1.2
CAOUT (internal) CCI1B
C
C
R
1
T
A
1
ADC10 (internal) ADC10 (internal)
DVSS GND CCR1 T
A
1
DVCC VCC
45 -- P7.6 -- TA0.2 CCI2A 45 -- P7.6 --
ACLK (internal) CCI2B
C
C
R
2
T
A
2
DVSS GND CCR2 T
A
2
DVCC VCC

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Timer1_A5
Timer_A5 is a 16-bit timer/counter with five capture/compare registers. Timer_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A5 SIGNAL CONNECTIONS
INPUT PIN NUMBER DE
V
ICE INPUT MODULE MODULE MODULE
O
U
T
P
U
T
OUTPUT PIN NUMBER
PM RGZ
D
E
V
I
C
E
I
N
P
U
T
SIGNAL
M
O
D
U
L
E
INPUT NAME
M
O
D
U
L
E
BLOCK OUTPUT
SIGNAL PM RGZ
32 -- P3.3 -- TA1CLK TACLK
ACLK ACLK
T
i
m
e
r
N
A
SMCLK SMCLK Timer N
A
32 -- P3.3 -- TA1CLK TACLK
49 -- P1.4 -- TA1.0 CCI0A 49 -- P1.4 --
50 -- P1.3 -- TA1.0 CCI0B
C
C
R
0
T
A
0
ADC10 (internal) ADC10 (internal)
DVSS GND CCR0 T
A
0
DVCC VCC
44 -- P5.0 -- TA1.1 CCI1A 44 -- P5.0 --
CAOUT (internal) CCI1B
C
C
R
1
T
A
1
27 -- P2.0 23 -- P2.0
DVSS GND CCR1 T
A
1ADC10 (internal) ADC10 (internal)
DVCC VCC
35 -- P3.0 -- TA1.2 CCI2A 35 -- P3.0 --
ACLK (internal) CCI2B
C
C
R
2
T
A
2
26 -- P2.1 22 -- P2.1
DVSS GND CCR2 T
A
263 -- P6.0 47 -- P6.0
DVCC VCC
34 -- P3.1 -- TA1.3 CCI3A 34 -- P3.1 --
61 -- P7.5 45 -- P7.5 TA1.3 CCI3B
C
C
R
3
T
A
3
25 -- P2.2 21 -- P2.2
DVSS GND CCR3 T
A
361 -- P7.5 45 -- P7.5
DVCC VCC
33 -- P3.2 -- TA1.4 CCI4A 33 -- P3.2 --
60 -- P7.4 44 -- P7.4 TA1.4 CCI4B
C
C
R
4
T
A
4
24 -- P2.3 20 -- P2.3
DVSS GND CCR4 T
A
460 -- P7.4 44 -- P7.4
DVCC VCC
universal serial communication interface (USCI) (USCI_A0, USCI_B0)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ADC10
The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer0_A3 Capture/compare register 2 TA0CCR2 0176h
T
i
m
e
r
0
_
A
3
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
2
Capture/compare register 1
T
A
0
C
C
R
2
TA0CCR1
0
1
7
6
h
0174h
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
1
Capture/compare register 0
T
A
0
C
C
R
1
TA0CCR0
0
1
7
4
h
0172h
p
/
p
g
Timer_A register TA0R 0170h
_
g
Capture/compare control 2 TA0CCTL2 0166h
p
p
Capture/compare control 1 TA0CCTL1 0164h
Capture/compare control 0 TA0CCTL0 0162h
Timer_A control TA0CTL 0160h
Timer_A interrupt vector TA0IV 012Eh
Timer1_A5 Capture/compare register 4
C
t
/
i
t
3
TA1CCR4
T
A
1
C
C
R
3
019A
0
1
9
8
Capture/compare register 3
Ca
p
ture
/
com
p
are re
g
ister 2
TA1CCR3
T
A
1CCR2
0198
0196h
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
2
Capture/compare register 1
T
A
1
C
C
R
2
TA1CCR1
0
1
9
6
h
0194h
Capture/compare register 0
T
i
m
e
r
A
r
e
g
i
s
t
e
r
TA1CCR0
T
A
1
R
0192h
0
1
9
0
h
T
i
m
e
r
_
A
r
e
g
i
s
t
e
r
Capture/compare control 4
T
A
1
R
TA1CCTL4
0
1
9
0
h
018A
p
p
Capture/compare control 3
C
a
p
t
u
r
e
/
c
o
m
p
a
r
e
c
o
n
t
r
o
l
2
TA1CCTL3
T
A
1
C
C
T
L
2
0188
0
1
8
6
h
C
ap
t
ure
/
compare con
t
ro
l
2
Capture/compare control 1
T
A
1
C
C
T
L
2
TA1CCTL1
0
1
8
6
h
0184h
p
/
p
Capture/compare control 0
T
i
m
e
r
A
c
o
n
t
r
o
l
TA1CCTL0
T
A
1
C
T
L
0182h
0
1
8
0
h
Timer
_
A
control
Timer_A interrupt vector
T
A
1CTL
TA1IV
0180h
011Eh
Flash Flash control 3 FCTL3 012Ch
F
l
a
s
h
F
l
a
s
h
c
o
n
t
r
o
l
3
Flash control 2
F
C
T
L
3
FCTL2
0
1
2
C
h
012Ah
F
l
a
s
h
c
o
n
t
r
o
l
2
Flash control 1
F
C
T
L
2
FCTL1
0
1
2
A
h
0128h
ADC10 ADC data transfer start address
ADC memory
ADC control register 1
ADC control register 0
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
ADC10SA
ADC10MEM
ADC10CTL1
ADC10CTL0
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
01BCh
01B4h
01B2h
01B0h
004Ah
004Bh
0049h
0048h

MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD_A LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDACTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
USCI A0/B0 USCI A0 auto baud rate control UCA0ABCTL 0x005D
/
USCI A0 transmit buffer UCA0TXBUF 0x0067
USCI A0 receive buffer UCA0RXBUF 0x0066
USCI A0 status UCA0STAT 0x0065
USCI A0 modulation control UCA0MCTL 0x0064
USCI A0 baud rate control 1 UCA0BR1 0x0063
USCI A0 baud rate control 0 UCA0BR0 0x0062
USCI A0 control 1 UCA0CTL1 0x0061
USCI A0 control 0 UCA0CTL0 0x0060
USCI A0 IrDA receive control UCA0IRRCTL 0x005F
USCI A0 IrDA transmit control UCA0IRTCTL 0x005E
USCI B0 transmit buffer UCB0TXBUF 0x006F
USCI B0 receive buffer UCB0RXBUF 0x006E
USCI B0 status UCB0STAT 0x006D
USCI B0 I2C Interrupt enable UCB0CIE 0x006C
USCI B0 baud rate control 1 UCB0BR1 0x006B
USCI B0 baud rate control 0 UCB0BR0 0x006A
USCI B0 control 1 UCB0CTL1 0x0069
USCI B0 control 0 UCB0CTL0 0x0068
USCI B0 I2C slave address UCB0SA 0x011A
USCI B0 I2C own address UCB0OA 0x0118
Comparator_A+ Comparator_A port disable CAPD 05Bh
p
_
Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
Brownout, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
FLL+ Clock FLL+ Control 2
FLL+ Control 1
FLL_CTL2
FLL_CTL1
055h
054h
FLL+ Control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h