Texas Instruments MSP430F5638 User manual

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Mixed Signal Microcontroller
Check for
Samples: MSP430F5638,MSP430F5637,MSP430F5636,MSP430F5635,MSP430F5634,MSP430F5633,MSP430F5632,MSP430F5631,
MSP430F5630
1FEATURES
23• Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers
• Ultralow-Power Consumption • Two Universal Serial Communication
– Active Mode (AM): Interfaces
All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support:
Execution (Typical) – Enhanced UART Supports Auto-
– Standby Mode (LPM3): Baudrate Detection
Watchdog With Crystal and Supply – IrDA Encoder and Decoder
Supervisor Operational, Full RAM – Synchronous SPI
Retention, Fast Wake-Up: – USCI_B0 and USCI_B1 Each Support:
1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) – I2C
– Shutdown RTC Mode (LPM3.5): – Synchronous SPI
Shutdown Mode, Active Real-Time Clock
With Crystal: • Full-Speed Universal Serial Bus (USB)
1.1 µA at 3.0 V (Typical) – Integrated USB-PHY
– Shutdown Mode (LPM4.5): – Integrated 3.3-V and 1.8-V USB Power
0.3 µA at 3.0 V (Typical) System
• Wake Up From Standby Mode in 3 µs (Typical) – Integrated USB-PLL
• 16-Bit RISC Architecture, Extended Memory, – Eight Input and Eight Output Endpoints
Up to 20-MHz System Clock • 12-Bit Analog-to-Digital Converter (ADC) With
• Flexible Power Management System Internal Shared Reference, Sample-and-Hold,
– Fully Integrated LDO With Programmable and Autoscan Feature
Regulated Core Supply Voltage • Dual 12-Bit Digital-to-Analog Converters
– Supply Voltage Supervision, Monitoring, (DACs) With Synchronization
and Brownout • Voltage Comparator
• Unified Clock System • Hardware Multiplier Supporting 32-Bit
– FLL Control Loop for Frequency Operations
Stabilization • Serial Onboard Programming, No External
– Low-Power Low-Frequency Internal Clock Programming Voltage Needed
Source (VLO) • Six-Channel Internal DMA
– Low-Frequency Trimmed Internal Reference • Real-Time Clock Module With Supply Voltage
Source (REFO) Backup Switch
– 32-kHz Crystals (XT1) • Family Members are Summarized in Table 1
– High-Frequency Crystals Up to 32 MHz • For Complete Module Descriptions, See the
(XT2) MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MSP430, Code Composer Studio are trademarks of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
APPLICATIONS
• Analog and Digital Sensor Systems
• Digital Motor Control
• Remote Controls
• Thermostats
• Digital Timers
• Hand-Held Meters
DESCRIPTION
The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in
3 µs (typical).
The MSP430F563x series are microcontroller configurations with a high-performance 12-bit analog-to-digital
converter (ADC), comparator, two universal serial communication interfaces (USCIs), USB 2.0, a hardware
multiplier, DMA, four 16-bit timers, a real-time clock module with alarm capabilities, and up to 74 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, and hand-held meters.
Table 1 summarizes the available family members.
Table 1. Family Members(1)(2)
USCI
Flash SRAM ADC12_A DAC12_A Comp_B Package
Channel A: Channel B:
Device Timer_A(4) Timer_B(5) I/O
(KB) (KB)(3) (Ch) (Ch) (Ch) Type
UART, SPI, I2C
IrDA, SPI
12 ext, 100 PZ,
MSP430F5638 256 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F5637 192 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F5636 128 16 + 2 5, 3, 3 7 2 2 2 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F5635 256 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F5634 192 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
12 ext, 100 PZ,
MSP430F5633 128 16 + 2 5, 3, 3 7 2 2 - 12 74
4 int 113 ZQW
100 PZ,
MSP430F5632 256 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
100 PZ,
MSP430F5631 192 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
100 PZ,
MSP430F5630 128 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at http://www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
http://www.ti.com/packaging.
(3) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

Unified
Clock
System
256KB
192KB
128KB
Flash
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
Interface/
Port PJ
SBW
PA PB PC PD
DMA
6 Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
USB
Full-speed
Comp_B
PJ.x
RTC_B
Battery
Backup
System
Unified
Clock
System
256KB
192KB
128KB
Flash
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
Interface/
Port PJ
SBW
PA PB PC PD
DMA
6 Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
RTC_B
Battery
Backup
System
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
ADC12_A
200 KSPS
16 Channels
(12 ext/4 int)
Autoscan
12 Bit
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
DAC12_A
12 bit
2 channels
voltage out
USB
Full-speed
Comp_B
PJ.x
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Functional Block Diagram, MSP430F5638, MSP430F5637, MSP430F5636
Functional Block Diagram, MSP430F5635, MSP430F5634, MSP430F5633
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

Unified
Clock
System
256KB
192KB
128KB
Flash
MCLK
ACLK
SMCLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
CPUXV2
and
Working
Registers
EEM
(L: 8+2)
XIN XOUT
JTAG/
Interface/
Port PJ
SBW
PA PB PC PD
DMA
6 Channel
XT2IN
XT OUT2
Power
Management
LDO
SVM/
Brownout
SVS
SYS
Watchdog
P2 Port
Mapping
Controller
I/O Ports
P3/P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
I/O Ports
P5/P6
2×8 I/Os
PC
1×16 I/Os
I/O Ports
P7/P8
1×6 I/Os
PD
1×14 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
MPY32
TA0
Timer_A
5 CC
Registers
TA1 and
TA2
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CRC16
USCI0,1
Ax: UART,
IrDA, SPI
Bx: SPI, I2C
DVCC DVSS AVCC AVSS
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x
RST/NMI
REF
Reference
1.5V, 2.0V,
2.5V
USB
Full-speed
Comp_B
PJ.x
RTC_B
Battery
Backup
System
16KB
RAM
+2KB RAM
USB Buffer
+8B Backup
RAM
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Functional Block Diagram, MSP430F5632, MSP430F5631, MSP430F5630
4Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
96
97
98
99
100
75
74
73
72
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70
69
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63
62
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60
59
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57
56
55
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46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6/DAC0
P6.7/CB7/A7/DAC1
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14/DAC0
P7.7/CB11/A15/DAC1
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F5638
MSP430F5637
MSP430F5636
PZ PACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN VBUS
VUSB PU.1/DM
PUR
PU.0/DP
VSSU V18
AVSS3
P1.3/TA0.2
P1.4/TA0.3
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4
P5.5
P1.0/TA0CLK/ACLK
P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P1.6/TA0.1
P1.7/TA0.2
P1.1/TA0.0
P1.2/TA0.1
P1.5/TA0.4
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2
P4.0/TB0.0
P4.2/TB0.2
P4.1/TB0.1
P4.4/TB0.4
P4.3/TB0.3
P4.6/TB0.6
P4.5/TB0.5
P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT
P8.4/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK
P8.2/UCA1TXD/UCA1SIMO
P8.3/UCA1RXD/UCA1SOMI
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Pin Designation, MSP430F5638IPZ, MSP430F5637IPZ, MSP430F5636IPZ
NOTE: DNC = Do not connect
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

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3
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7
8
9
10
11
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16
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23
24
25
76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P7.4/CB8/A12
P7.5/CB9/A13
P7.6/CB10/A14
P7.7/CB11/A15
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F5635
MSP430F5634
MSP430F5633
PZ PACKAGE
(TOP VIEW)
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN VBUS
VUSB PU.1/DM
PUR
PU.0/DP
VSSU V18
AVSS3
P1.3/TA0.2
P1.4/TA0.3
AVSS2
P5.6/ADC12CLK/DMAE0
P5.4
P5.5
P1.0/TA0CLK/ACLK
P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P1.6/TA0.1
P1.7/TA0.2
P1.1/TA0.0
P1.2/TA0.1
P1.5/TA0.4
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2
P4.0/TB0.0
P4.2/TB0.2
P4.1/TB0.1
P4.4/TB0.4
P4.3/TB0.3
P4.6/TB0.6
P4.5/TB0.5
P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT
P8.4/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK
P8.2/UCA1TXD/UCA1SIMO
P8.3/UCA1RXD/UCA1SOMI
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Pin Designation, MSP430F5635IPZ, MSP430F5634IPZ, MSP430F5633IPZ
NOTE: DNC = Do not connect
6Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

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7
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76 77 78 79 80
81
82
83 84 85 86 87 88 89 90 91 92 93 94 95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
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45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P6.4/CB4
P6.5/CB5
P6.6/CB6
P6.7/CB7
P7.4/CB8
P7.5/CB9
P7.6/CB10
P7.7/CB11
P5.0/VREF+/VeREF+
P5.1/VREF−/VeREF−
AVCC1
AVSS1
XIN
XOUT
DVCC1
DVSS1
VCORE
P5.2
DVSS
DNC
P5.3
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P8.7
P8.6/UCB1SOMI/UCB1SCL
P8.5/UCB1SIMO/UCB1SDA
DVCC2
DVSS2
P2.0/P2MAP0
MSP430F5632
MSP430F5631
MSP430F5630
PZ PACKAGE
(TOP VIEW)
P6.3/CB3
P6.2/CB2
P6.1/CB1 P6.0/CB0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK P7.3/XT2OUT
P7.2/XT2IN VBUS
VUSB PU.1/DM
PUR
PU.0/DP
VSSU V18
AVSS3
P1.3/TA0.2
P1.4/TA0.3
AVSS2
P5.6/DMAE0
P5.4
P5.5
P1.0/TA0CLK/ACLK
P3.0/TA1CLK/CBOUT
P3.1/TA1.0
P3.2/TA1.1
P1.6/TA0.1
P1.7/TA0.2
P1.1/TA0.0
P1.2/TA0.1
P1.5/TA0.4
P3.3/TA1.2
P3.4/TA2CLK/SMCLK
P3.5/TA2.0
P3.6/TA2.1
P3.7/TA2.2
P4.0/TB0.0
P4.2/TB0.2
P4.1/TB0.1
P4.4/TB0.4
P4.3/TB0.3
P4.6/TB0.6
P4.5/TB0.5
P8.0/TB0CLK
P4.7/TB0OUTH/SVMOUT
P8.4/UCB1CLK/UCA1STE
VBAK
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6
P2.7/P2MAP7
DVCC3
DVSS3 VBAT
P5.7/RTCCLK
P8.1/UCB1STE/UCA1CLK
P8.2/UCA1TXD/UCA1SIMO
P8.3/UCA1RXD/UCA1SOMI
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Pin Designation, MSP430F5632IPZ, MSP430F5631IPZ, MSP430F5630IPZ
NOTE: DNC = Do not connect
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
C1 C2 C3 C11 C12
D1 D2 D4 D5 D6 D7 D8 D9 D11 D12
E1 E2 E4 E5 E6 E7 E8 E9 E11 E12
F1 F2 F4 F5 F8 F9 F11 F12
G1 G2 G4 G5 G8 G9 G11 G12
J1 J2 J4 J5 J6 J7 J8 J9 J11 J12
H1 H2 H4 H5 H6 H7 H8 H9 H11 H12
K1 K2 K11 K12
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12
M4
ZQW PACKAGE
(TOP VIEW)
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Pin Designation, MSP430F5638IZQW, MSP430F5637IZQW, MSP430F5636IZQW,
MSP430F5635IZQW, MSP430F5634IZQW, MSP430F5633IZQW, MSP430F5632IZQW,
MSP430F5631IZQW, MSP430F5630IZQW
NOTE: For terminal assignments, see Table 2
8Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Table 2. Terminal Functions
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4
Analog input A4 – ADC(not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5
Analog input A5 – ADC(not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
Comparator_B input CB6
P6.6/CB6/A6/DAC0 3 B1 I/O Analog input A6 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, F5630
devices)
General-purpose digital I/O
Comparator_B input CB7
P6.7/CB7/A7/DAC1 4 C2 I/O Analog input A7 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, F5630
devices)
General-purpose digital I/O
P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8
Analog input A12 –ADC (not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9
Analog input A13 – ADC (not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
Comparator_B input CB10
P7.6/CB10/A14/DAC0 7 D2 I/O Analog input A14 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, F5630
devices)
General-purpose digital I/O
Comparator_B input CB11
P7.7/CB11/A15/DAC1 8 D1 I/O Analog input A15 – ADC (not available on F5632, F5631, F5630 devices)
DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, F5630
devices)
General-purpose digital I/O
P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O
P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
E1,
AVCC1 11 Analog power supply
E2
AVSS1 12 F2 Analog ground supply
XIN 13 F1 I Input terminal for crystal oscillator XT1
XOUT 14 G1 O Output terminal of crystal oscillator XT1
AVSS2 15 G2 Analog ground supply
(1) I = input, O = output, N/A = not available on this package offering
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC (not available on F5632, F5631, F5630 devices)
DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/P2MAP0 17 G4 I/O Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
P2.1/P2MAP1 18 H2 I/O Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
General-purpose digital I/O with port interrupt and mappable secondary function
P2.2/P2MAP2 19 J1 I/O Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
P2.3/P2MAP3 20 H4 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
P2.4/P2MAP4 21 J2 I/O Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function
P2.5/P2MAP5 22 K1 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/P2MAP6 23 K2 I/O Default mapping: no secondary function
General-purpose digital I/O with port interrupt and mappable secondary function
P2.7/P2MAP7 24 L2 I/O Default mapping: no secondary function
DVCC1 25 L1 Digital power supply
DVSS1 26 M1 Digital ground supply
VCORE(2) 27 M2 Regulated core power supply (internal use only, no external current loading)
P5.2 28 L3 I/O General-purpose digital I/O
DVSS 29 M3 Digital ground supply
DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open.
P5.3 31 L4 I/O General-purpose digital I/O
P5.4 32 M4 I/O General-purpose digital I/O
P5.5 33 J5 I/O General-purpose digital I/O
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK 34 L5 I/O Timer TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
P1.1/TA0.0 35 M5 I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
P1.2/TA0.1 36 J6 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
General-purpose digital I/O with port interrupt
P1.3/TA0.2 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
P1.4/TA0.3 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Table 2. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O with port interrupt
P1.5/TA0.4 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
P1.6/TA0.1 40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt
P1.7/TA0.2 41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt
P3.0/TA1CLK/CBOUT 42 L7 I/O Timer TA1 clock input
Comparator_B output
General-purpose digital I/O with port interrupt
P3.1/TA1.0 43 H7 I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O with port interrupt
P3.2/TA1.1 44 M8 I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt
P3.3/TA1.2 45 L8 I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt
P3.4/TA2CLK/SMCLK 46 J8 I/O Timer TA2 clock input
SMCLK output
General-purpose digital I/O with port interrupt
P3.5/TA2.0 47 M9 I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O with port interrupt
P3.6/TA2.1 48 L9 I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt
P3.7/TA2.2 49 M10 I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt
P4.0/TB0.0 50 J9 I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O with port interrupt
P4.1/TB0.1 51 M11 I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O with port interrupt
P4.2/TB0.2 52 L10 I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O with port interrupt
P4.3/TB0.3 53 M12 I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
General-purpose digital I/O with port interrupt
P4.4/TB0.4 54 L12 I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O with port interrupt
P4.5/TB0.5 55 L11 I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
General-purpose digital I/O with port interrupt
P4.6/TB0.6 56 K11 I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
General-purpose digital I/O with port interrupt
P4.7/TB0OUTH/SVMOUT 57 K12 I/O Timer TB0: Switch all PWM outputs high impedance
SVM output
General-purpose digital I/O
P8.0/TB0CLK 58 J11 I/O Timer TB0 clock input
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Table 2. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
General-purpose digital I/O
P8.1/UCB1STE/UCA1CLK 59 J12 I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output
General-purpose digital I/O
P8.2/UCA1TXD/UCA1SIMO 60 H11 I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out
General-purpose digital I/O
P8.3/UCA1RXD/UCA1SOMI 61 H12 I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in
General-purpose digital I/O
P8.4/UCB1CLK/UCA1STE 62 G11 I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable
DVSS2 63 G12 Digital ground supply
DVCC2 64 F12 Digital power supply
General-purpose digital I/O
P8.5/UCB1SIMO/UCB1SDA 65 F11 I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data
General-purpose digital I/O
P8.6/UCB1SOMI/UCB1SCL 66 G9 I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock
P8.7 67 E12 I/O General-purpose digital I/O
P9.0 68 E11 I/O General-purpose digital I/O
P9.1 69 F9 I/O General-purpose digital I/O
P9.2 70 D12 I/O General-purpose digital I/O
P9.3 71 D11 I/O General-purpose digital I/O
P9.4 72 E9 I/O General-purpose digital I/O
P9.5 73 C12 I/O General-purpose digital I/O
P9.6 74 C11 I/O General-purpose digital I/O
P9.7 75 D9 I/O General-purpose digital I/O
B11
VSSU 76 and USB PHY ground supply
B12
General-purpose digital I/O - controlled by USB control register
PU.0/DP 77 A12 I/O USB data terminal DP
USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to
PUR 78 B10 I/O invoke the default USB BSL. Recommended 1-MΩresistor to ground. See USB
BSL for more information.
General-purpose digital I/O - controlled by USB control register
PU.1/DM 79 A11 I/O USB data terminal DM
VBUS 80 A10 USB LDO input (connect to USB power source)
VUSB 81 A9 USB LDO output
V18 82 B9 USB regulated power (internal use only, no external current loading)
AVSS3 83 A8 Analog ground supply
General-purpose digital I/O
P7.2/XT2IN 84 B8 I/O Input terminal for crystal oscillator XT2
General-purpose digital I/O
P7.3/XT2OUT 85 B7 I/O Output terminal of crystal oscillator XT2
Capacitor for backup subsystem. Do not load this pin externally. For capacitor
VBAK 86 A7 values, see CBAK in Recommended Operating Conditions.
12 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Table 2. Terminal Functions (continued)
TERMINAL
NO. I/O(1) DESCRIPTION
NAME PZ ZQW
Backup or secondary supply voltage. If backup voltage is not supplied, connect to
VBAT 87 D8 DVCC externally.
General-purpose digital I/O
P5.7/RTCCLK 88 D7 I/O RTCCLK output
DVCC3 89 A6 Digital power supply
DVSS3 90 A5 Digital ground supply
Test mode pin; selects digital I/O on JTAG pins
TEST/SBWTCK 91 B6 I Spy-bi-wire input clock
General-purpose digital I/O
PJ.0/TDO 92 B5 I/O Test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK 93 A4 I/O Test data input or test clock input
General-purpose digital I/O
PJ.2/TMS 94 E7 I/O Test mode select
General-purpose digital I/O
PJ.3/TCK 95 D6 I/O Test clock
Reset input (active low)(3)
RST/NMI/SBWTDIO 96 A3 I/O Non-maskable interrupt input
Spy-bi-wire data input/output
General-purpose digital I/O
P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0
Analog input A0 – ADC (not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1
Analog input A1 – ADC (not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2
Analog input A2 – ADC (not available on F5632, F5631, F5630 devices)
General-purpose digital I/O
P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3
Analog input A3 – ADC (not available on F5632, F5631, F5630 devices)
E5,
E6,
E8,
F4,
F5,
Reserved N/A F8, Reserved. It is recommended to connect to ground (DVSS, AVSS).
G5,
G8,
H5,
H8,
H9
(3) When this pin is configured as reset, the intermal pullup resistor is enabled by default.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
Break- Range LPMx.5
MSP430 4-Wire 2-Wire Clock State Trace
points Break- Debugging
Architecture JTAG JTAG Control Sequencer Buffer
(N) points Support
MSP430Xv2 Yes Yes 8 Yes Yes Yes Yes No
Recommended Hardware Options
Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also feature
header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG
programmer and debugger included. The following table shows the compatible target boards and the supported
packages.
Package Target Board and Programmer Bundle Target Board Only
100-pin LQFP (PZ) MSP-FET430U100USB MSP-TS430PZ100USB
Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional
hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools
for details.
Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full
list of available tools at www.ti.com/msp430tools.
Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number PC Port Features Provider
MSP-GANG Serial and USB Program up to eight devices at a time. Works with PC or standalone. Texas Instruments
Recommended Software Options
Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also available.
This device is supported by Code Composer Studio™ IDE (CCS).
MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices
delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design
resources, MSP430Ware also includes a high-level API called MSP430 Driver Library. This library makes it easy
to program MSP430 hardware. MSP430Ware is available as a component of CCS or as a standalone package.
14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633
MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
TI-RTOS
TI-RTOS is a complete real-time operating system for the MSP430 microcontrollers. It combines a real-time
multitasking kernel SYS/BIOS with additional middleware components. TI-RTOS is available free of charge and
provided with full source code.
MSP430 USB Developer's Package
MSP430 USB Developer's Package is an easy-to-use USB stack implementation for the MSP430
microcontrollers.
Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a
FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to
download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of two
prefixes: MSP or XMS (for example, MSP430F5259). Texas Instruments recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product
development from engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified
production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
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MSP430F5632 MSP430F5631 MSP430F5630

Processor Family CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon
430 MCU Platform TI’s Low Power Microcontroller Platform
Device Type Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series 1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz w/ LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series
Feature Set Various Levels of Integration Within a Series
Optional: A = Revision N/A
Optional: Temperature Range S = 0°C to 50 C
C to 70 C
I = -40 C to 85 C
T = -40 C to 105 C
°
C = 0° °
° °
° °
Packaging www.ti.com/packaging
Optional: Tape and Reel T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features *-EP = Enhanced Product (-40°C to 105°C)
*-HT = Extreme Temperature Parts (-55°C to 150°C)
MSP 430 F5438 AIZQW TXX
Processor Family
Series Optional: Temperature Range
430 MCU Platform
PackagingDevice Type
Optional: A = Revision
Optional: Tape and Reel
Feature Set
Optional: Additional Features
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZP) and temperature range (for example, T). Figure 1 provides a legend for reading the complete
device name for any family member.
Part Number Decoder
Figure 1. Device Nomenclature
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MSP430F5632 MSP430F5631 MSP430F5630

Program Counter PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
General-Purpose Register R4
General-Purpose Register R5
General-Purpose Register R6
General-Purpose Register R7
General-Purpose Register R8
General-Purpose Register R9
General-Purpose Register R10
General-Purpose Register R11
General-Purpose Register R12
General-Purpose Register R13
General-Purpose Register R15
General-Purpose Register R14
MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Short-Form Description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
Instruction Set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data. Table 3 shows examples of the three
types of instruction formats; Table 4 shows the
address modes.
Table 3. Instruction Word Formats
INSTRUCTION WORD FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 →R5
Single operands, destination only CALL R8 PC →(TOS), R8 →PC
Relative jump, un/conditional JNE Jump-on-equal bit = 0
Table 4. Address Mode Descriptions
ADDRESS MODE S(1) D(1) SYNTAX EXAMPLE OPERATION
Register + + MOV Rs,Rd MOV R10,R11 R10 →R11
Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) →M(6+R6)
Symbolic (PC relative) + + MOV EDE,TONI M(EDE) →M(TONI)
Absolute + + MOV &MEM, &TCDAT M(MEM) →M(TCDAT)
Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) →M(Tab+R6)
M(R10) →R11
Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 →R10
Immediate + MOV #X,TONI MOV #45,TONI #45 →M(TONI)
(1) S = source, D = destination
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MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Operating Modes
The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4
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MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
www.ti.com SLAS650D –JUNE 2010–REVISED AUGUST 2013
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up, External Reset WDTIFG, KEYV (SYSRSTIV)(1)(2) Reset 0FFFEh 63, highest
Watchdog Timeout, Key Violation
Flash Memory Key Violation
System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG (Non)maskable 0FFFAh 61
Oscillator Fault (SYSUNIV)(1)(2)
Flash Memory Access Violation
Comp_B Comparator B interrupt flags (CBIV)(1)(3) Maskable 0FFF8h 60
Timer TB0 TB0CCR0 CCIFG0(3) Maskable 0FFF6h 59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
Timer TB0 Maskable 0FFF4h 58
TB0IFG (TBIV)(1) (3)
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3) Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(3) Maskable 0FFEEh 55
ADC12_A(4) ADC12IFG0 to ADC12IFG15 (ADC12IV)(1)(3) Maskable 0FFECh 54
Timer TA0 TA0CCR0 CCIFG0(3) Maskable 0FFEAh 53
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
Timer TA0 Maskable 0FFE8h 52
TA0IFG (TA0IV)(1)(3)
USB_UBM USB interrupts (USBIV)(1)(3) Maskable 0FFE6h 51
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA Maskable 0FFE4h 50
DMA4IFG, DMA5IFG (DMAIV)(1)(3)
Timer TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
Timer TA1 Maskable 0FFE0h 48
TA1IFG (TA1IV)(1)(3)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3) Maskable 0FFDAh 45
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD8h 44
Reserved Reserved Maskable 0FFD6h 43
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B Maskable 0FFD4h 42
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)(3)
DAC12_A(5) DAC12_0IFG, DAC12_1IFG(1)(3) Maskable 0FFD2h 41
Timer TA2 TA2CCR0 CCIFG0(3) Maskable 0FFD0h 40
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
Timer TA2 Maskable 0FFCEh 39
TA2IFG (TA2IV)(1)(3)
I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV)(1)(3) Maskable 0FFCCh 38
I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)(1)(3) Maskable 0FFCAh 37
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with peripheral module ADC12_A, otherwise reserved.
(5) Only on devices with peripheral module DAC12_A, otherwise reserved.
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MSP430F5638, MSP430F5637, MSP430F5636
MSP430F5635, MSP430F5634, MSP430F5633
MSP430F5632, MSP430F5631, MSP430F5630
SLAS650D –JUNE 2010–REVISED AUGUST 2013 www.ti.com
Table 5. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations (continued)
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
0FFC8h 36
Reserved Reserved(6) ⋮ ⋮
0FF80h 0, lowest
(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatability with other devices, it is recommended to reserve these locations.
Memory Organization
Table 6. Memory Organization(1)(2)
MSP430F5636 MSP430F5637 MSP430F5638
MSP430F5633 MSP430F5634 MSP430F5635
MSP430F5630 MSP430F5631 MSP430F5632
Memory (flash) Total Size 128KB 192KB 256KB
Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
Bank 3 N/A N/A 64 KB
047FFF-038000h
Bank 2 N/A 64 KB 64 KB
037FFF-028000h 037FFF-028000h
Main: code memory Bank 1 64 KB 64 KB 64 KB
027FFF-018000h 027FFF-018000h 027FFF-018000h
Bank 0 64 KB 64 KB 64 KB
017FFF-008000h 017FFF-008000h 017FFF-008000h
Sector 3 4 KB 4 KB 4 KB
0063FFh–005400h 0063FFh–005400h 0063FFh–005400h
Sector 2 4 KB 4 KB 4 KB
0053FFh–004400h 0053FFh–004400h 0053FFh–004400h
RAM Sector 1 4 KB 4 KB 4 KB
0043FFh–003400h 0043FFh–003400h 0043FFh–003400h
Sector 0 4 KB 4 KB 4 KB
0033FFh–002400h 0033FFh–002400h 0033FFh–002400h
Size 2KB 2KB 2KB
USB RAM(3) RAM 0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h
Info A 128 B 128 B 128 B
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
Info B 128 B 128 B 128 B
00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
Information memory
(flash) Info C 128 B 128 B 128 B
0018FFh–001880h 0018FFh–001880h 0018FFh–001880h
Info D 128 B 128 B 128 B
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
BSL 3 512 B 512 B 512 B
0017FFh–001600h 0017FFh–001600h 0017FFh–001600h
BSL 2 512 B 512 B 512 B
0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
Bootstrap loader (BSL)
memory (flash) BSL 1 512 B 512 B 512 B
0013FFh–001200h 0013FFh–001200h 0013FFh–001200h
BSL 0 512 B 512 B 512 B
0011FFh–001000h 0011FFh–001000h 0011FFh–001000h
Size 4KB 4KB 4KB
Peripherals 000FFFh–000000h 000FFFh–000000h 000FFFh–000000h
(1) N/A = Not available.
(2) Backup RAM is accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
(3) USB RAM can be used as general purpose RAM when not used for USB operation.
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