Texas Instruments SimpleLink MSP432P4 Series Product manual

MSP432P4xx SimpleLink™ Microcontrollers
Technical Reference Manual
Literature Number: SLAU356I
March 2015–Revised June 2019

2SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 48
1 Cortex-M4F Processor ........................................................................................................ 49
1.1 Introduction.................................................................................................................. 50
1.1.1 Block Diagram ..................................................................................................... 52
1.2 Overview..................................................................................................................... 53
1.2.1 Bus Interface....................................................................................................... 53
1.2.2 Integrated Configurable Debug.................................................................................. 54
1.2.3 Cortex-M4F System Component Details....................................................................... 54
1.3 Programming Model ....................................................................................................... 55
1.3.1 Processor Mode and Privilege Levels for Software Execution.............................................. 55
1.3.2 Stacks............................................................................................................... 55
1.3.3 Register Map....................................................................................................... 56
1.3.4 Register Descriptions............................................................................................. 56
1.3.5 Exceptions and Interrupts........................................................................................ 59
1.3.6 Data Types......................................................................................................... 59
1.4 Memory Model.............................................................................................................. 59
1.4.1 Memory Regions, Types, and Attributes ....................................................................... 60
1.4.2 Memory System Ordering of Memory Accesses.............................................................. 61
1.4.3 Behavior of Memory Accesses .................................................................................. 61
1.4.4 Software Ordering of Memory Accesses....................................................................... 61
1.4.5 Bit-Banding......................................................................................................... 62
1.4.6 Data Storage....................................................................................................... 64
1.5 Exception Model............................................................................................................ 65
1.5.1 Exception States .................................................................................................. 66
1.5.2 Exception Types................................................................................................... 66
1.5.3 Exception Handlers ............................................................................................... 67
1.5.4 Vector Table ....................................................................................................... 68
1.5.5 Exception Priorities................................................................................................ 69
1.5.6 Interrupt Priority Grouping........................................................................................ 69
1.5.7 Level and Pulse Interrupts ....................................................................................... 69
1.5.8 Exception Entry and Return...................................................................................... 70
1.6 Fault Handling .............................................................................................................. 72
1.6.1 Fault Types......................................................................................................... 73
1.6.2 Fault Escalation and Hard Faults ............................................................................... 73
1.6.3 Fault Status Registers and Fault Address Registers......................................................... 74
1.6.4 Lockup.............................................................................................................. 74
1.7 Power Management........................................................................................................ 74
1.8 Instruction Set Summary .................................................................................................. 75
2 Cortex-M4F Peripherals....................................................................................................... 80
2.1 Cortex-M4F Peripherals Introduction .................................................................................... 81
2.2 Functional Peripherals Description....................................................................................... 81
2.2.1 System Timer (SysTick).......................................................................................... 81
2.2.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 82
2.2.3 System Control Block (SCB)..................................................................................... 83
2.2.4 Memory Protection Unit (MPU).................................................................................. 84

www.ti.com
3
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
2.2.5 Floating-Point Unit (FPU)......................................................................................... 88
2.3 Debug Peripherals Description........................................................................................... 91
2.3.1 FPB ................................................................................................................. 91
2.3.2 DWT................................................................................................................. 91
2.3.3 ITM .................................................................................................................. 92
2.3.4 TPIU................................................................................................................. 92
2.4 Functional Peripherals Registers......................................................................................... 93
2.4.1 FPU Registers ..................................................................................................... 93
2.4.2 MPU Registers..................................................................................................... 99
2.4.3 NVIC Registers................................................................................................... 115
2.4.4 SYSTICK Registers.............................................................................................. 130
2.4.5 SCB Registers.................................................................................................... 135
2.4.6 SCnSCB Registers .............................................................................................. 170
2.4.7 COREDEBUG Registers........................................................................................ 173
2.5 Debug Peripherals Registers............................................................................................ 180
2.5.1 FPB Registers.................................................................................................... 180
2.5.2 DWT Registers................................................................................................... 191
2.5.3 ITM Registers .................................................................................................... 217
3 Reset Controller (RSTCTL)................................................................................................. 254
3.1 Introduction ................................................................................................................ 255
3.2 Reset Classification....................................................................................................... 255
3.2.1 Class 0 : Power On/Off Reset (POR) Class.................................................................. 255
3.2.2 Class 1 : Reboot Reset ......................................................................................... 256
3.2.3 Class 2 : Hard Reset ............................................................................................ 256
3.2.4 Class 3 : Soft Reset ............................................................................................. 257
3.3 RSTCTL Registers........................................................................................................ 258
3.3.1 RSTCTL_RESET_REQ Register (offset = 00h) ............................................................ 259
3.3.2 RSTCTL_HARDRESET_STAT Register (offset = 04h) .................................................... 260
3.3.3 RSTCTL_HARDRESET_CLR Register (offset = 08h)...................................................... 261
3.3.4 RSTCTL_HARDRESET_SET Register (offset = 0Ch)...................................................... 262
3.3.5 RSTCTL_SOFTRESET_STAT Register (offset = 10h)..................................................... 263
3.3.6 RSTCTL_SOFTRESET_CLR Register (offset = 14h) ...................................................... 264
3.3.7 RSTCTL_SOFTRESET_SET Register (offset = 18h)....................................................... 265
3.3.8 RSTCTL_PSSRESET_STAT Register (offset = 100h) ..................................................... 266
3.3.9 RSTCTL_PSSRESET_CLR Register (offset = 104h)....................................................... 266
3.3.10 RSTCTL_PCMRESET_STAT Register (offset = 108h).................................................... 267
3.3.11 RSTCTL_PCMRESET_CLR Register (offset = 10Ch)..................................................... 267
3.3.12 RSTCTL_PINRESET_STAT Register (offset = 110h)..................................................... 268
3.3.13 RSTCTL_PINRESET_CLR Register (offset = 114h)....................................................... 268
3.3.14 RSTCTL_REBOOTRESET_STAT Register (offset = 118h) .............................................. 269
3.3.15 RSTCTL_REBOOTRESET_CLR Register (offset = 11Ch) ............................................... 269
3.3.16 RSTCTL_CSRESET_STAT Register (offset = 120h)...................................................... 270
3.3.17 RSTCTL_CSRESET_CLR Register (offset = 124h) ....................................................... 270
4 System Controller (SYSCTL) .............................................................................................. 271
4.1 SYSCTL Introduction..................................................................................................... 272
4.2 Device Memory Configuration and Status............................................................................. 272
4.2.1 Flash............................................................................................................... 272
4.2.2 SRAM ............................................................................................................. 272
4.3 NMI Configuration ........................................................................................................ 273
4.4 Watchdog Timer Reset Configuration.................................................................................. 273
4.5 Peripheral Halt Control................................................................................................... 273
4.6 Glitch Filtering on Digital I/Os........................................................................................... 273
4.7 Reset Status and Override Control..................................................................................... 274

www.ti.com
4SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
4.8 Device Security ........................................................................................................... 274
4.8.1 Device Security Introduction.................................................................................... 274
4.8.2 Device Security Components .................................................................................. 274
4.8.3 JTAG and SWD Lock Based Security ........................................................................ 274
4.8.4 IP Protection Through Secure Memory Zones............................................................... 274
4.8.5 In-Field Updates ................................................................................................. 276
4.8.6 Boot-Overrides ................................................................................................... 278
4.8.7 Device Security and Boot Overrides User Considerations................................................. 288
4.9 Device Descriptor Table ................................................................................................. 289
4.9.1 Tag Length Value (TLV) Descriptors.......................................................................... 290
4.9.2 TLV Checksum................................................................................................... 290
4.9.3 Calibration Values ............................................................................................... 291
4.10 Arm Cortex-M4F ROM Table Based Part Number................................................................... 294
4.11 SYSCTL Registers........................................................................................................ 295
4.11.1 SYS_REBOOT_CTL Register (offset = 0000h) ............................................................ 296
4.11.2 SYS_NMI_CTLSTAT Register (offset = 0004h) ........................................................... 297
4.11.3 SYS_WDTRESET_CTL Register (offset = 0008h) ........................................................ 298
4.11.4 SYS_PERIHALT_CTL Register (offset = 000Ch) ......................................................... 299
4.11.5 SYS_SRAM_SIZE Register (offset = 0010h) .............................................................. 300
4.11.6 SYS_SRAM_BANKEN Register (offset = 0014h) ......................................................... 301
4.11.7 SYS_SRAM_BANKRET Register (offset = 0018h) ........................................................ 302
4.11.8 SYS_FLASH_SIZE Register (offset = 0020h) .............................................................. 303
4.11.9 SYS_DIO_GLTFLT_CTL Register (offset = 0030h) ....................................................... 304
4.11.10 SYS_SECDATA_UNLOCK Register (offset = 0040h) ................................................... 305
4.11.11 SYS_MASTER_UNLOCK Register (offset = 1000h) .................................................... 306
4.11.12 SYS_BOOTOVER_REQ0 Register (offset = 1004h)..................................................... 307
4.11.13 SYS_BOOTOVER_REQ1 Register (offset = 1008h)..................................................... 308
4.11.14 SYS_BOOTOVER_ACK Register (offset = 100Ch) ..................................................... 309
4.11.15 SYS_RESET_REQ Register (offset = 1010h) ............................................................ 310
4.11.16 SYS_RESET_STATOVER Register (offset = 1014h) ................................................... 311
4.11.17 SYS_SYSTEM_STAT Register (offset = 1020h) ......................................................... 312
5 System Controller A (SYSCTL_A) ....................................................................................... 313
5.1 SYSCTL_A Introduction.................................................................................................. 314
5.2 Device Memory Configuration and Status............................................................................. 314
5.2.1 Flash............................................................................................................... 314
5.2.2 SRAM ............................................................................................................. 314
5.3 NMI Configuration ........................................................................................................ 315
5.4 Watchdog Timer Reset Configuration.................................................................................. 315
5.5 Peripheral Halt Control................................................................................................... 316
5.6 Glitch Filtering on Digital I/Os........................................................................................... 316
5.7 Reset Status and Override Control..................................................................................... 316
5.8 Device Security ........................................................................................................... 316
5.8.1 Device Security Introduction.................................................................................... 316
5.8.2 Device Security Components .................................................................................. 316
5.8.3 JTAG and SWD Lock Based Security ........................................................................ 316
5.8.4 IP Protection Through Secure Memory Zones............................................................... 317
5.8.5 In-Field Updates ................................................................................................. 319
5.8.6 Boot Overrides ................................................................................................... 321
5.8.7 Device Security and Boot Overrides User Considerations................................................. 331
5.9 Device Descriptor Table ................................................................................................. 332
5.9.1 TLV Descriptors.................................................................................................. 332
5.9.2 TLV Checksum................................................................................................... 333
5.9.3 Calibration Values ............................................................................................... 334

www.ti.com
5
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
5.10 Arm Cortex-M4F ROM Table Based Part Number................................................................... 337
5.11 SYSCTL_A Registers .................................................................................................... 338
5.11.1 SYS_REBOOT_CTL Register (offset = 0000h) ............................................................ 339
5.11.2 SYS_NMI_CTLSTAT Register (offset = 0004h) ........................................................... 340
5.11.3 SYS_WDTRESET_CTL Register (offset = 0008h) ........................................................ 341
5.11.4 SYS_PERIHALT_CTL Register (offset = 000Ch) ......................................................... 342
5.11.5 SYS_SRAM_SIZE Register (offset = 0010h) .............................................................. 343
5.11.6 SYS_SRAM_NUMBANKS Register (offset = 0014h) ..................................................... 344
5.11.7 SYS_SRAM_NUMBLOCKS Register (offset = 0018h) ................................................... 345
5.11.8 SYS_MAINFLASH_SIZE Register (offset = 0020h) ....................................................... 346
5.11.9 SYS_INFOFLASH_SIZE Register (offset = 0024h) ....................................................... 347
5.11.10 SYS_DIO_GLTFLT_CTL Register (offset = 0030h) ..................................................... 348
5.11.11 SYS_SECDATA_UNLOCK Register (offset = 0040h) ................................................... 349
5.11.12 SYS_SRAM_BANKEN_CTL0 Register (offset = 0050h) ................................................ 350
5.11.13 SYS_SRAM_BANKEN_CTL1 Register (offset = 0054h) ................................................ 353
5.11.14 SYS_SRAM_BANKEN_CTL2 Register (offset = 0058h)................................................. 356
5.11.15 SYS_SRAM_BANKEN_CTL3 Register (offset = 005Ch) ................................................ 359
5.11.16 SYS_SRAM_BLKRET_CTL0 Register (offset = 0070h) ................................................ 362
5.11.17 SYS_SRAM_BLKRET_CTL1 Register (offset = 0074h) ................................................ 364
5.11.18 SYS_SRAM_BLKRET_CTL2 Register (offset = 0078h) ................................................ 366
5.11.19 SYS_SRAM_BLKRET_CTL3 Register (offset = 007Ch) ................................................ 368
5.11.20 SYS_SRAM_STAT Register (offset = 0090h) ............................................................ 370
5.11.21 SYS_MASTER_UNLOCK Register (offset = 1000h) .................................................... 371
5.11.22 SYS_BOOTOVER_REQ0 Register (offset = 1004h)..................................................... 372
5.11.23 SYS_BOOTOVER_REQ1 Register (offset = 1008h)..................................................... 373
5.11.24 SYS_BOOTOVER_ACK Register (offset = 100Ch) ..................................................... 374
5.11.25 SYS_RESET_REQ Register (offset = 1010h) ............................................................ 375
5.11.26 SYS_RESET_STATOVER Register (offset = 1014h) ................................................... 376
5.11.27 SYS_SYSTEM_STAT Register (offset = 1020h) ......................................................... 377
6 Clock System (CS)............................................................................................................ 378
6.1 Clock System Introduction............................................................................................... 379
6.2 Clock System Operation................................................................................................. 381
6.2.1 CS Module Features for Low-Power Applications........................................................... 381
6.2.2 LFXT Oscillator .................................................................................................. 381
6.2.3 HFXT Oscillator ................................................................................................. 382
6.2.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 383
6.2.5 Internal Low-Power Low-Frequency Oscillator (REFO) .................................................... 384
6.2.6 Module Oscillator (MODOSC).................................................................................. 385
6.2.7 System Oscillator (SYSOSC) .................................................................................. 385
6.2.8 Digitally Controlled Oscillator (DCO) .......................................................................... 385
6.2.9 Module Clock Request System ................................................................................ 387
6.2.10 Clock System Fail-Safe Operation ........................................................................... 389
6.2.11 Start-up Counters............................................................................................... 391
6.2.12 Synchronization of Clock Signals............................................................................. 391
6.2.13 Clock Status..................................................................................................... 392
6.3 CS Registers .............................................................................................................. 393
6.3.1 CSKEY Register (offset = 00h) [reset = 0000_A596h]...................................................... 394
6.3.2 CSCTL0 Register (offset = 04h) [reset = 0001_0000h]..................................................... 395
6.3.3 CSCTL1 Register (offset = 08h) [reset = 0000_0033h]..................................................... 396
6.3.4 CSCTL2 Register (offset = 0Ch) [reset = 0001_0003h] .................................................... 398
6.3.5 CSCTL3 Register (offset = 10h) [reset = 0000_00BBh].................................................... 400
6.3.6 CSCLKEN Register (offset = 30h) [reset = 0000_000Fh] .................................................. 401
6.3.7 CSSTAT Register (offset = 34h) [reset = 0000_0003h] .................................................... 402

www.ti.com
6SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
6.3.8 CSIE Register (offset = 40h) [reset = 0000_0000h]......................................................... 404
6.3.9 CSIFG Register (offset = 48h) [reset = 0000_0001h]....................................................... 405
6.3.10 CSCLRIFG Register (offset = 50h) [reset = 0000_0000h] ................................................ 406
6.3.11 CSSETIFG Register (offset = 58h) [reset = 0000_0000h] ................................................ 407
6.3.12 CSDCOERCAL0 Register (offset = 60h) [reset = 0100_0000h] ......................................... 408
6.3.13 CSDCOERCAL1 Register (offset = 64h) [reset = 0000_0100h] ......................................... 409
7 Power Supply System (PSS) .............................................................................................. 410
7.1 Power Supply System (PSS) Introduction............................................................................. 411
7.2 PSS Operation ............................................................................................................ 412
7.2.1 Supply Voltage Supervisor and Monitor ...................................................................... 412
7.2.2 Supply Voltage Supervisor During Power up ................................................................ 413
7.2.3 VCCDET .......................................................................................................... 413
7.2.4 PSS Interrupts.................................................................................................... 414
7.3 PSS Registers............................................................................................................. 415
7.3.1 PSSKEY Register (offset = 00h) [reset = 0000A596h] ..................................................... 416
7.3.2 PSSCTL0 Register (offset = 04h) [reset = 00002000h]..................................................... 417
7.3.3 PSSIE Register (offset = 34h) [reset = 0000h]............................................................... 419
7.3.4 PSSIFG Register (offset = 38h) [reset = 0000h]............................................................. 420
7.3.5 PSSCLRIFG Register (offset = 3Ch) [reset = 0000h]....................................................... 421
8 Power Control Manager (PCM) ........................................................................................... 422
8.1 PCM Introduction ......................................................................................................... 423
8.2 PCM Overview ............................................................................................................ 423
8.3 Core Voltage Regulators................................................................................................. 424
8.3.1 DC/DC Regulator Care Abouts ................................................................................ 424
8.4 Power Modes.............................................................................................................. 424
8.4.1 Active Modes (AM) .............................................................................................. 425
8.4.2 LPM0 .............................................................................................................. 425
8.4.3 LPM3 and LPM4................................................................................................. 426
8.4.4 LPM3.5 and LPM4.5............................................................................................. 426
8.4.5 Summary of Power Modes ..................................................................................... 427
8.5 Power Mode Transitions................................................................................................. 430
8.5.1 Active Mode Transitions ........................................................................................ 431
8.5.2 Transitions To and From LPM0................................................................................ 432
8.5.3 Transitions To and From LPM3 and LPM4................................................................... 433
8.5.4 Transitions To and From LPM3.5 and LPM4.5 .............................................................. 433
8.6 Changing Core Voltages................................................................................................. 434
8.6.1 Increasing VCORE for Higher MCLK Frequencies ............................................................. 434
8.6.2 Decreasing VCORE for Power Optimization .................................................................... 434
8.7 Arm Cortex Processor Sleep Modes................................................................................... 434
8.7.1 WFI, Wait for Interrupt........................................................................................... 435
8.7.2 WFE, Wait for Event............................................................................................. 435
8.7.3 Sleep on Exit ..................................................................................................... 435
8.7.4 SLEEPDEEP ..................................................................................................... 435
8.8 Power Mode Requests................................................................................................... 435
8.9 Power Mode Selection ................................................................................................... 436
8.10 Power Mode Transition Checks......................................................................................... 437
8.11 Power Mode Clock Checks.............................................................................................. 437
8.12 Clock Configuration Changes........................................................................................... 438
8.13 Changing Active Modes.................................................................................................. 438
8.13.1 DC/DC Error Checking......................................................................................... 439
8.14 Entering LPM0 Modes ................................................................................................... 440
8.15 Exiting LPM0 Modes ..................................................................................................... 440
8.16 Entering LPM3 or LPM4 Modes ........................................................................................ 440

www.ti.com
7
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
8.17 Exiting LPM3 or LPM4 Mode – Interrupt Based Wakeup ........................................................... 441
8.18 Exiting LPM3 or LPM4 Mode – Interrupt From Device Pins ........................................................ 441
8.19 Exiting LPM3 or LPM4 Mode – DMA Trigger Based Wakeup (Not Applicable for MSP432P401R and
MSP432P401M Devices)................................................................................................ 442
8.20 Entering LPM3.5 and LPM4.5 Modes.................................................................................. 442
8.21 Exiting LPM3.5 and LPM4.5 Modes.................................................................................... 443
8.22 Supply Voltage Supervisor and Monitor and Power Modes......................................................... 443
8.23 Low-Power Reset......................................................................................................... 444
8.24 Power Requests During Debug......................................................................................... 444
8.24.1 Debug During Active Modes .................................................................................. 445
8.24.2 Debug During LPM0 Modes................................................................................... 445
8.24.3 Debug During LPM3, LPM4, and LPMx.5 Modes .......................................................... 445
8.25 Wake-up Sources From Low-Power Modes .......................................................................... 445
8.26 PCM Registers............................................................................................................ 448
8.26.1 PCMCTL0 Register (offset = 00h) [reset = A5960000h]................................................... 449
8.26.2 PCMCTL1 Register (offset = 04h) [reset = A5960000h]................................................... 451
8.26.3 PCMIE Register (offset = 08h) [reset = 00000000h]....................................................... 453
8.26.4 PCMIFG Register (offset = 0Ch) [reset = 00000000h] .................................................... 454
8.26.5 PCMCLRIFG Register (offset = 10h) [reset = 00000000h]................................................ 455
9 Flash Controller (FLCTL) ................................................................................................... 456
9.1 Introduction ................................................................................................................ 457
9.1.1 Flash Memory Organization.................................................................................... 457
9.1.2 Flash Controller Address Mapping ............................................................................ 457
9.1.3 Flash Controller Access Privileges ............................................................................ 457
9.2 Common Operations Using the Flash Controller ..................................................................... 458
9.2.1 Using MSP432 Driver Library for Flash Operations......................................................... 458
9.2.2 Flash Read ....................................................................................................... 458
9.2.3 Flash Program.................................................................................................... 459
9.2.4 Flash Erase....................................................................................................... 459
9.2.5 Flash Program and Erase Protection ......................................................................... 460
9.3 Advanced Operations using the Flash Controller..................................................................... 460
9.3.1 Advanced Flash Read .......................................................................................... 460
9.3.2 Advanced Flash Program....................................................................................... 461
9.3.3 Advanced Flash Erase.......................................................................................... 471
9.3.4 Flash Controller Interrupts ..................................................................................... 472
9.3.5 Application Benchmarking Features........................................................................... 473
9.3.6 Support for AM_LF_VCOREx and LPM0_LF_VCOREx Power Modes .................................. 473
9.3.7 Flash Functionality During Resets............................................................................. 473
9.4 FLCTL Registers.......................................................................................................... 475
9.4.1 FLCTL_POWER_STAT Register (offset = 0000h) ......................................................... 477
9.4.2 FLCTL_BANK0_RDCTL Register (offset = 0010h) ......................................................... 478
9.4.3 FLCTL_BANK1_RDCTL Register (offset = 0014h) ......................................................... 480
9.4.4 FLCTL_RDBRST_CTLSTAT Register (offset = 0020h) ................................................... 482
9.4.5 FLCTL_RDBRST_STARTADDR Register (offset = 0024h) ............................................... 483
9.4.6 FLCTL_RDBRST_LEN Register (offset = 0028h) .......................................................... 484
9.4.7 FLCTL_RDBRST_FAILADDR Register (offset = 003Ch) .................................................. 485
9.4.8 FLCTL_RDBRST_FAILCNT Register (offset = 0040h) .................................................... 486
9.4.9 FLCTL_PRG_CTLSTAT Register (offset = 0050h) ......................................................... 487
9.4.10 FLCTL_PRGBRST_CTLSTAT Register (offset = 0054h) ................................................ 488
9.4.11 FLCTL_PRGBRST_STARTADDR Register (offset = 0058h) ............................................ 490
9.4.12 FLCTL_PRGBRST_DATA0_0 Register (offset = 060h) .................................................. 491
9.4.13 FLCTL_PRGBRST_DATA0_1 Register (offset = 064h) .................................................. 491
9.4.14 FLCTL_PRGBRST_DATA0_2 Register (offset = 068h) .................................................. 492

www.ti.com
8SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
9.4.15 FLCTL_PRGBRST_DATA0_3 Register (offset = 06Ch) .................................................. 492
9.4.16 FLCTL_PRGBRST_DATA1_0 Register (offset = 070h) .................................................. 493
9.4.17 FLCTL_PRGBRST_DATA1_1 Register (offset = 074h) .................................................. 493
9.4.18 FLCTL_PRGBRST_DATA1_2 Register (offset = 078h) .................................................. 494
9.4.19 FLCTL_PRGBRST_DATA1_3 Register (offset = 07Ch) .................................................. 494
9.4.20 FLCTL_PRGBRST_DATA2_0 Register (offset = 080h) .................................................. 495
9.4.21 FLCTL_PRGBRST_DATA2_1 Register (offset = 084h) .................................................. 495
9.4.22 FLCTL_PRGBRST_DATA2_2 Register (offset = 088h) .................................................. 496
9.4.23 FLCTL_PRGBRST_DATA2_3 Register (offset = 08Ch) .................................................. 496
9.4.24 FLCTL_PRGBRST_DATA3_0 Register (offset = 090h) .................................................. 497
9.4.25 FLCTL_PRGBRST_DATA3_1 Register (offset = 094h) .................................................. 497
9.4.26 FLCTL_PRGBRST_DATA3_2 Register (offset = 098h) .................................................. 498
9.4.27 FLCTL_PRGBRST_DATA3_3 Register (offset = 09Ch) .................................................. 498
9.4.28 FLCTL_ERASE_CTLSTAT Register (offset = 00A0h) .................................................... 499
9.4.29 FLCTL_ERASE_SECTADDR Register (offset = 00A4h) ................................................. 500
9.4.30 FLCTL_BANK0_INFO_WEPROT Register (offset = 00B0h) ............................................ 501
9.4.31 FLCTL_BANK0_MAIN_WEPROT Register (offset = 00B4h) ............................................ 502
9.4.32 FLCTL_BANK1_INFO_WEPROT Register (offset = 00C0h) ............................................ 504
9.4.33 FLCTL_BANK1_MAIN_WEPROT Register (offset = 00C4h) ............................................ 505
9.4.34 FLCTL_BMRK_CTLSTAT Register (offset = 00D0h) ..................................................... 507
9.4.35 FLCTL_BMRK_IFETCH Register (offset = 00D4h) ....................................................... 508
9.4.36 FLCTL_BMRK_DREAD Register (offset = 00D8h) ........................................................ 509
9.4.37 FLCTL_BMRK_CMP Register (offset = 00DCh) ........................................................... 510
9.4.38 FLCTL_IFG Register (offset = 0F0h) ........................................................................ 511
9.4.39 FLCTL_IE Register (offset = 0F4h) .......................................................................... 512
9.4.40 FLCTL_CLRIFG Register (offset = 0F8h) .................................................................. 513
9.4.41 FLCTL_SETIFG Register (offset = 0FCh) .................................................................. 514
9.4.42 FLCTL_READ_TIMCTL Register (offset = 0100h) ........................................................ 515
9.4.43 FLCTL_READMARGIN_TIMCTL Register (offset = 0104h) ............................................. 516
9.4.44 FLCTL_PRGVER_TIMCTL Register (offset = 0108h) .................................................... 517
9.4.45 FLCTL_ERSVER_TIMCTL Register (offset = 010Ch) .................................................... 518
9.4.46 FLCTL_PROGRAM_TIMCTL Register (offset = 0114h) .................................................. 519
9.4.47 FLCTL_ERASE_TIMCTL Register (offset = 0118h) ...................................................... 520
9.4.48 FLCTL_MASSERASE_TIMCTL Register (offset = 011Ch) .............................................. 521
9.4.49 FLCTL_BURSTPRG_TIMCTL Register (offset = 0120h) ................................................. 522
10 Flash Controller A (FLCTL_A) ............................................................................................ 523
10.1 Introduction ................................................................................................................ 524
10.1.1 Flash Memory Organization................................................................................... 524
10.1.2 Flash Controller Address Mapping ........................................................................... 524
10.1.3 Flash Controller Access Privileges........................................................................... 524
10.2 Common Operations Using the Flash Controller ..................................................................... 525
10.2.1 Using MSP432 Driver Library for Flash Operations........................................................ 525
10.2.2 Flash Read ...................................................................................................... 525
10.2.3 Flash Program .................................................................................................. 526
10.2.4 Flash Erase...................................................................................................... 526
10.2.5 Flash Program and Erase Protection ........................................................................ 527
10.3 Advanced Operations using the Flash Controller..................................................................... 527
10.3.1 Advanced Flash Read ......................................................................................... 527
10.3.2 Advanced Flash Program...................................................................................... 528
10.3.3 Advanced Flash Erase......................................................................................... 538
10.3.4 Flash Controller Interrupts .................................................................................... 539
10.3.5 Application Benchmarking Features ......................................................................... 540
10.3.6 Support for AM_LF_VCOREx and LPM0_LF_VCOREx Power Modes ................................. 540

www.ti.com
9
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
10.3.7 Flash Functionality During Resets............................................................................ 540
10.4 FLCTL_A Registers....................................................................................................... 542
10.4.1 FLCTL_POWER_STAT Register (offset = 0000h) ........................................................ 544
10.4.2 FLCTL_BANK0_RDCTL Register (offset = 0010h) ........................................................ 545
10.4.3 FLCTL_BANK1_RDCTL Register (offset = 0014h) ........................................................ 547
10.4.4 FLCTL_RDBRST_CTLSTAT Register (offset = 0020h) .................................................. 549
10.4.5 FLCTL_RDBRST_STARTADDR Register (offset = 0024h) .............................................. 550
10.4.6 FLCTL_RDBRST_LEN Register (offset = 0028h) ......................................................... 551
10.4.7 FLCTL_RDBRST_FAILADDR Register (offset = 003Ch) ................................................. 552
10.4.8 FLCTL_RDBRST_FAILCNT Register (offset = 0040h) ................................................... 553
10.4.9 FLCTL_PRG_CTLSTAT Register (offset = 0050h) ........................................................ 554
10.4.10 FLCTL_PRGBRST_CTLSTAT Register (offset = 0054h) ............................................... 555
10.4.11 FLCTL_PRGBRST_STARTADDR Register (offset = 0058h) .......................................... 557
10.4.12 FLCTL_PRGBRST_DATA0_0 Register (offset = 060h) ................................................. 558
10.4.13 FLCTL_PRGBRST_DATA0_1 Register (offset = 064h) ................................................. 558
10.4.14 FLCTL_PRGBRST_DATA0_2 Register (offset = 068h) ................................................. 559
10.4.15 FLCTL_PRGBRST_DATA0_3 Register (offset = 06Ch) ................................................ 559
10.4.16 FLCTL_PRGBRST_DATA1_0 Register (offset = 070h) ................................................. 560
10.4.17 FLCTL_PRGBRST_DATA1_1 Register (offset = 074h) ................................................. 560
10.4.18 FLCTL_PRGBRST_DATA1_2 Register (offset = 078h) ................................................. 561
10.4.19 FLCTL_PRGBRST_DATA1_3 Register (offset = 07Ch) ................................................ 561
10.4.20 FLCTL_PRGBRST_DATA2_0 Register (offset = 080h) ................................................. 562
10.4.21 FLCTL_PRGBRST_DATA2_1 Register (offset = 084h) ................................................. 562
10.4.22 FLCTL_PRGBRST_DATA2_2 Register (offset = 088h) ................................................. 563
10.4.23 FLCTL_PRGBRST_DATA2_3 Register (offset = 08Ch) ................................................ 563
10.4.24 FLCTL_PRGBRST_DATA3_0 Register (offset = 090h) ................................................. 564
10.4.25 FLCTL_PRGBRST_DATA3_1 Register (offset = 094h) ................................................. 564
10.4.26 FLCTL_PRGBRST_DATA3_2 Register (offset = 098h) ................................................. 565
10.4.27 FLCTL_PRGBRST_DATA3_3 Register (offset = 09Ch) ................................................ 565
10.4.28 FLCTL_ERASE_CTLSTAT Register (offset = 00A0h) .................................................. 566
10.4.29 FLCTL_ERASE_SECTADDR Register (offset = 00A4h) ................................................ 567
10.4.30 FLCTL_BANK0_INFO_WEPROT Register (offset = 00B0h) ........................................... 568
10.4.31 FLCTL_BANK0_MAIN_WEPROT Register (offset = 00B4h) ........................................... 569
10.4.32 FLCTL_BANK1_INFO_WEPROT Register (offset = 00C0h) ........................................... 571
10.4.33 FLCTL_BANK1_MAIN_WEPROT Register (offset = 00C4h) ........................................... 572
10.4.34 FLCTL_BMRK_CTLSTAT Register (offset = 00D0h) .................................................... 574
10.4.35 FLCTL_BMRK_IFETCH Register (offset = 00D4h) ...................................................... 575
10.4.36 FLCTL_BMRK_DREAD Register (offset = 00D8h) ...................................................... 576
10.4.37 FLCTL_BMRK_CMP Register (offset = 00DCh) ......................................................... 577
10.4.38 FLCTL_IFG Register (offset = 0F0h) ...................................................................... 578
10.4.39 FLCTL_IE Register (offset = 0F4h) ........................................................................ 579
10.4.40 FLCTL_CLRIFG Register (offset = 0F8h) ................................................................. 580
10.4.41 FLCTL_SETIFG Register (offset = 0FCh) ................................................................. 581
10.4.42 FLCTL_READ_TIMCTL Register (offset = 0100h) ....................................................... 582
10.4.43 FLCTL_READMARGIN_TIMCTL Register (offset = 0104h) ............................................ 583
10.4.44 FLCTL_PRGVER_TIMCTL Register (offset = 0108h) ................................................... 584
10.4.45 FLCTL_ERSVER_TIMCTL Register (offset = 010Ch) ................................................... 585
10.4.46 FLCTL_PROGRAM_TIMCTL Register (offset = 0114h) ................................................ 586
10.4.47 FLCTL_ERASE_TIMCTL Register (offset = 0118h) ..................................................... 587
10.4.48 FLCTL_MASSERASE_TIMCTL Register (offset = 011Ch) ............................................. 588
10.4.49 FLCTL_BURSTPRG_TIMCTL Register (offset = 0120h) ............................................... 589
10.4.50 FLCTL_BANK0_MAIN_WEPROT0 Register (offset = 0200h) ......................................... 590
10.4.51 FLCTL_BANK0_MAIN_WEPROT1 Register (offset = 0204h) ......................................... 592

www.ti.com
10 SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
10.4.52 FLCTL_BANK0_MAIN_WEPROT2 Register (offset = 0208h) ......................................... 594
10.4.53 FLCTL_BANK0_MAIN_WEPROT3 Register (offset = 020Ch) ......................................... 596
10.4.54 FLCTL_BANK0_MAIN_WEPROT4 Register (offset = 0210h) ......................................... 598
10.4.55 FLCTL_BANK0_MAIN_WEPROT5 Register (offset = 0214h) ......................................... 600
10.4.56 FLCTL_BANK0_MAIN_WEPROT6 Register (offset = 0218h) ......................................... 602
10.4.57 FLCTL_BANK0_MAIN_WEPROT7 Register (offset = 021Ch) ......................................... 604
10.4.58 FLCTL_BANK1_MAIN_WEPROT0 Register (offset = 0240h) ......................................... 606
10.4.59 FLCTL_BANK1_MAIN_WEPROT1 Register (offset = 0244h) ......................................... 608
10.4.60 FLCTL_BANK1_MAIN_WEPROT2 Register (offset = 0248h) ......................................... 610
10.4.61 FLCTL_BANK1_MAIN_WEPROT3 Register (offset = 024Ch) ......................................... 612
10.4.62 FLCTL_BANK1_MAIN_WEPROT4 Register (offset = 0250h) ......................................... 614
10.4.63 FLCTL_BANK1_MAIN_WEPROT5 Register (offset = 0254h) ......................................... 616
10.4.64 FLCTL_BANK1_MAIN_WEPROT6 Register (offset = 0258h) ......................................... 618
10.4.65 FLCTL_BANK1_MAIN_WEPROT7 Register (offset = 025Ch) ......................................... 620
11 DMA................................................................................................................................ 622
11.1 DMA Introduction ......................................................................................................... 623
11.2 DMA Operation............................................................................................................ 624
11.2.1 APB Slave Interface............................................................................................ 624
11.2.2 AHB Master Interface .......................................................................................... 624
11.2.3 DMA Control Interface ......................................................................................... 626
11.2.4 Channel Control Data Structure .............................................................................. 640
11.2.5 Peripheral Triggers ............................................................................................. 647
11.2.6 Interrupts......................................................................................................... 647
11.3 DMA Registers............................................................................................................ 648
11.3.1 DMA_DEVICE_CFG Register (offset = 000h) ............................................................. 649
11.3.2 DMA_SW_CHTRIG Register (offset = 004h) .............................................................. 650
11.3.3 DMA_CHn_SRCCFG Register (offset = 010h + 4h*n, n = 0 through NUM_DMA_CHANNELS) ... 652
11.3.4 DMA_INT1_SRCCFG Register (offset = 100h) ............................................................ 653
11.3.5 DMA_INT2_SRCCFG Register (offset = 104h) ............................................................ 654
11.3.6 DMA_INT3_SRCCFG Register (offset = 108h) ............................................................ 655
11.3.7 DMA_INT0_SRCFLG Register (offset = 110h) ............................................................ 656
11.3.8 DMA_INT0_CLRFLG Register (offset = 114h) ............................................................. 657
11.3.9 DMA_STAT Register (offset = 1000h) [reset = 0h]......................................................... 659
11.3.10 DMA_CFG Register (offset = 1004h) [reset = 0h] ........................................................ 660
11.3.11 DMA_CTLBASE Register (offset = 1008h) [reset = 0h].................................................. 661
11.3.12 DMA_ALTBASE Register (offset = 100Ch) [reset = 0h] ................................................. 662
11.3.13 DMA_WAITSTAT Register (offset = 1010h) [reset = 0h] ................................................ 663
11.3.14 DMA_SWREQ Register (offset = 1014h) [reset = 0h].................................................... 664
11.3.15 DMA_USEBURSTSET Register (offset = 1018h) [reset = 0h].......................................... 665
11.3.16 DMA_USEBURSTCLR Register (offset = 101Ch) [reset = 0h] ......................................... 666
11.3.17 DMA_REQMASKSET Register (offset = 1020h) [reset = 0h] ........................................... 667
11.3.18 DMA_REQMASKCLR Register (offset = 1024h) [reset = 0h]........................................... 668
11.3.19 DMA_ENASET Register (offset = 1028h) [reset = 0h] ................................................... 669
11.3.20 DMA_ENACLR Register (offset = 102Ch) [reset = 0h]................................................... 670
11.3.21 DMA_ALTSET Register (offset = 1030h) [reset = 0h].................................................... 671
11.3.22 DMA_ALTCLR Register (offset = 1034h) [reset = 0h].................................................... 672
11.3.23 DMA_PRIOSET Register (offset = 1038h) [reset = 0h] .................................................. 673
11.3.24 DMA_PRIOCLR Register (offset = 103Ch) [reset = 0h].................................................. 674
11.3.25 DMA_ERRCLR Register (offset = 104Ch) [reset = 0h] .................................................. 675
12 Digital I/O......................................................................................................................... 676
12.1 Digital I/O Introduction ................................................................................................... 677
12.2 Digital I/O Operation...................................................................................................... 678
12.2.1 Input Registers (PxIN).......................................................................................... 678

www.ti.com
11
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
12.2.2 Output Registers (PxOUT) .................................................................................... 678
12.2.3 Direction Registers (PxDIR)................................................................................... 678
12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 678
12.2.5 Output Drive Strength Selection Registers (PxDS) ........................................................ 679
12.2.6 Function Select Registers (PxSEL0, PxSEL1).............................................................. 679
12.2.7 Port Interrupts................................................................................................... 679
12.3 I/O Configuration.......................................................................................................... 681
12.3.1 Configuration After Reset...................................................................................... 681
12.3.2 Configuration of Unused Port Pins ........................................................................... 681
12.3.3 Configuration for LPM3 and LPM4 Modes .................................................................. 681
12.3.4 Configuration for LPM3.5 and LPM4.5 Modes.............................................................. 681
12.4 Digital I/O Registers ...................................................................................................... 683
12.4.1 PxIV Register.................................................................................................... 695
12.4.2 PxIN Register ................................................................................................... 696
12.4.3 PxOUT Register ................................................................................................ 696
12.4.4 PxDIR Register ................................................................................................. 696
12.4.5 PxREN Register ................................................................................................ 697
12.4.6 PxDS Register .................................................................................................. 697
12.4.7 PxSEL0 Register ............................................................................................... 697
12.4.8 PxSEL1 Register ............................................................................................... 698
12.4.9 PxSELC Register .............................................................................................. 698
12.4.10 PxIES Register ................................................................................................ 698
12.4.11 PxIE Register .................................................................................................. 699
12.4.12 PxIFG Register ............................................................................................... 699
13 Port Mapping Controller (PMAP)......................................................................................... 700
13.1 Port Mapping Controller Introduction................................................................................... 701
13.2 Port Mapping Controller Operation..................................................................................... 701
13.2.1 Access ........................................................................................................... 701
13.2.2 Mapping.......................................................................................................... 701
13.3 PMAP Registers .......................................................................................................... 704
13.3.1 PMAPKEYID Register (offset = 00h) [reset = 96A5h] ..................................................... 706
13.3.2 PMAPCTL Register (offset = 02h) [reset = 0001h]......................................................... 706
13.3.3 P1MAP0 to P1MAP7 Register (offset = 08h to 0Fh) [reset = X] ......................................... 706
13.3.4 P2MAP0 to P2MAP7 Register (offset = 10h to 17h) [reset = X].......................................... 707
13.3.5 P3MAP0 to P3MAP7 Register (offset = 18h to 1Fh) [reset = X] ......................................... 707
13.3.6 P4MAP0 to P4MAP7 Register (offset = 20h to 27h) [reset = X].......................................... 707
13.3.7 P5MAP0 to P5MAP7 Register (offset = 28h to 2Fh) [reset = X] ......................................... 707
13.3.8 P6MAP0 to P6MAP7 Register (offset = 30h to 37h) [reset = X].......................................... 708
13.3.9 P7MAP0 to P7MAP7 Register (offset = 38h to 3Fh) [reset = X] ......................................... 708
13.3.10 PxMAPyz Register [reset = X]............................................................................... 708
14 Capacitive Touch IO (CAPTIO)............................................................................................ 709
14.1 Capacitive Touch IO Introduction....................................................................................... 710
14.2 Capacitive Touch IO Operation......................................................................................... 711
14.3 CapTouch Registers...................................................................................................... 712
14.3.1 CAPTIOxCTL Register (offset = 0Eh) [reset = 0000h]..................................................... 713
15 CRC32 Module.................................................................................................................. 714
15.1 Cyclic Redundancy Check (CRC32) Module Introduction........................................................... 715
15.2 CRC Checksum Generation............................................................................................. 715
15.2.1 CRC Standard and Bit Order.................................................................................. 716
15.2.2 CRC Implementation........................................................................................... 716
15.3 CRC32 Registers ......................................................................................................... 717
16 AES256 Accelerator .......................................................................................................... 728

www.ti.com
12 SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
16.1 AES Accelerator Introduction............................................................................................ 729
16.2 AES Accelerator Operation.............................................................................................. 730
16.2.1 Load the Key (128-Bit, 192-Bit, or 256-Bit Keylength)..................................................... 731
16.2.2 Load the Data (128-Bit State)................................................................................. 731
16.2.3 Read the Data (128-Bit State) ................................................................................ 732
16.2.4 Trigger an Encryption or Decryption ......................................................................... 732
16.2.5 Encryption ....................................................................................................... 733
16.2.6 Decryption ....................................................................................................... 733
16.2.7 Decryption Key Generation.................................................................................... 734
16.2.8 AES Key Buffer ................................................................................................. 735
16.2.9 Using the AES Accelerator With Low-Power Modes....................................................... 736
16.2.10 AES Accelerator Interrupts................................................................................... 736
16.2.11 DMA Operation and Implementing Block Cipher Modes................................................. 736
16.3 AES256 Registers ........................................................................................................ 746
16.3.1 AESACTL0 Register............................................................................................ 747
16.3.2 AESACTL1 Register............................................................................................ 749
16.3.3 AESASTAT Register ........................................................................................... 750
16.3.4 AESAKEY Register............................................................................................. 751
16.3.5 AESADIN Register ............................................................................................. 752
16.3.6 AESADOUT Register .......................................................................................... 753
16.3.7 AESAXDIN Register............................................................................................ 754
16.3.8 AESAXIN Register.............................................................................................. 755
17 Watchdog Timer (WDT_A).................................................................................................. 756
17.1 WDT_A Introduction...................................................................................................... 757
17.2 WDT_A Operation ........................................................................................................ 759
17.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 759
17.2.2 Watchdog Mode ................................................................................................ 759
17.2.3 Interval Timer Mode ............................................................................................ 759
17.2.4 Watchdog Related Interrupts and Flags..................................................................... 760
17.2.5 Clock Sources of the WDT_A................................................................................. 760
17.2.6 WDT_A Operation in Different Device Power Modes...................................................... 760
17.3 WDT_A Registers......................................................................................................... 762
17.3.1 WDTCTL Register .............................................................................................. 763
18 Timer32 ........................................................................................................................... 764
18.1 Introduction ................................................................................................................ 765
18.2 Functional Description.................................................................................................... 765
18.3 Operation .................................................................................................................. 765
18.4 Interrupt Generation...................................................................................................... 766
18.5 Timer32 Registers ........................................................................................................ 767
18.5.1 T32LOAD1 Register (offset = 00h) [reset = 0h] ............................................................ 768
18.5.2 T32VALUE1 Register (offset = 04h) [reset = FFFFFFFFh] ............................................... 769
18.5.3 T32CONTROL1 Register (offset = 08h) [reset = 20h] ..................................................... 770
18.5.4 T32INTCLR1 Register (offset = 0Ch) [reset = undefined]................................................. 771
18.5.5 T32RIS1 Register (offset = 10h) [reset = 0h] ............................................................... 772
18.5.6 T32MIS1 Register (offset = 14h) [reset = 0h]............................................................... 773
18.5.7 T32BGLOAD1 Register (offset = 18h) [reset = 0h]......................................................... 774
18.5.8 T32LOAD2 Register (offset = 20h) [reset = 0h] ............................................................ 775
18.5.9 T32VALUE2 Register (offset = 24h) [reset = FFFFFFFFh] ............................................... 776
18.5.10 T32CONTROL2 Register (offset = 28h) [reset = 20h].................................................... 777
18.5.11 T32INTCLR2 Register (offset = 2Ch) [reset = undefined] ............................................... 778
18.5.12 T32RIS2 Register (offset = 30h) [reset = 0h].............................................................. 779
18.5.13 T32MIS2 Register (offset = 34h) [reset = 0h] ............................................................. 780
18.5.14 T32BGLOAD2 Register (offset = 38h) [reset = 0h]....................................................... 781

www.ti.com
13
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
19 Timer_A........................................................................................................................... 782
19.1 Timer_A Introduction ..................................................................................................... 783
19.2 Timer_A Operation ....................................................................................................... 785
19.2.1 16-Bit Timer Counter........................................................................................... 785
19.2.2 Starting the Timer............................................................................................... 785
19.2.3 Timer Mode Control ............................................................................................ 786
19.2.4 Capture/Compare Blocks...................................................................................... 789
19.2.5 Output Unit ...................................................................................................... 791
19.2.6 Timer_A Interrupts.............................................................................................. 795
19.3 Timer_A Registers........................................................................................................ 796
19.3.1 TAxCTL Register ............................................................................................... 797
19.3.2 TAxR Register................................................................................................... 798
19.3.3 TAxCCTL0 to TAxCCTL6 Register........................................................................... 799
19.3.4 TAxCCR0 to TAxCCR6 Register ............................................................................ 801
19.3.5 TAxIV Register.................................................................................................. 801
19.3.6 TAxEX0 Register ............................................................................................... 802
20 Real-Time Clock (RTC_C) .................................................................................................. 803
20.1 RTC_C Introduction ...................................................................................................... 804
20.2 RTC_C Operation......................................................................................................... 806
20.2.1 Calendar Mode.................................................................................................. 806
20.2.2 Real-Time Clock and Prescale Dividers..................................................................... 806
20.2.3 Real-Time Clock Alarm Function ............................................................................. 806
20.2.4 Real-Time Clock Protection ................................................................................... 807
20.2.5 Reading or Writing Real-Time Clock Registers............................................................. 807
20.2.6 Real-Time Clock Interrupts.................................................................................... 808
20.2.7 Real-Time Clock Calibration for Crystal Offset Error....................................................... 809
20.2.8 Real-Time Clock Compensation for Crystal Temperature Drift........................................... 809
20.2.9 Real-Time Clock Operation in Low-Power Modes ......................................................... 812
20.3 RTC_C Registers......................................................................................................... 813
20.3.1 RTCCTL0_L Register .......................................................................................... 815
20.3.2 RTCCTL0_H Register.......................................................................................... 816
20.3.3 RTCCTL1 Register ............................................................................................. 817
20.3.4 RTCCTL3 Register ............................................................................................. 818
20.3.5 RTCOCAL Register ............................................................................................ 819
20.3.6 RTCTCMP Register ............................................................................................ 820
20.3.7 RTCSEC Register – Hexadecimal Format .................................................................. 821
20.3.8 RTCSEC Register – BCD Format ............................................................................ 821
20.3.9 RTCMIN Register – Hexadecimal Format................................................................... 822
20.3.10 RTCMIN Register – BCD Format ........................................................................... 822
20.3.11 RTCHOUR Register – Hexadecimal Format .............................................................. 823
20.3.12 RTCHOUR Register – BCD Format ........................................................................ 823
20.3.13 RTCDOW Register ........................................................................................... 824
20.3.14 RTCDAY Register – Hexadecimal Format................................................................. 824
20.3.15 RTCDAY Register – BCD Format........................................................................... 824
20.3.16 RTCMON Register – Hexadecimal Format................................................................ 825
20.3.17 RTCMON Register – BCD Format.......................................................................... 825
20.3.18 RTCYEAR Register – Hexadecimal Format............................................................... 826
20.3.19 RTCYEAR Register – BCD Format......................................................................... 826
20.3.20 RTCAMIN Register – Hexadecimal Format ............................................................... 827
20.3.21 RTCAMIN Register – BCD Format ......................................................................... 827
20.3.22 RTCAHOUR Register – Hexadecimal Format ............................................................ 828
20.3.23 RTCAHOUR Register – BCD Format ...................................................................... 828
20.3.24 RTCADOW Register – Calendar Mode .................................................................... 829

www.ti.com
14 SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
20.3.25 RTCADAY Register – Hexadecimal Format............................................................... 829
20.3.26 RTCADAY Register – BCD Format......................................................................... 829
20.3.27 RTCPS0CTL Register ........................................................................................ 830
20.3.28 RTCPS1CTL Register ........................................................................................ 831
20.3.29 RTCPS0 Register ............................................................................................. 832
20.3.30 RTCPS1 Register ............................................................................................. 832
20.3.31 RTCIV Register................................................................................................ 833
20.3.32 RTCBIN2BCD Register....................................................................................... 834
20.3.33 RTCBCD2BIN Register....................................................................................... 834
21 Reference Module (REF_A) ................................................................................................ 835
21.1 REF_A Introduction....................................................................................................... 836
21.2 Principle of Operation .................................................................................................... 837
21.2.1 Low-Power Operation.......................................................................................... 837
21.2.2 Reference System Requests.................................................................................. 837
21.3 REF_A Registers ......................................................................................................... 839
21.3.1 REFCTL0 Register (offset = 00h) [reset = 0008h] ......................................................... 840
22 Precision ADC.................................................................................................................. 842
22.1 Precision ADC Introduction.............................................................................................. 843
22.2 Precision ADC Operation................................................................................................ 845
22.2.1 14-Bit ADC Core................................................................................................ 845
22.2.2 Precision ADC Inputs and Multiplexer ....................................................................... 846
22.2.3 Voltage References ............................................................................................ 846
22.2.4 Auto Power Down .............................................................................................. 846
22.2.5 Power Modes.................................................................................................... 846
22.2.6 Sample and Conversion Timing .............................................................................. 847
22.2.7 Conversion Memory............................................................................................ 849
22.2.8 Precision ADC Conversion Modes ........................................................................... 850
22.2.9 Window Comparator............................................................................................ 855
22.2.10 Using the Integrated Temperature Sensor................................................................. 856
22.2.11 Precision ADC Grounding and Noise Considerations.................................................... 857
22.2.12 Precision ADC Calibration ................................................................................... 858
22.2.13 Precision ADC Interrupts..................................................................................... 858
22.3 ADC14 Registers ......................................................................................................... 859
22.3.1 ADC14CTL0 Register (offset = 00h) [reset = 00000000h] ................................................ 860
22.3.2 ADC14CTL1 Register (offset = 04h) [reset = 00000030h] ................................................ 863
22.3.3 ADC14LO0 Register (offset = 08h) [reset = 00000000h].................................................. 865
22.3.4 ADC14HI0 Register (offset = 0Ch) [reset = 00003FFFh] ................................................. 866
22.3.5 ADC14LO1 Register (offset = 10h) [reset = 00000000h].................................................. 867
22.3.6 ADC14HI1 Register (offset = 14h) [reset = 00003FFFh] .................................................. 868
22.3.7 ADC14MCTL0 to ADC14MCTL31 Register (offset = 018h to 094h) [reset = 00000000h]............ 869
22.3.8 ADC14MEM0 to ADC14MEM31 Register (offset = 098h to 114h) [reset = Undefined]............... 871
22.3.9 ADC14IER0 Register (offset = 13Ch) [reset = 00000000h]............................................... 872
22.3.10 ADC14IER1 Register (offset = 140h) [reset = 00000000h].............................................. 875
22.3.11 ADC14IFGR0 Register (offset = 144h) [reset = 00000000h]............................................ 876
22.3.12 ADC14IFGR1 Register (offset = 148h) [reset = 00000000h]............................................ 880
22.3.13 ADC14CLRIFGR0 Register (offset = 14Ch) [reset = 00000000h]...................................... 881
22.3.14 ADC14CLRIFGR1 Register (offset = 150h) [reset = 00000000h] ...................................... 884
22.3.15 ADC14IV Register (offset = 154h) [reset = 00000000h] ................................................. 885
23 Comparator E Module (COMP_E)........................................................................................ 887
23.1 COMP_E Introduction.................................................................................................... 888
23.2 COMP_E Operation ...................................................................................................... 889
23.2.1 Comparator...................................................................................................... 889

www.ti.com
15
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
23.2.2 Analog Input Switches ......................................................................................... 889
23.2.3 Port Logic........................................................................................................ 889
23.2.4 Input Short Switch .............................................................................................. 889
23.2.5 Output Filter ..................................................................................................... 890
23.2.6 Reference Voltage Generator................................................................................. 891
23.2.7 Port Disable Register (CEPD) ................................................................................ 892
23.2.8 Comparator_E Interrupts ...................................................................................... 892
23.2.9 Comparator_E Used to Measure Resistive Elements ..................................................... 892
23.3 COMP_E Registers....................................................................................................... 895
23.3.1 CExCTL0 Register (offset = 00h) [reset = 0000h].......................................................... 896
23.3.2 CExCTL1 Register (offset = 02h) [reset = 0000h].......................................................... 897
23.3.3 CExCTL2 Register (offset = 04h) [reset = 0000h].......................................................... 898
23.3.4 CExCTL3 Register (offset = 06h) [reset = 0000h].......................................................... 899
23.3.5 CExINT Register (offset = 0Ch) [reset = 0000h]............................................................ 901
23.3.6 CExIV Register (offset = 0Eh) [reset = 0000h] ............................................................. 902
24 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode............................ 903
24.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview .................................. 904
24.2 eUSCI_A Introduction – UART Mode .................................................................................. 904
24.3 eUSCI_A Operation – UART Mode .................................................................................... 906
24.3.1 eUSCI_A Initialization and Reset............................................................................. 906
24.3.2 Character Format............................................................................................... 906
24.3.3 Asynchronous Communication Format ...................................................................... 906
24.3.4 Automatic Baud-Rate Detection .............................................................................. 909
24.3.5 IrDA Encoding and Decoding ................................................................................. 910
24.3.6 Automatic Error Detection ..................................................................................... 911
24.3.7 eUSCI_A Receive Enable ..................................................................................... 912
24.3.8 eUSCI_A Transmit Enable .................................................................................... 912
24.3.9 UART Baud-Rate Generation................................................................................. 913
24.3.10 Setting a Baud Rate .......................................................................................... 915
24.3.11 Transmit Bit Timing - Error calculation ..................................................................... 916
24.3.12 Receive Bit Timing – Error Calculation..................................................................... 916
24.3.13 Typical Baud Rates and Errors.............................................................................. 917
24.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................. 919
24.3.15 eUSCI_A Interrupts ........................................................................................... 919
24.3.16 DMA Operation................................................................................................ 921
24.4 eUSCI_A UART Registers............................................................................................... 922
24.4.1 UCAxCTLW0 Register ......................................................................................... 923
24.4.2 UCAxCTLW1 Register ......................................................................................... 924
24.4.3 UCAxBRW Register............................................................................................ 925
24.4.4 UCAxMCTLW Register ........................................................................................ 925
24.4.5 UCAxSTATW Register......................................................................................... 926
24.4.6 UCAxRXBUF Register ......................................................................................... 927
24.4.7 UCAxTXBUF Register ......................................................................................... 927
24.4.8 UCAxABCTL Register.......................................................................................... 928
24.4.9 UCAxIRCTL Register........................................................................................... 929
24.4.10 UCAxIE Register .............................................................................................. 930
24.4.11 UCAxIFG Register ............................................................................................ 931
24.4.12 UCAxIV Register .............................................................................................. 932
25 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode ............................... 933
25.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ....................... 934
25.2 eUSCI Introduction – SPI Mode ........................................................................................ 934
25.3 eUSCI Operation – SPI Mode........................................................................................... 936
25.3.1 eUSCI Initialization and Reset ................................................................................ 936

www.ti.com
16 SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
Contents
25.3.2 Character Format............................................................................................... 937
25.3.3 Master Mode .................................................................................................... 937
25.3.4 Slave Mode...................................................................................................... 938
25.3.5 SPI Enable....................................................................................................... 939
25.3.6 Serial Clock Control ............................................................................................ 939
25.3.7 Using the SPI Mode With Low-Power Modes............................................................... 940
25.3.8 SPI Interrupts.................................................................................................... 940
25.4 eUSCI_A SPI Registers.................................................................................................. 942
25.4.1 UCAxCTLW0 Register ......................................................................................... 943
25.4.2 UCAxBRW Register............................................................................................ 944
25.4.3 UCAxSTATW Register......................................................................................... 945
25.4.4 UCAxRXBUF Register ......................................................................................... 946
25.4.5 UCAxTXBUF Register ......................................................................................... 947
25.4.6 UCAxIE Register................................................................................................ 948
25.4.7 UCAxIFG Register.............................................................................................. 949
25.4.8 UCAxIV Register................................................................................................ 950
25.5 eUSCI_B SPI Registers.................................................................................................. 951
25.5.1 UCBxCTLW0 Register ......................................................................................... 952
25.5.2 UCBxBRW Register............................................................................................ 953
25.5.3 UCBxSTATW Register......................................................................................... 953
25.5.4 UCBxRXBUF Register ......................................................................................... 954
25.5.5 UCBxTXBUF Register ......................................................................................... 954
25.5.6 UCBxIE Register ............................................................................................... 955
25.5.7 UCBxIFG Register.............................................................................................. 955
25.5.8 UCBxIV Register................................................................................................ 956
26 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode ................................ 957
26.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview................................... 958
26.2 eUSCI_B Introduction – I2C Mode...................................................................................... 958
26.3 eUSCI_B Operation – I2C Mode ........................................................................................ 959
26.3.1 eUSCI_B Initialization and Reset............................................................................. 960
26.3.2 I2C Serial Data .................................................................................................. 960
26.3.3 I2C Addressing Modes ......................................................................................... 961
26.3.4 I2C Module Operating Modes ................................................................................. 962
26.3.5 Glitch Filtering................................................................................................... 972
26.3.6 I2C Clock Generation and Synchronization.................................................................. 972
26.3.7 Byte Counter .................................................................................................... 973
26.3.8 Multiple Slave Addresses...................................................................................... 974
26.3.9 Using the eUSCI_B Module in I2C Mode With Low-Power Modes....................................... 975
26.3.10 eUSCI_B Interrupts in I2C Mode ............................................................................ 975
26.4 eUSCI_B I2C Registers.................................................................................................. 977
26.4.1 UCBxCTLW0 Register ......................................................................................... 978
26.4.2 UCBxCTLW1 Register ......................................................................................... 980
26.4.3 UCBxBRW Register............................................................................................ 982
26.4.4 UCBxSTATW.................................................................................................... 982
26.4.5 UCBxTBCNT Register ......................................................................................... 983
26.4.6 UCBxRXBUF Register ......................................................................................... 984
26.4.7 UCBxTXBUF .................................................................................................... 984
26.4.8 UCBxI2COA0 Register......................................................................................... 985
26.4.9 UCBxI2COA1 Register......................................................................................... 986
26.4.10 UCBxI2COA2 Register ....................................................................................... 986
26.4.11 UCBxI2COA3 Register ....................................................................................... 987
26.4.12 UCBxADDRX Register ....................................................................................... 987
26.4.13 UCBxADDMASK Register ................................................................................... 988

www.ti.com
17
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Contents
26.4.14 UCBxI2CSA Register......................................................................................... 988
26.4.15 UCBxIE Register .............................................................................................. 989
26.4.16 UCBxIFG Register ............................................................................................ 991
26.4.17 UCBxIV Register .............................................................................................. 993
27 LCD_F Controller.............................................................................................................. 994
27.1 LCD_F Controller Introduction .......................................................................................... 995
27.1.1 Introduction...................................................................................................... 995
27.1.2 Features.......................................................................................................... 995
27.1.3 Functional Block Diagram ..................................................................................... 996
27.2 LCD_F Controller Architecture and Operation........................................................................ 997
27.2.1 Power Management ........................................................................................... 997
27.2.2 Clock System.................................................................................................... 997
27.2.3 Interrupts......................................................................................................... 997
27.2.4 Memory .......................................................................................................... 998
27.2.5 LCD_F Functional Operation.................................................................................. 999
27.3 LCD_F Registers........................................................................................................ 1015
27.3.1 LCDCTL Register ............................................................................................. 1021
27.3.2 LCDBMCTL Register ......................................................................................... 1023
27.3.3 LCDVCTL Register............................................................................................ 1025
27.3.4 LCDPCTL0 Register.......................................................................................... 1026
27.3.5 LCDPCTL1 Register.......................................................................................... 1030
27.3.6 LCDCSSEL0 Register........................................................................................ 1034
27.3.7 LCDCSSEL1 Register........................................................................................ 1037
27.3.8 LCDANMCTL Register ....................................................................................... 1040
27.3.9 LCDIE Register................................................................................................ 1042
27.3.10 LCDIFG Register ............................................................................................ 1043
27.3.11 LCDSETIFG Register ....................................................................................... 1044
27.3.12 LCDCLRIFG Register....................................................................................... 1045
27.3.13 LCDM[index] Register....................................................................................... 1046
27.3.14 LCDBM[index] Register..................................................................................... 1048
27.3.15 LCDANM[index] Register................................................................................... 1050
Revision History ...................................................................................................................... 1052

www.ti.com
18 SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
List of Figures
List of Figures
1-1. CPU Block Diagram........................................................................................................ 53
1-2. Cortex-M4F Register Set.................................................................................................. 56
1-3. Bit-Band Mapping .......................................................................................................... 64
1-4. Data Storage................................................................................................................ 65
1-5. Vector Table ................................................................................................................ 68
1-6. Exception Stack Frame.................................................................................................... 71
2-1. SRD Use Example ......................................................................................................... 88
2-2. FPU Register Bank......................................................................................................... 89
2-3. TPIU Block Diagram ....................................................................................................... 92
2-4. FPCCR Register............................................................................................................ 94
2-5. FPCAR Register............................................................................................................ 95
2-6. FPDSCR Register.......................................................................................................... 96
2-7. MVFR0 Register............................................................................................................ 97
2-8. MVFR1 Register............................................................................................................ 98
2-9. TYPE Register ............................................................................................................ 100
2-10. CTRL Register ............................................................................................................ 101
2-11. RNR Register.............................................................................................................. 102
2-12. RBAR Register............................................................................................................ 103
2-13. RASR Register............................................................................................................ 104
2-14. RBAR_A1 Register ....................................................................................................... 106
2-15. RASR_A1 Register ....................................................................................................... 107
2-16. RBAR_A2 Register ....................................................................................................... 109
2-17. RASR_A2 Register ....................................................................................................... 110
2-18. RBAR_A3 Register ....................................................................................................... 112
2-19. RASR_A3 Register ....................................................................................................... 113
2-20. ISER0 Register............................................................................................................ 116
2-21. ISER1 Register............................................................................................................ 116
2-22. ICER0 Register ........................................................................................................... 117
2-23. ICER1 Register ........................................................................................................... 117
2-24. ISPR0 Register............................................................................................................ 118
2-25. ISPR1 Register............................................................................................................ 118
2-26. ICPR0 Register ........................................................................................................... 119
2-27. ICPR1 Register ........................................................................................................... 119
2-28. IABR0 Register............................................................................................................ 120
2-29. IABR1 Register............................................................................................................ 120
2-30. IPR0 Register ............................................................................................................. 121
2-31. IPR1 Register ............................................................................................................. 121
2-32. IPR2 Register ............................................................................................................. 122
2-33. IPR3 Register ............................................................................................................. 122
2-34. IPR4 Register ............................................................................................................. 123
2-35. IPR5 Register ............................................................................................................. 123
2-36. IPR6 Register ............................................................................................................. 124
2-37. IPR7 Register ............................................................................................................. 124
2-38. IPR8 Register ............................................................................................................. 125
2-39. IPR9 Register ............................................................................................................. 125
2-40. IPR10 Register............................................................................................................ 126
2-41. IPR11 Register............................................................................................................ 126

www.ti.com
19
SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
List of Figures
2-42. IPR12 Register............................................................................................................ 127
2-43. IPR13 Register............................................................................................................ 127
2-44. IPR14 Register............................................................................................................ 128
2-45. IPR15 Register............................................................................................................ 128
2-46. STIR Register ............................................................................................................. 129
2-47. STCSR Register .......................................................................................................... 131
2-48. STRVR Register .......................................................................................................... 132
2-49. STCVR Register .......................................................................................................... 133
2-50. STCR Register............................................................................................................ 134
2-51. CPUID Register........................................................................................................... 136
2-52. ICSR Register............................................................................................................. 137
2-53. VTOR Register............................................................................................................ 139
2-54. AIRCR Register........................................................................................................... 140
2-55. SCR Register.............................................................................................................. 142
2-56. CCR Register.............................................................................................................. 143
2-57. SHPR1 Register .......................................................................................................... 144
2-58. SHPR2 Register .......................................................................................................... 145
2-59. SHPR3 Register .......................................................................................................... 146
2-60. SHCSR Register.......................................................................................................... 147
2-61. CFSR Register............................................................................................................ 149
2-62. HFSR Register............................................................................................................ 151
2-63. DFSR Register............................................................................................................ 152
2-64. MMFAR Register.......................................................................................................... 153
2-65. BFAR Register ............................................................................................................ 154
2-66. AFSR Register ............................................................................................................ 155
2-67. PFR0 Register............................................................................................................. 156
2-68. PFR1 Register............................................................................................................. 157
2-69. DFR0 Register ............................................................................................................ 158
2-70. AFR0 Register............................................................................................................. 159
2-71. MMFR0 Register.......................................................................................................... 160
2-72. MMFR1 Register.......................................................................................................... 161
2-73. MMFR2 Register.......................................................................................................... 162
2-74. MMFR3 Register.......................................................................................................... 163
2-75. ISAR0 Register............................................................................................................ 164
2-76. ISAR1 Register............................................................................................................ 165
2-77. ISAR2 Register............................................................................................................ 166
2-78. ISAR3 Register............................................................................................................ 167
2-79. ISAR4 Register............................................................................................................ 168
2-80. CPACR Register.......................................................................................................... 169
2-81. ICTR Register ............................................................................................................. 171
2-82. ACTLR Register........................................................................................................... 172
2-83. DHCSR Register.......................................................................................................... 174
2-84. DCRSR Register.......................................................................................................... 176
2-85. DCRDR Register.......................................................................................................... 177
2-86. DEMCR Register.......................................................................................................... 178
2-87. FP_CTRL Register ....................................................................................................... 181
2-88. FP_REMAP Register..................................................................................................... 182
2-89. FP_COMP0 Register..................................................................................................... 183
2-90. FP_COMP1 Register..................................................................................................... 184

www.ti.com
20 SLAU356I–March 2015–Revised June 2019
Submit Documentation Feedback
Copyright © 2015–2019, Texas Instruments Incorporated
List of Figures
2-91. FP_COMP2 Register..................................................................................................... 185
2-92. FP_COMP3 Register..................................................................................................... 186
2-93. FP_COMP4 Register..................................................................................................... 187
2-94. FP_COMP5 Register..................................................................................................... 188
2-95. FP_COMP6 Register..................................................................................................... 189
2-96. FP_COMP7 Register..................................................................................................... 190
2-97. CTRL Register ............................................................................................................ 192
2-98. CYCCNT Register ........................................................................................................ 194
2-99. CPICNT Register ......................................................................................................... 195
2-100. EXCCNT Register ........................................................................................................ 196
2-101. SLEEPCNT Register ..................................................................................................... 197
2-102. LSUCNT Register......................................................................................................... 198
2-103. FOLDCNT Register....................................................................................................... 199
2-104. PCSR Register............................................................................................................ 200
2-105. COMP0 Register.......................................................................................................... 201
2-106. MASK0 Register .......................................................................................................... 202
2-107. FUNCTION0 Register.................................................................................................... 203
2-108. COMP1 Register.......................................................................................................... 205
2-109. MASK1 Register .......................................................................................................... 206
2-110. FUNCTION1 Register.................................................................................................... 207
2-111. COMP2 Register.......................................................................................................... 209
2-112. MASK2 Register .......................................................................................................... 210
2-113. FUNCTION2 Register.................................................................................................... 211
2-114. COMP3 Register.......................................................................................................... 213
2-115. MASK3 Register .......................................................................................................... 214
2-116. FUNCTION3 Register.................................................................................................... 215
2-117. STIM0 Register ........................................................................................................... 218
2-118. STIM1 Register ........................................................................................................... 219
2-119. STIM2 Register ........................................................................................................... 220
2-120. STIM3 Register ........................................................................................................... 221
2-121. STIM4 Register ........................................................................................................... 222
2-122. STIM5 Register ........................................................................................................... 223
2-123. STIM6 Register ........................................................................................................... 224
2-124. STIM7 Register ........................................................................................................... 225
2-125. STIM8 Register ........................................................................................................... 226
2-126. STIM9 Register ........................................................................................................... 227
2-127. STIM10 Register.......................................................................................................... 228
2-128. STIM11 Register.......................................................................................................... 229
2-129. STIM12 Register.......................................................................................................... 230
2-130. STIM13 Register.......................................................................................................... 231
2-131. STIM14 Register.......................................................................................................... 232
2-132. STIM15 Register.......................................................................................................... 233
2-133. STIM16 Register.......................................................................................................... 234
2-134. STIM17 Register.......................................................................................................... 235
2-135. STIM18 Register.......................................................................................................... 236
2-136. STIM19 Register.......................................................................................................... 237
2-137. STIM20 Register.......................................................................................................... 238
2-138. STIM21 Register.......................................................................................................... 239
2-139. STIM22 Register.......................................................................................................... 240