Texas Instruments TMS320DM357 User manual

TMS320DM357 DMSoC Enhanced DirectMemory Access (EDMA3) Controller
User's Guide
Literature Number: SPRUG34November 2008

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Contents
Preface .............................................................................................................................. 13
1 Introduction ............................................................................................................. 171.1 Overview..................................................................................................................... 181.2 Features ..................................................................................................................... 181.3 Terminology Used in This Document .................................................................................... 19
2 EDMA3 Architecture ................................................................................................. 212.1 Functional Overview ....................................................................................................... 222.1.1 EDMA3 Controller Block Diagram ............................................................................... 222.1.2 EDMA3 Channel Controller (EDMA3CC) ...................................................................... 222.1.3 EDMA3 Transfer Controller (EDMA3TC) ....................................................................... 242.2 Types of EDMA3 Transfers ............................................................................................... 252.2.1 A-Synchronized Transfers........................................................................................ 262.2.2 AB-Synchronized Transfers ...................................................................................... 272.3 Parameter RAM (PaRAM) ................................................................................................ 282.3.1 PaRAM Set ......................................................................................................... 292.3.2 EDMA3 Channel Parameter Set Fields ........................................................................ 312.3.3 Null PaRAM Set ................................................................................................... 332.3.4 Dummy PaRAM Set............................................................................................... 332.3.5 Dummy Versus Null Transfer Comparison ..................................................................... 332.3.6 Parameter Set Updates .......................................................................................... 332.3.7 Linking Transfers .................................................................................................. 352.4 Initiating a DMA Transfer .................................................................................................. 382.4.1 DMA Channel ...................................................................................................... 382.4.2 QDMA Channels .................................................................................................. 412.4.3 Comparison Between DMA and QDMA Channels ............................................................ 412.5 Completion of a DMA Transfer ........................................................................................... 422.5.1 Normal Completion ................................................................................................ 432.5.2 Early Completion .................................................................................................. 432.5.3 Dummy or Null Completion ...................................................................................... 432.6 Event, Channel, and PaRAM Mapping .................................................................................. 432.6.1 DMA Channel to PaRAM Mapping .............................................................................. 442.6.2 QDMA Channel to PaRAM Mapping............................................................................ 442.7 EDMA3 Channel Controller Regions .................................................................................... 452.7.1 Region Overview .................................................................................................. 452.7.2 Channel Controller Regions...................................................................................... 472.8 Chaining EDMA3 Channels ............................................................................................... 472.9 EDMA3 Interrupts .......................................................................................................... 492.9.1 Transfer Completion Interrupts .................................................................................. 492.9.2 EDMA3 Interrupt Servicing ....................................................................................... 512.9.3 Interrupt Evaluation Operations ................................................................................. 542.9.4 Error Interrupts ..................................................................................................... 54
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2.10 Event Queue(s) ............................................................................................................. 552.10.1 DMA/QDMA Channel to Event Queue Mapping ............................................................. 562.10.2 Queue RAM Debug Visibility ................................................................................... 562.10.3 Queue Resource Tracking ...................................................................................... 562.10.4 Performance Considerations ................................................................................... 562.11 EDMA3 Transfer Controller (EDMA3TC) ................................................................................ 572.11.1 Architecture Details .............................................................................................. 572.11.2 Error Generation .................................................................................................. 582.11.3 Debug Features .................................................................................................. 592.11.4 EDMA3TC Configuration ........................................................................................ 592.12 Event Dataflow .............................................................................................................. 602.13 EDMA3 Prioritization ....................................................................................................... 612.13.1 Channel Priority .................................................................................................. 612.13.2 Trigger Source Priority ........................................................................................... 622.13.3 Dequeue Priority .................................................................................................. 622.13.4 System (Transfer Controller) Priority .......................................................................... 622.14 EDMA3 Operating Frequency (Clock Control) ......................................................................... 622.15 Reset Considerations ...................................................................................................... 622.16 Power Management ........................................................................................................ 632.17 Emulation Considerations ................................................................................................. 63
3 EDMA3 Transfer Examples ........................................................................................ 653.1 Block Move Example ...................................................................................................... 663.2 Subframe Extraction Example ............................................................................................ 683.3 Data Sorting Example ..................................................................................................... 703.4 Peripheral Servicing Example ............................................................................................ 723.4.1 Nonbursting Peripherals .......................................................................................... 723.4.2 Bursting Peripherals .............................................................................................. 743.4.3 Continuous Operation ............................................................................................ 763.4.4 Ping-Pong Buffering ............................................................................................... 793.4.5 Transfer Chaining Examples ..................................................................................... 82
4 Registers ................................................................................................................. 854.1 Register Memory Maps .................................................................................................... 864.2 Parameter RAM (PaRAM) Entries ....................................................................................... 864.2.1 Channel Options Parameter (OPT) ............................................................................. 874.2.2 Channel Source Address Parameter (SRC) ................................................................... 894.2.3 A Count/B Count Parameter (A_B_CNT) ...................................................................... 894.2.4 Channel Destination Address Parameter (DST) .............................................................. 904.2.5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ........................................ 904.2.6 Link Address/B Count Reload Parameter (LINK_BCNTRLD) ............................................... 914.2.7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ....................................... 924.2.8 C Count Parameter (CCNT) ..................................................................................... 924.3 EDMA3 Channel Controller Control Registers ......................................................................... 934.3.1 Global Registers ................................................................................................... 974.3.2 Error Registers ................................................................................................... 1024.3.3 Region Access Enable Registers .............................................................................. 1104.3.4 Status/Debug Visibility Registers .............................................................................. 1124.3.5 DMA Channel Registers ........................................................................................ 1164.3.6 Interrupt Registers ............................................................................................... 128
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4.3.7 QDMA Registers ................................................................................................. 1344.4 EDMA3 Transfer Controller Control Registers ........................................................................ 1404.4.1 Peripheral Identification Register (PID) ....................................................................... 1414.4.2 EDMA3TC Configuration Register (TCCFG) ................................................................. 1424.4.3 EDMA3TC Channel Status Register (TCSTAT) ............................................................. 1434.4.4 Error Registers ................................................................................................... 1444.4.5 Read Rate Register (RDRATE) ................................................................................ 1494.4.6 EDMA3TC Channel Registers ................................................................................. 149
A Tips ....................................................................................................................... 163A.1 Debug Checklist ........................................................................................................... 163A.2 Miscellaneous Programming/Debug Tips .............................................................................. 164
B Setting Up a Transfer .............................................................................................. 165
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List of Figures
2-1 EDMA3 Controller Block Diagram ........................................................................................ 222-2 EDMA3 Channel Controller (EDMA3CC) Block Diagram ............................................................. 232-3 EDMA3 Transfer Controller (EDMA3TC) Block Diagram ............................................................. 242-4 Definition of ACNT, BCNT, and CCNT ................................................................................. 252-5 A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ....................................................... 262-6 AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ..................................................... 272-7 PaRAM Set .................................................................................................................. 292-8 Linked Transfer ............................................................................................................. 362-9 Link-to-Self Transfer ....................................................................................................... 372-10 QDMA Channel to PaRAM Mapping .................................................................................... 452-11 Shadow Region Registers ................................................................................................ 462-12 Interrupt Diagram ........................................................................................................... 512-13 Error Interrupt Operation .................................................................................................. 552-14 EDMA3 Prioritization ....................................................................................................... 613-1 Block Move Example ...................................................................................................... 663-2 Block Move Example PaRAM Configuration............................................................................ 673-3 Subframe Extraction Example ............................................................................................ 683-4 Subframe Extraction Example PaRAM Configuration ................................................................. 693-5 Data Sorting Example ..................................................................................................... 703-6 Data Sorting Example PaRAM Configuration .......................................................................... 713-7 Servicing Incoming ASP Data Example ................................................................................. 723-8 Servicing Incoming ASP Data Example PaRAM ....................................................................... 733-9 Servicing Peripheral Burst Example ..................................................................................... 743-10 Servicing Peripheral Burst Example PaRAM ........................................................................... 753-11 Servicing Continuous ASP Data Example .............................................................................. 763-12 Servicing Continuous ASP Data Example PaRAM .................................................................... 773-13 Servicing Continuous ASP Data Example Reload PaRAM ........................................................... 783-14 Ping-Pong Buffering for ASP Data Example ........................................................................... 803-15 Ping-Pong Buffering for ASP Example PaRAM ........................................................................ 803-16 Ping-Pong Buffering for ASP Example Pong PaRAM ................................................................. 813-17 Ping-Pong Buffering for ASP Example Ping PaRAM .................................................................. 823-18 Intermediate Transfer Completion Chaining Example ................................................................. 833-19 Single Large Block Transfer Example ................................................................................... 843-20 Smaller Packet Data Transfers Example ................................................................................ 844-1 Channel Options Parameter (OPT) ...................................................................................... 874-2 Channel Source Address Parameter (SRC) ............................................................................ 894-3 A Count/B Count Parameter (A_B_CNT) ............................................................................... 894-4 Channel Destination Address Parameter (DST) ....................................................................... 904-5 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) ................................................. 904-6 Link Address/B Count Reload Parameter (LINK_BCNTRLD) ........................................................ 914-7 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) ................................................ 924-8 C Count Parameter (CCNT) .............................................................................................. 924-9 Peripheral ID Register (PID) .............................................................................................. 974-10 EDMA3CC Configuration Register (CCCFG) ........................................................................... 974-11 QDMA Channel Map nRegisters (QCHMAP n)........................................................................ 994-12 DMA Channel Queue Number Registers (DMAQNUM n)............................................................ 1004-13 QDMA Channel Queue Number Register (QDMAQNUM) .......................................................... 1014-14 Queue Priority Register (QUEPRI) ..................................................................................... 1024-15 Event Missed Register (EMR) ........................................................................................... 1034-16 Event Missed Register High (EMRH) .................................................................................. 1034-17 Event Missed Clear Register (EMCR) ................................................................................. 1044-18 Event Missed Clear Register High (EMCRH) ......................................................................... 104
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4-19 QDMA Event Missed Register (QEMR) ................................................................................ 1054-20 QDMA Event Missed Clear Register (QEMCR) ...................................................................... 1064-21 EDMA3CC Error Register (CCERR) ................................................................................... 1074-22 EDMA3CC Error Clear Register (CCERRCLR) ....................................................................... 1084-23 Error Evaluation Register (EEVAL) ..................................................................................... 1094-24 DMA Region Access Enable Register for Region m(DRAE m)..................................................... 1104-25 DMA Region Access Enable High Register for Region m(DRAEH m)............................................ 1104-26 QDMA Region Access Enable for Region m(QRAE m)............................................................. 1114-27 Event Queue Entry Registers (Q xEy).................................................................................. 1124-28 Queue nStatus Register (QSTAT n)................................................................................... 1134-29 Queue Watermark Threshold A Register (QWMTHRA) ............................................................. 1144-30 EDMA3CC Status Register (CCSTAT) ................................................................................ 1154-31 Event Register (ER) ...................................................................................................... 1174-32 Event Register High (ERH) .............................................................................................. 1174-33 Event Clear Register (ECR) ............................................................................................. 1184-34 Event Clear Register High (ECRH) ..................................................................................... 1184-35 Event Set Register (ESR)................................................................................................ 1194-36 Event Set Register High (ESRH) ....................................................................................... 1204-37 Chained Event Register (CER) ......................................................................................... 1214-38 Chained Event Register High (CERH) ................................................................................. 1214-39 Event Enable Register (EER) ........................................................................................... 1224-40 Event Enable Register High (EERH) ................................................................................... 1224-41 Event Enable Clear Register (EECR) .................................................................................. 1234-42 Event Enable Clear Register High (EECRH) .......................................................................... 1234-43 Event Enable Set Register (EESR) .................................................................................... 1244-44 Event Enable Set Register High (EESRH) ............................................................................ 1244-45 Secondary Event Register (SER) ....................................................................................... 1254-46 Secondary Event Register High (SERH) .............................................................................. 1264-47 Secondary Event Clear Register (SECR) ............................................................................. 1264-48 Secondary Event Clear Register High (SECRH) ..................................................................... 1274-49 Interrupt Enable Register (IER) ......................................................................................... 1284-50 Interrupt Enable Register High (IERH) ................................................................................. 1284-51 Interrupt Enable Clear Register (IECR) ................................................................................ 1294-52 Interrupt Enable Clear Register High (IECRH) ........................................................................ 1294-53 Interrupt Enable Set Register (IESR) .................................................................................. 1304-54 Interrupt Enable Set Register High (IESRH) .......................................................................... 1304-55 Interrupt Pending Register (IPR) ........................................................................................ 1314-56 Interrupt Pending Register High (IPRH) ............................................................................... 1314-57 Interrupt Clear Register (ICR) ........................................................................................... 1324-58 Interrupt Clear Register High (ICRH) ................................................................................... 1324-59 Interrupt Evaluate Register (IEVAL) .................................................................................... 1334-60 QDMA Event Register (QER) ........................................................................................... 1344-61 QDMA Event Enable Register (QEER) ................................................................................ 1354-62 QDMA Event Enable Clear Register (QEECR) ....................................................................... 1364-63 QDMA Event Enable Set Register (QEESR) ......................................................................... 1374-64 QDMA Secondary Event Register (QSER) ............................................................................ 1384-65 QDMA Secondary Event Clear Register (QSECR) .................................................................. 1394-66 Peripheral ID Register (PID)............................................................................................. 1414-67 EDMA3TC Configuration Register (TCCFG) .......................................................................... 1424-68 EDMA3TC Channel Status Register (TCSTAT) ...................................................................... 1434-69 Error Status Register (ERRSTAT) ...................................................................................... 1444-70 Error Enable Register (ERREN) ........................................................................................ 1454-71 Error Clear Register (ERRCLR) ........................................................................................ 146
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4-72 Error Details Register (ERRDET) ....................................................................................... 1474-73 Error Interrupt Command Register (ERRCMD) ....................................................................... 1484-74 Read Rate Register (RDRATE) ......................................................................................... 1494-75 Source Active Options Register (SAOPT) ............................................................................. 1504-76 Source Active Source Address Register (SASRC) ................................................................... 1514-77 Source Active Count Register (SACNT) ............................................................................... 1514-78 Source Active Destination Address Register (SADST) .............................................................. 1524-79 Source Active Source B-Dimension Index Register (SABIDX) ..................................................... 1524-80 Source Active Memory Protection Proxy Register (SAMPPRXY) .................................................. 1534-81 Source Active Count Reload Register (SACNTRLD) ................................................................ 1544-82 Source Active Source Address B-Reference Register (SASRCBREF) ............................................ 1544-83 Source Active Destination Address B-Reference Register (SADSTBREF) ....................................... 1554-84 Destination FIFO Options Register (DFOPT n)........................................................................ 1564-85 Destination FIFO Source Address Register (DFSRC n).............................................................. 1574-86 Destination FIFO Count Register (DFCNT n).......................................................................... 1584-87 Destination FIFO Destination Address Register (DFDST n)......................................................... 1594-88 Destination FIFO B-Index Register (DFBIDX n)....................................................................... 1594-89 Destination FIFO Memory Protection Proxy Register (DFMPPRXY n)............................................. 1604-90 Destination FIFO Count Reload Register (DFCNTRLD n)........................................................... 1614-91 Destination FIFO Source Address B-Reference Register (DFSRCBREF n)...................................... 1614-92 Destination FIFO Destination Address B-Reference Register (DFDSTBREF n).................................. 162
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List of Tables
2-1 EDMA3 Parameter RAM Contents ....................................................................................... 282-2 EDMA3 Channel Parameter Description ................................................................................ 302-3 Dummy and Null Transfer Request ...................................................................................... 332-4 Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ....................................... 342-5 EDMA3 Channel Synchronization Events ............................................................................... 382-6 Expected Number of Transfers for Non-Null Transfer ................................................................. 422-7 EDMA3 DMA Channel to PaRAM Mapping ............................................................................ 442-8 Shadow Region Registers ................................................................................................ 462-9 EDMA3 Shadow Regions ................................................................................................. 472-10 Chain Event Triggers ...................................................................................................... 482-11 EDMA3 Transfer Completion Interrupts ................................................................................. 492-12 EDMA3 Error Interrupts ................................................................................................... 492-13 Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping ................................................... 502-14 Number of Interrupts ....................................................................................................... 502-15 Read/Write Command Optimization Rules.............................................................................. 582-16 EDMA3 Transfer Controller Configurations ............................................................................. 594-1 EDMA3 Channel Controller (EDMA3CC) Parameter RAM (PaRAM) Entries ...................................... 864-2 Channel Options Parameters (OPT) Field Descriptions .............................................................. 874-3 Channel Source Address Parameter (SRC) Field Descriptions ...................................................... 894-4 A Count/B Count Parameter (A_B_CNT) Field Descriptions ......................................................... 894-5 Channel Destination Address Parameter (DST) Field Descriptions ................................................. 904-6 Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions .......................... 904-7 Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions .................................. 914-8 Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions .......................... 924-9 C Count Parameter (CCNT) Field Descriptions ........................................................................ 924-10 EDMACC Registers ........................................................................................................ 934-11 Peripheral ID Register (PID) Field Descriptions ........................................................................ 974-12 EDMA3CC Configuration Register (CCCFG) Field Descriptions .................................................... 984-13 QDMA Channel Map nRegisters (QCHMAP n) Field Descriptions .................................................. 994-14 DMA Channel Queue Number Registers (DMAQNUM n) Field Descriptions ..................................... 1004-15 Bits in DMAQNUM n...................................................................................................... 1004-16 QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions .................................... 1014-17 Queue Priority Register (QUEPRI) Field Descriptions ............................................................... 1024-18 Event Missed Register (EMR) Field Descriptions .................................................................... 1034-19 Event Missed Register High (EMRH) Field Descriptions ............................................................ 1034-20 Event Missed Clear Register (EMCR) Field Descriptions ........................................................... 1044-21 Event Missed Clear Register High (EMCRH) Field Descriptions ................................................... 1044-22 QDMA Event Missed Register (QEMR) Field Descriptions ......................................................... 1054-23 QDMA Event Missed Clear Register (QEMCR) Field Descriptions ................................................ 1064-24 EDMA3CC Error Register (CCERR) Field Descriptions ............................................................. 1074-25 EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ................................................ 1084-26 Error Evaluation Register (EEVAL) Field Descriptions .............................................................. 1094-27 DMA Region Access Enable Registers for Region m(DRAE m/DRAEH m) Field Descriptions ................. 1104-28 QDMA Region Access Enable for Region m(QRAE m) Field Descriptions ....................................... 1114-29 Event Queue Entry Registers (Q xEy) Field Descriptions ............................................................ 1124-30 Queue nStatus Register (QSTAT n) Field Descriptions ............................................................. 1134-31 Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................... 1144-32 EDMA3CC Status Register (CCSTAT) Field Descriptions .......................................................... 1154-33 Event Register (ER) Field Descriptions ................................................................................ 117
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4-34 Event Register High (ERH) Field Descriptions ........................................................................ 1174-35 Event Clear Register (ECR) Field Descriptions ....................................................................... 1184-36 Event Clear Register High (ECRH) Field Descriptions .............................................................. 1184-37 Event Set Register (ESR) Field Descriptions ......................................................................... 1194-38 Event Set Register High (ESRH) Field Descriptions ................................................................. 1204-39 Chained Event Register (CER) Field Descriptions ................................................................... 1214-40 Chained Event Register High (CERH) Field Descriptions ........................................................... 1214-41 Event Enable Register (EER) Field Descriptions ..................................................................... 1224-42 Event Enable Register High (EERH) Field Descriptions ............................................................. 1234-43 Event Enable Clear Register (EECR) Field Descriptions ............................................................ 1234-44 Event Enable Clear Register High (EECRH) Field Descriptions ................................................... 1244-45 Event Enable Set Register (EESR) Field Descriptions ............................................................. 1244-46 Event Enable Set Register High (EESRH) Field Descriptions ...................................................... 1254-47 Secondary Event Register (SER) Field Descriptions ................................................................ 1254-48 Secondary Event Register High (SERH) Field Descriptions ........................................................ 1264-49 Secondary Event Clear Register (SECR) Field Descriptions ....................................................... 1264-50 Secondary Event Clear Register High (SECRH) Field Descriptions ............................................... 1274-51 Interrupt Enable Register (IER) Field Descriptions ................................................................... 1284-52 Interrupt Enable Register High (IERH) Field Descriptions .......................................................... 1284-53 Interrupt Enable Clear Register (IECR) Field Descriptions .......................................................... 1294-54 Interrupt Enable Clear Register High (IECRH) Field Descriptions ................................................. 1294-55 Interrupt Enable Set Register (IESR) Field Descriptions ............................................................ 1304-56 Interrupt Enable Set Register High (IESRH) Field Descriptions .................................................... 1304-57 Interrupt Pending Register (IPR) Field Descriptions ................................................................. 1314-58 Interrupt Pending Register High (IPRH) Field Descriptions ......................................................... 1314-59 Interrupt Clear Register (ICR) Field Descriptions ..................................................................... 1324-60 Interrupt Clear Register High (ICRH) Field Descriptions ............................................................ 1324-61 Interrupt Evaluate Register (IEVAL) Field Descriptions ............................................................. 1334-62 QDMA Event Register (QER) Field Descriptions ..................................................................... 1344-63 QDMA Event Enable Register (QEER) Field Descriptions .......................................................... 1354-64 QDMA Event Enable Clear Register (QEECR) Field Descriptions ................................................. 1364-65 QDMA Event Enable Set Register (QEESR) Field Descriptions ................................................... 1374-66 QDMA Secondary Event Register (QSER) Field Descriptions ..................................................... 1384-67 QDMA Secondary Event Clear Register (QSECR) Field Descriptions ............................................ 1394-68 EDMA3 Transfer Controller Registers ................................................................................. 1404-69 Peripheral ID Register (PID) Field Descriptions ...................................................................... 1414-70 EDMA3TC Configuration Register (TCCFG) Field Descriptions ................................................... 1424-71 EDMA3TC Channel Status Register (TCSTAT) Field Descriptions ................................................ 1434-72 Error Status Register (ERRSTAT) Field Descriptions ............................................................... 1444-73 Error Enable Register (ERREN) Field Descriptions .................................................................. 1454-74 Error Clear Register (ERRCLR) Field Descriptions .................................................................. 1464-75 Error Details Register (ERRDET) Field Descriptions ................................................................ 1474-76 Error Interrupt Command Register (ERRCMD) Field Descriptions ................................................. 1484-77 Read Rate Register (RDRATE) Field Descriptions .................................................................. 1494-78 Source Active Options Register (SAOPT) Field Descriptions ....................................................... 1504-79 Source Active Source Address Register (SASRC) Field Descriptions ............................................ 1514-80 Source Active Count Register (SACNT) Field Descriptions ......................................................... 1514-81 Source Active Destination Address Register (SADST) Field Descriptions ........................................ 1524-82 Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions ............................... 1524-83 Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ............................ 1534-84 Source Active Count Reload Register (SACNTRLD) Field Descriptions .......................................... 154
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4-85 Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions ..................... 1544-86 Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions ................. 1554-87 Destination FIFO Options Register (DFOPT n) Field Descriptions ................................................. 1564-88 Destination FIFO Source Address Register (DFSRC n) Field Descriptions ....................................... 1574-89 Destination FIFO Count Register (DFCNT n) Field Descriptions ................................................... 1584-90 Destination FIFO Destination Address Register (DFDST n) Field Descriptions ................................... 1594-91 Destination FIFO B-Index Register (DFBIDX n) Field Descriptions ................................................. 1594-92 Destination FIFO Memory Protection Proxy Register (DFMPPRXY n) Field Descriptions ...................... 1604-93 Destination FIFO Count Reload Register (DFCNTRLD n) Field Descriptions ..................................... 1614-94 Destination FIFO Source Address B-Reference Register (DFSRCBREF n) Field Descriptions ................ 1614-95 Destination FIFO Destination Address B-Reference Register (DFDSTBREF n) Field Descriptions ........... 162A-1 Debug List ................................................................................................................. 163
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PrefaceSPRUG34 – November 2008
Read This First
About This Manual
Describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM357Digital Media System-on-Chip (DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM357 Digital Media System-on-Chip (DMSoC). Copies ofthese documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.
SPRUG06 —TMS320DM357 DMSoC Video Processing Back End (VPBE) User's Guide. Describesthe video processing back end (VPBE) in the TMS320DM357 Digital Media System-on-Chip(DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screendisplay, and digital LCD controller.
SPRUG25 —TMS320DM357 DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the video processing subsystem,and a majority of the peripherals and external memories.
SPRUG26 —TMS320DM357 DMSoC Universal Asynchronous Receiver/Transmitter (UART) User'sGuide. This document describes the universal asynchronous receiver/transmitter (UART) peripheralin the TMS320DM357 Digital Media System-on-Chip (DMSoC). The UART peripheral performsserial-to-parallel conversion on data received from a peripheral device, and parallel-to-serialconversion on data received from the CPU.
SPRUG27 —TMS320DM357 DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide.Describes the inter-integrated circuit (I2C) peripheral in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and otherdevices compliant with the I2C-bus specification and connected by way of an I2C-bus. Externalcomponents attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to andfrom the DMSoC through the I2C peripheral. This document assumes the reader is familiar with theI2C-bus specification.
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SPRUG28 —TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes the operation of thesoftware-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC).Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bitmode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as awatchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanceddirect memory access (EDMA) synchronization events. The watchdog timer mode is used toprovide a recovery mechanism for the device in the event of a fault condition, such as a non-exitingcode loop.
SPRUG29 —TMS320DM357 DMSoC Serial Peripheral Interface (SPI) User's Guide. Describes theserial peripheral interface (SPI) in the TMS320DM357 Digital Media System-on-Chip (DMSoC). TheSPI is a high-speed synchronous serial input/output port that allows a serial bit stream ofprogrammed length (1 to 16 bits) to be shifted into and out of the device at a programmedbit-transfer rate. The SPI is normally used for communication between the DMSoC and externalperipherals. Typical applications include an interface to external I/O or peripheral expansion viadevices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters.
SPRUG30 —TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide. This documentdescribes the host port interface in the TMS320DM357 Digital Media System-on-Chip (DMSoC).The HPI provides a parallel port interface through which an external host processor can directlyaccess the TMS320DM357 DMSoC processor's resources (configuration and program/datamemories).
SPRUG31 —TMS320DM357 DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describesthe general-purpose input/output (GPIO) peripheral in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that canbe configured as either inputs or outputs. When configured as an input, you can detect the state ofthe input by reading the state of an internal register. When configured as an output, you can writeto an internal register to control the state driven on the output pin.
SPRUG32 —TMS320DM357 DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card ControllerUser's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in theTMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number ofapplications to provide removable data storage. The MMC/SD controller provides an interface toexternal MMC and SD cards. The communication between the MMC/SD controller and MMC/SDcard(s) is performed by the MMC/SD protocol.
SPRUG33 —TMS320DM357 DMSoC Asynchronous External Memory Interface (EMIF) User'sGuide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM357Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety ofexternal devices.
SPRUG34 —TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA) Controller User'sGuide. Describes the operation of the enhanced direct memory access (EDMA3) controller in theTMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 controller’s primary purposeis to service user-programmed data transfers between two memory-mapped slave endpoints on theDMSoC.
SPRUG35 —TMS320DM357 DMSoC Audio Serial Port (ASP) User's Guide. Describes the operationof the audio serial port (ASP) audio interface in the TMS320DM357 Digital Media System-on-Chip(DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. Inaddition to the primary audio modes, the ASP supports general serial port receive and transmitoperation, but is not intended to be used as a high-speed interface.
SPRUG36 —TMS320DM357 DMSoC Ethernet Media Access Controller (EMAC)/Management DataInput/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller(EMAC) and physical layer (PHY) device management data input/output (MDIO) module in theTMS320DM357 Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packetdata from the DMSoC to the PHY. The MDIO module controls PHY configuration and statusmonitoring.
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www.ti.com Notational Conventions
SPRUG37 —TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide.Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC).
SPRUG38 —TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2memory controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The DDR2memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices.
SPRUG39 —TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describesthe video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip(DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller,resizer, histogram, and hardware 3A (H3A) statistic generator.
SPRUGH2 —TMS320DM357 DMSoC Peripherals Overview Reference Guide. This document providesan overview of the peripherals in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
SPRUGH3 —TMS320DM357 DMSoC Universal Serial Bus Controller User's Guide. This documentdescribes the universal serial bus (USB) controller in the TMS320DM357 Digital MediaSystem-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. Itprovides a mechanism for data transfer between USB devices and also supports host negotiation.
Trademarks
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Chapter 1SPRUG34 – November 2008
Introduction
This document describes the features and operations of the enhanced direct memory access (EDMA3)controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
The EDMA3 is a high-performance, multichannel, multithreaded DMA controller that allows you to programa wide variety of transfer geometries and transfer sequences.
Chapter 1 provides a brief overview, features, and terminology. Chapter 2 provides the architecture detailsand common operations of the EDMA3 channel controller (EDMA3CC) and the EDMA3 transfer controller(EDMA3TC). Chapter 3 contains examples and common usage scenarios. Chapter 4 describes thememory-mapped registers associated with the EDMA3 controller.
Topic .................................................................................................. Page
1.1 Overview .................................................................................. 181.2 Features ................................................................................... 181.3 Terminology Used in This Document ........................................... 19
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1.1 Overview
1.2 Features
Overview www.ti.com
The enhanced direct memory access (EDMA3) controller’s primary purpose is to serviceuser-programmed data transfers between two memory-mapped slave endpoints on the device. Typicalusage includes, but is not limited to:•Servicing software driven paging transfers (for example, from external memory such as SDRAM tointernal device memory such as TCM•Servicing event driven peripherals, such as a serial port•Performing sorting or subframe extraction of various data structures•Offloading data transfers from the main device CPU(s) (See the device data manual for specificperipherals that are accessible via EDMA3. See the section on SCR connectivity in the device datamanual for EDMA3 connectivity.)
The EDMA3 controller consists of two principal blocks:•EDMA3 channel controller (EDMA3CC)•EDMA3 transfer controller(s) (EDMA3TC)
The EDMA3 channel controller serves as the user interface for the EDMA3 controller. The EDMA3CCincludes parameter RAM (PaRAM), channel control registers, and interrupt control registers. TheEDMA3CC serves to prioritize incoming software requests or events from peripherals, and submitstransfer requests (TR) to the transfer controller.
The EDMA3 transfer controllers are slaves to the EDMA3 channel controller responsible for datamovement. The transfer controller issues read/write commands to the source and destination addressesprogrammed for a given transfer. The operation is transparent to you.
The EDMA3 channel controller has following features:•Fully orthogonal transfer description– 3 transfer dimensions– A-synchronized transfers: 1 dimension serviced per event– AB- synchronized transfers: 2 dimensions serviced per event– Independent indexes on source and destination– Chaining feature allows 3-D transfer based on single event•Flexible transfer definition– Increment or constant transfer addressing modes– Linking mechanism allows automatic PaRAM set update– Chaining allows multiple transfers to execute with one event•Interrupt generation for:– Transfer completion– Error conditions•Debug visibility– Queue watermarking/threshold
– Error and status recording to facilitate debug•64 DMA channels– Event synchronization
– Manual synchronization (CPU(s) write to event set register)– Chain synchronization (completion of one transfer triggers another transfer)•8 QDMA channels– QDMA channels are triggered automatically upon writing to a PaRAM set entry– Support for programmable QDMA channel to PaRAM mapping
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1.3 Terminology Used in This Document
www.ti.com Terminology Used in This Document
•128 PaRAM sets– Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)•2 transfer controllers/event queues. The system-level priority of these queues is user programmable.(See the device data manual for the possible system priorities.)•16 event entries per event queue
The EDMA3 transfer controller has following features:•2 transfer controllers (TC)•64-bit wide read and write ports per TC•Up to 4 in-flight transfer requests (TR)•Programmable priority level•Supports 2 dimensional transfers with independent indexes on source and destination (EDMA3CCmanages the 3rd dimension)•Support for increment or constant addressing mode transfers•Interrupt and error support
The following is a brief explanation of some terms used in this document:
Term MeaningA-synchronized A transfer type where 1 dimension is serviced per synchronization event.transfer
AB-synchronized A transfer type where 2 dimensions are serviced per synchronization event.transfer
Chaining A trigger mechanism in which a transfer can be initiated at the completion of anothertransfer or subtransfer.CPU(s) The main processing engine or engines on a device. Typically an ARM orgeneral-purpose processor. (See the device data manual to learn more about theCPU on your system.)Device TMS320DM357 DMSoCDMA channel One of the 64 channels that can be triggered by external, manual, and chainedevents. All DMA channels exist in the EDMA3CC.Dummy set or A PaRAM set for which at least one of the count fields is equal to 0 and at least oneDummy PaRAM set of the count fields is nonzero. A null PaRAM set has all the count set fields cleared.Dummy transfer A dummy set results in the EDMA3CC performing a dummy transfer. This is not anerror condition. A null set results in an error condition.EDMA3 channel The user-programmable portion of the EDMA3. The EDMA3CC contains thecontroller parameter RAM (PaRAM) , event processing logic, DMA/QDMA channels, event(EDMA3CC) queues, etc. The EDMA3CC services events (external, manual, chained, QDMA)and is responsible for submitting transfer requests to the transfer controllers(EDMA3TC), which perform the actual transfer.EDMA3 Any entity on the chip that has read/write access to the EDMA3 registers and canprogrammer program an EDMA3 transfer.EDMA3 transfer Transfer controllers are the transfer engine for the EDMA3. Performs the read/writescontroller(s) as dictated by the transfer requests submitted by the EDMA3CC.(EDMA3TC)
Enhanced direct Consists of the EDMA3 channel controller (EDMA3CC) and EDMA3 transfermemory access controller(s) (EDMA3TC). Is referred to as EDMA3 in this document.(EDMA3)
controller
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Terminology Used in This Document www.ti.com
Term MeaningLink parameter set A PaRAM set that is used for linking.Linking The mechanism of reloading a PaRAM set with new transfer characteristics oncompletion of the current transfer.Memory-mapped All on-chip memories, off-chip memories, and slave peripherals. These typically relyslave on the EDMA3 (or other master peripheral) to perform transfers to and from them.Master All peripherals that are capable of initiating read and write transfers to theperipherals peripherals system and may not solely rely on the EDMA3 for their data transfers.Null set or Null A PaRAM set that has all count fields cleared (except for the link field). A dummyPaRAM set PaRAM set has at least one of the count fields nonzero.Null transfer A trigger event for a null PaRAM set results in the EDMA3CC performing a nulltransfer. This is an error condition. A dummy transfer is not an error condition.QDMA channel One of the 8 channels that can be triggered when writing to the trigger word(TRWORD) of a PaRAM set. All QDMA channels exist in the EDMA3CC.Parameter RAM Programmable RAM that stores PaRAM sets used by DMA channels, QDMA(PaRAM) channels, and linking.Parameter RAM A 32-byte EDMA3 channel transfer definition. Each parameter set consists of 8(PaRAM) set words ( 4-bytes each), which store the context for a DMA/QDMA/link transfer. APaRAM set includes source address, destination address, counts, indexes, options,etc.Parameter RAM One of the 4-byte components of the parameter set.(PaRAM) set entrySlave end points All on-chip memories, off-chip memories, and slave peripherals. These rely on theEDMA3 to perform transfers to and from them.Transfer request A command for data movement that is issued from the EDMA3CC to the EDMA3TC.(TR) A TR includes source and destination addresses, counts, indexes, options, etc.Trigger event Action that causes the EDMA3CC to service the PaRAM set and submit a transferrequest to the EDMA3TC. Trigger events for DMA channels include manualtriggered (CPU triggered), external event triggered, and chain triggered. Triggerevents for QDMA channels include autotriggered and link triggered.Trigger word For QDMA channels, the trigger word specifies the PaRAM set entry that whenwritten results in a QDMA trigger event. The trigger word is programmed via theQDMA channel map register (QCHMAP) and can point to any PaRAM set entry.TR synchronization See Trigger Event.(sync) event
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