
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
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SPRS881A –AUGUST 2014–REVISED JUNE 2015
•Section 5.3: Added reference to the Calculating Useful Lifetimes of Embedded Processors Application Report
(SPRABX4). ......................................................................................................................... 51
•Section 5.4 (Electrical Characteristics): Updated VOH, VOL, IOH, IOL, IOZ, VIH, VIL, IIH, and IIL .............................. 51
•Section 5.5 (Power Consumption Summary): Added section. ................................................................ 52
•Section 5.5.1 (Operational Current Consumption Graphs): Added section. ................................................ 53
•Section 5.6 (Thermal Resistance Characteristics): Added section. .......................................................... 56
•Section 5.6.1 (ZWT Package): Added section. ................................................................................. 56
•Section 5.6.2 (PTP Package): Added section. .................................................................................. 56
•Section 5.6.3 (PZP Package): Added section. .................................................................................. 57
•Section 5.7 (System): Changed section title from "Timing and Switching Characteristics" to "System". ............... 58
•Section 5.7.1 (Power Sequencing): Changed section title from "Power Management" to "Power Sequencing". ...... 58
•Section 5.7.1: Updated and restructured section. .............................................................................. 58
•Section 5.7.2 (Reset Timing): Added section. .................................................................................. 58
•Section 5.7.3 (Clock Specifications): Changed section title from "Clocking" to "Clock Specifications". ................ 60
•Section 5.7.3.1 (Clock Sources): Removed "Clocking Options for System PLL" figure (which was Figure 5-1 in
SPRS881). .......................................................................................................................... 60
•Section 5.7.3.1: Removed NOTE about clock name, PERx.SYSCLK. ...................................................... 60
•Section 5.7.3.1: Removed "Clocking Options for Auxiliary PLL" figure (which was Figure 5-2 in SPRS881). ......... 60
•Section 5.7.3.1: Removed "Peripheral Clock Options" figure (which was Figure 5-3 in SPRS881). .................... 60
•Figure 5-5 (Device Clocking): Added figure. .................................................................................... 61
•Table 5-6 (Input Clock Frequency): Changed MIN value of f(OSC) from 2 MHz to 10 MHz. ............................... 62
•Table 5-7 (X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)): Added table. .... 62
•Table 5-10 (PLL Lock Times): Updated table and footnote. .................................................................. 62
•Table 5-11 (Internal Clock Frequencies): Added tc(SYSCLK) .................................................................... 63
•Table 5-11: Added f(PLLRAWCLK) .................................................................................................... 63
•Table 5-11: Added f(AUXPLLRAWCLK) ................................................................................................ 63
•Table 5-11: Added tc(LSPCLK) ....................................................................................................... 63
•Table 5-11: Added f(HRPWM) ........................................................................................................ 63
•Table 5-11: Removed NOM value of f(LSP), 50 MHz. ........................................................................... 63
•Table 5-11: Combined LSPCLK footnote and default-at-reset footnote. .................................................... 63
•Figure 5-6 (Connecting Input Clocks to a 2837xS Device): Updated figure. ............................................... 64
•Section 5.7.3.4 (Crystal Oscillator): Added section. ........................................................................... 65
•Table 5-14 (Crystal Oscillator Parameters): Added table. .................................................................... 65
•Table 5-15 (Crystal Equivalent Series Resistance (ESR) Requirements): Changed "MAXIMUM ESR (Ω) (CL1/2
= 12 pF)" to "MAXIMUM ESR (Ω) (CL1 = CL2 = 12 pF)"...................................................................... 65
•Table 5-15: Changed "MAXIMUM ESR (Ω) (CL1/2 = 24 pF)" to "MAXIMUM ESR (Ω) (CL1 = CL2 = 24 pF)"......... 65
•Table 5-15: Removed data for CRYSTAL FREQUENCY of 2 MHz, 4 MHz, 6 MHz, and 8 MHz. ....................... 65
•Table 5-16 (Crystal Oscillator Electrical Characteristics): Added table. ..................................................... 65
•Table 5-17 (Internal Oscillator Electrical Characteristics): Frequency accuracy across temperature: Removed
temperature ranges from TEST CONDITIONS. ................................................................................ 66
•Table 5-17: Added tOSCST symbol to "Start-up and settling time". ............................................................ 66
•Section 5.7.4 (Flash Parameters): Changed section title from "Flash Timing" to "Flash Parameters"................... 67
•Table 5-19 (Flash Parameters at 200 MHz): Added table. .................................................................... 67
•Table 5-20 (Flash/OTP Endurance): Added table. ............................................................................. 67
•Table 5-21 (Flash Data Retention Duration): Added table. ................................................................... 67
•Section 5.7.5 (Emulation/JTAG): Added section. .............................................................................. 68
•Section 5.7.6 (GPIO Electrical Data and Timing): Added section. ........................................................... 69
•Figure 5-12 (External and ePIE Interrupt Sources): Updated figure. ........................................................ 72
•Section 5.7.7.1 (External Interrupt Electrical Data and Timing): Added section. ........................................... 73
•Section 5.7.8.3 (Low-Power Mode Wakeup Timing): Added section. ....................................................... 75
•Section 5.7.9 (External Memory Interface): Updated section. ................................................................ 82
•Section 5.7.9.2 (Synchronous DRAM Support): Updated section. ........................................................... 82
•Section 5.7.9.3 (EMIF Electrical Data and Timing): Added section. ......................................................... 83
•Section 5.8 (Analog Peripherals): Changed "each containing a 12-bit reference DAC" to "each containing two
12-bit reference DACs". ........................................................................................................... 90
•Figure 5-24 (Analog Subsystem Block Diagram (337-Ball ZWT)): Updated figure. ....................................... 91
•Figure 5-25 (Analog Subsystem Block Diagram (176-Pin PTP)): Updated figure. ......................................... 92
•Figure 5-26 (Analog Subsystem Block Diagram (100-Pin PZP)): Updated figure. ......................................... 93
•Section 5.8.1 (Analog-to-Digital Converter (ADC)): Updated "The ADCs on this device are successive
approximation (SAR) style ADCs ..." paragraph. ............................................................................... 94
Copyright © 2014–2015, Texas Instruments Incorporated Revision History 7
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