Texas Instruments TMS570LC4357 Product manual

TMS570LC43x 16/32-Bit RISC Flash
Microcontroller
Technical Reference Manual
Literature Number: SPNU563A
March 2018

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Contents
Preface..................................................................................................................................... 104
1 Introduction ..................................................................................................................... 106
1.1 Designed for Safety Applications ....................................................................................... 107
1.2 Family Description........................................................................................................ 108
1.3 Endianism Considerations............................................................................................... 111
1.3.1 TMS570: Big Endian (BE32) ................................................................................... 111
2 Architecture ..................................................................................................................... 112
2.1 Introduction ................................................................................................................ 113
2.1.1 Architecture Block Diagram .................................................................................... 113
2.1.2 Definitions of Terms ............................................................................................. 115
2.1.3 Bus Master / Slave Access Privileges ........................................................................ 118
2.1.4 CPU Interconnect Subsystem SDC MMR Port .............................................................. 118
2.1.5 Interconnect Subsystem Runtime Status..................................................................... 119
2.1.6 Master ID to PCRx............................................................................................... 119
2.2 Memory Organization .................................................................................................... 120
2.2.1 Memory-Map Overview ......................................................................................... 120
2.2.2 Memory-Map Table.............................................................................................. 122
2.2.3 Flash on Microcontrollers....................................................................................... 129
2.2.4 On-Chip SRAM................................................................................................... 134
2.3 Exceptions................................................................................................................. 139
2.3.1 Resets............................................................................................................. 139
2.3.2 Aborts ............................................................................................................. 139
2.3.3 System Software Interrupts..................................................................................... 141
2.4 Clocks ...................................................................................................................... 142
2.4.1 Clock Sources.................................................................................................... 142
2.4.2 Clock Domains................................................................................................... 143
2.4.3 Low Power Modes............................................................................................... 145
2.4.4 Clock Test Mode................................................................................................. 146
2.4.5 Embedded Trace Macrocell (ETM-R5)........................................................................ 148
2.4.6 Safety Considerations for Clocks.............................................................................. 148
2.5 System and Peripheral Control Registers ............................................................................. 151
2.5.1 Primary System Control Registers (SYS) .................................................................... 151
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 205
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 217
3 SCR Control Module (SCM)................................................................................................ 252
3.1 Overview................................................................................................................... 253
3.1.1 Features........................................................................................................... 253
3.1.2 System Block Diagram.......................................................................................... 254
3.2 Module Operation......................................................................................................... 255
3.2.1 Block Diagram.................................................................................................... 255
3.2.2 Timeout Threshold Compare Block ........................................................................... 255
3.2.3 SCM Control Block .............................................................................................. 256
3.3 How to Use SCM ......................................................................................................... 257
3.3.1 How to Check the Parity Compare Logic..................................................................... 257
3.3.2 How to Initiate Self-test Sequence ............................................................................ 258

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3.3.3 How to Configure Timeout Check ............................................................................. 259
3.4 SCM Registers............................................................................................................ 260
3.4.1 SCM REVID Register (SCMREVID)........................................................................... 260
3.4.2 SCM Control Register (SCMCNTRL) ......................................................................... 261
3.4.3 SCM Compare Threshold Counter Register (SCMTHRESHOLD)........................................ 262
3.4.4 SCM Initiator Error0 Status Register (SCMIAERR0STAT)................................................. 263
3.4.5 SCM Initiator Error1 Status Register (SCMIAERR1STAT)................................................. 263
3.4.6 SCM Initiator Active Status Register (SCMIASTAT) ........................................................ 264
3.4.7 SCM Target Active Status Register (SCMTASTAT) ........................................................ 264
4 Interconnect..................................................................................................................... 265
4.1 Overview................................................................................................................... 266
4.1.1 Block Diagram.................................................................................................... 266
4.2 Peripheral Interconnect Subsystem .................................................................................... 266
4.2.1 Accessing PCRx and CRCx Slave ............................................................................ 267
4.2.2 Accessing SDC MMR Port Slave.............................................................................. 267
4.2.3 Accessing Other Slaves via PS_SCR_S ..................................................................... 267
4.3 CPU Interconnect Subsystem........................................................................................... 268
4.3.1 Slave Accessing ................................................................................................. 268
4.3.2 ECC Generation and Evaluation............................................................................... 269
4.3.3 Safety Diagnostic Checker ..................................................................................... 269
4.3.4 Interconnect Self-test............................................................................................ 270
4.3.5 Interconnect Timeout............................................................................................ 270
4.3.6 Interconnect Runtime Status ................................................................................... 271
4.4 SDC MMR Registers ..................................................................................................... 272
4.4.1 SDC Status Register (SDC_STATUS)........................................................................ 273
4.4.2 SDC Control Register (SDC_CONTROL) .................................................................... 274
4.4.3 Error Generic Parity Register (ERR_GENERIC_PARITY) ................................................. 274
4.4.4 Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) ............................... 275
4.4.5 Error Transaction ID Register (ERR_TRANS_ID)........................................................... 275
4.4.6 Error Transaction Signature Register (ERR_TRANS_SIGNATURE)..................................... 276
4.4.7 Error Transaction Type Register (ERR_TRANS_TYPE) ................................................... 276
4.4.8 Error User Parity Register (ERR_USER_PARITY).......................................................... 277
4.4.9 Slave Error Unexpected Master ID Register (SERR_UNEXPECTED_MID)............................. 277
4.4.10 Slave Error Address Decode Register (SERR_ADDR_DECODE)....................................... 278
4.4.11 Slave Error User Parity Register (SERR_USER_PARITY) ............................................... 278
5 Power Management Module (PMM) ..................................................................................... 279
5.1 Overview................................................................................................................... 280
5.1.1 Features........................................................................................................... 280
5.1.2 Block Diagram.................................................................................................... 280
5.2 Power Domains ........................................................................................................... 282
5.3 PMM Operation ........................................................................................................... 283
5.3.1 Power Domain State ............................................................................................ 283
5.3.2 Default Power Domain State................................................................................... 283
5.3.3 Disabling a Power Domain Permanently ..................................................................... 283
5.3.4 Changing Power Domain State................................................................................ 283
5.3.5 Reset Management.............................................................................................. 284
5.3.6 Diagnostic Power State Controller (PSCON) ................................................................ 284
5.3.7 PSCON Compare Block ........................................................................................ 284
5.4 PMM Registers............................................................................................................ 285
5.4.1 Logic Power Domain Control Register (LOGICPDPWRCTRL0) .......................................... 286
5.4.2 Logic Power Domain Control Register (LOGICPDPWRCTRL1) .......................................... 287
5.4.3 Power Domain Clock Disable Register (PDCLKDISREG) ................................................. 288
5.4.4 Power Domain Clock Disable Set Register (PDCLKDISSETREG) ...................................... 289

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5.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)..................................... 290
5.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0)............................. 291
5.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1)............................. 292
5.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2)............................. 293
5.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3)............................. 294
5.4.10 Logic Power Domain PD6 Power Status Register (LOGICPDPWRSTAT4)............................ 295
5.4.11 Global Control Register 1 (GLOBALCTRL1)................................................................ 296
5.4.12 Global Status Register (GLOBALSTAT)..................................................................... 297
5.4.13 PSCON Diagnostic Compare Key Register (PRCKEYREG) ............................................. 297
5.4.14 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)............................. 298
5.4.15 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)............................. 299
5.4.16 Isolation Diagnostic Status Register (ISODIAGSTAT)..................................................... 300
6 I/O Multiplexing and Control Module (IOMM) ........................................................................ 301
6.1 Overview .................................................................................................................. 302
6.2 Main Features of I/O Multiplexing Module (IOMM)................................................................... 302
6.3 Control of Multiplexed Outputs.......................................................................................... 302
6.4 Control of Multiplexed Inputs............................................................................................ 303
6.5 Control of Special Multiplexed Options ................................................................................ 312
6.5.1 Control of SDRAM Clock (EMIF_CLK)........................................................................ 314
6.5.2 Control for other EMIF Outputs ................................................................................ 314
6.5.3 Control of Ethernet Controller Mode .......................................................................... 314
6.5.4 Control of ADC Trigger Events................................................................................. 314
6.5.5 Control for ADC Event Trigger Signal Generation from ePWMx Modules ............................... 315
6.5.6 Control for Generating Interrupt Upon External Fault Indication to N2HETx ............................ 318
6.5.7 Control for Synchronizing Time Bases for All ePWMx Modules........................................... 320
6.5.8 Control for Synchronizing all ePWMx Modules to N2HET1 Module Time-Base ........................ 320
6.5.9 Control for Input Connections to ePWMx Modules.......................................................... 321
6.5.10 Control for Input Connections to eCAPx Modules.......................................................... 322
6.5.11 Control for Input Connections to eQEPx Modules.......................................................... 323
6.5.12 Selecting GIO Port for External DMA Request ............................................................. 325
6.5.13 Temperature Sensor Selection ............................................................................... 326
6.6 Safety Features ........................................................................................................... 327
6.6.1 Locking Mechanism for Memory-Mapped Registers........................................................ 327
6.6.2 Error Conditions.................................................................................................. 327
6.7 IOMM Registers........................................................................................................... 328
6.7.1 REVISION_REG: Revision Register .......................................................................... 328
6.7.2 BOOT_REG: Boot Mode Register............................................................................. 329
6.7.3 KICK_REG0: Kicker Register 0................................................................................ 330
6.7.4 KICK_REG1: Kicker Register 1................................................................................ 330
6.7.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register............................................. 331
6.7.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register................................ 332
6.7.7 ERR_ENABLE_REG: Error Signaling Enable Register..................................................... 333
6.7.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register ...................................... 334
6.7.9 FAULT_ADDRESS_REG: Fault Address Register.......................................................... 334
6.7.10 FAULT_STATUS_REG: Fault Status Register ............................................................. 335
6.7.11 FAULT_CLEAR_REG: Fault Clear Register ................................................................ 336
6.7.12 PINMMRnn: Output Pin Multiplexing Control Registers ................................................... 336
6.7.13 PINMMRnn: Input Pin Multiplexing Control Registers ..................................................... 337
6.7.14 PINMMRnn: Special Functionality Multiplexing Control Registers ....................................... 337
7 F021 Level 2 Flash Module Controller (L2FMC)..................................................................... 338
7.1 Overview................................................................................................................... 339
7.1.1 Features........................................................................................................... 339
7.1.2 Definition of Terms............................................................................................... 339

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7.1.3 F021 Flash Tools ................................................................................................ 340
7.2 Default Flash Configuration ............................................................................................. 340
7.3 EEPROM Emulation Support............................................................................................ 340
7.4 SECDED................................................................................................................... 341
7.4.1 SECDED Initialization ........................................................................................... 341
7.4.2 ECC Encoding.................................................................................................... 341
7.4.3 Syndrome Table: Decode to Bit in Error...................................................................... 343
7.4.4 Syndrome Table: An Alternate Method ....................................................................... 344
7.5 Memory Map .............................................................................................................. 345
7.5.1 Location of Flash ECC Bits..................................................................................... 345
7.5.2 OTP Memory ..................................................................................................... 346
7.6 Power On, Power Off Considerations.................................................................................. 350
7.6.1 Error Checking at Power On ................................................................................... 350
7.6.2 Flash Integrity at Power Off .................................................................................... 350
7.7 Emulation and SIL3 Diagnostic Modes ................................................................................ 350
7.7.1 System Emulation ............................................................................................... 350
7.7.2 Diagnostic Mode ................................................................................................. 350
7.7.3 Diagnostic Mode Summary..................................................................................... 352
7.7.4 SECDED Software Diagnostic ................................................................................. 353
7.7.5 Read Margin...................................................................................................... 353
7.8 Parameter Overlay Module (POM) ..................................................................................... 353
7.8.1 Example Procedure to Configure the POM .................................................................. 353
7.9 Summary of L2FMC Errors.............................................................................................. 354
7.10 Flash Control Registers.................................................................................................. 355
7.10.1 Flash Read Control Register (FRDCNTL)................................................................... 356
7.10.2 Read Margin Control Register (FSPRD)..................................................................... 357
7.10.3 EEPROM Error Correction Control Register (EE_FEDACCTRL1)....................................... 358
7.10.4 Flash Port A Error and Status Register (FEDAC_PASTATUS) .......................................... 359
7.10.5 Flash Port B Error and Status Register (FEDAC_PBSTATUS) .......................................... 360
7.10.6 Flash Global Error and Status Register (FEDAC_GBLSTATUS) ........................................ 361
7.10.7 Flash Error Detection and Correction Sector Disable Register (FEDACSDIS)......................... 362
7.10.8 Primary Address Tag Register (FPRIM_ADD_TAG)....................................................... 363
7.10.9 Duplicate Address Tag Register (FDUP_ADD_TAG)...................................................... 363
7.10.10 Flash Bank Protection Register (FBPROT)................................................................ 364
7.10.11 Flash Bank Sector Enable Register (FBSE)............................................................... 364
7.10.12 Flash Bank Busy Register (FBBUSY)...................................................................... 365
7.10.13 Flash Bank Access Control Register (FBAC) ............................................................. 365
7.10.14 Flash Bank Power Mode Register (FBPWRMODE) ..................................................... 366
7.10.15 Flash Bank/Pump Ready Register (FBPRDY) ............................................................ 367
7.10.16 Flash Pump Access Control Register 1 (FPAC1)......................................................... 368
7.10.17 Flash Module Access Control Register (FMAC) .......................................................... 369
7.10.18 Flash Module Status Register (FMSTAT).................................................................. 370
7.10.19 EEPROM Emulation Data MSW Register (FEMU_DMSW) ............................................. 372
7.10.20 EEPROM Emulation Data LSW Register (FEMU_DLSW)............................................... 372
7.10.21 EEPROM Emulation ECC Register (FEMU_ECC) ....................................................... 373
7.10.22 Flash Lock Register (FLOCK) ............................................................................... 373
7.10.23 Diagnostic Control Register (FDIAGCTRL)................................................................ 374
7.10.24 Raw Address Register (FRAW_ADDR) ................................................................... 375
7.10.25 Parity Override Register (FPAR_OVR)..................................................................... 376
7.10.26 Reset Configuration Valid Register (RCR_VALID) ....................................................... 377
7.10.27 Crossbar Access Time Threshold Register (ACC_THRESHOLD) ..................................... 377
7.10.28 Flash Error Detection and Correction Sector Disable Register 2 (FEDACSDIS2) ................... 378
7.10.29 Lower Word of Reset Configuration Read Register (RCR_VALUE0).................................. 379

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7.10.30 Upper Word of Reset Configuration Read Register (RCR_VALUE1).................................. 379
7.10.31 FSM Register Write Enable Register (FSM_WR_ENA).................................................. 380
7.10.32 EEPROM Emulation Configuration Register (EEPROM_CONFIG) .................................... 380
7.10.33 FSM Sector Register 1 (FSM_SECTOR1)................................................................. 381
7.10.34 FSM Sector Register 2 (FSM_SECTOR2)................................................................. 381
7.10.35 Flash Bank Configuration Register (FCFG_BANK)....................................................... 382
7.11 POM Control Registers .................................................................................................. 383
7.11.1 POM Global Control Register (POMGLBCTRL)............................................................ 383
7.11.2 POM Revision ID Register (POMREV) ...................................................................... 384
7.11.3 POM Flag Register (POMFLG) ............................................................................... 384
7.11.4 POM Region Start Address Register (POMPROGSTARTx).............................................. 385
7.11.5 POM Overlay Region Start Address Register (POMOVLSTARTx) ...................................... 385
7.11.6 POM Region Size Register (POMREGSIZEx).............................................................. 386
8 Level 2 RAM (L2RAMW) Module ......................................................................................... 387
8.1 Overview................................................................................................................... 388
8.2 Module Operation......................................................................................................... 388
8.2.1 RAM Memory Map............................................................................................... 388
8.2.2 Safety Features .................................................................................................. 389
8.2.3 L2RAMW Auto-Initialization .................................................................................... 392
8.2.4 Trace Module Support .......................................................................................... 392
8.2.5 Emulation/Debug Mode Behavior.............................................................................. 392
8.2.6 Diagnostic Test Procedure ..................................................................................... 392
8.3 Control and Status Registers............................................................................................ 393
8.3.1 L2RAMW Module Control Register (RAMCTRL)............................................................ 393
8.3.2 L2RAMW Error Status Register (RAMERRSTATUS)....................................................... 395
8.3.3 L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H).......................... 398
8.3.4 L2RAMW Diagnostic Data Vector Low Register (DIAG_DATA_VECTOR_L)........................... 398
8.3.5 L2RAMW Diagnostic ECC Vector Register (DIAG_ECC).................................................. 399
8.3.6 L2RAMW RAM Test Mode Control Register (RAMTEST) ................................................. 400
8.3.7 L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT)...................... 401
8.3.8 L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN)................................. 402
8.3.9 L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0)............................... 403
8.3.10 L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1).............................. 404
9 Programmable Built-In Self-Test (PBIST) Module.................................................................. 405
9.1 Overview................................................................................................................... 406
9.1.1 Features of PBIST............................................................................................... 406
9.1.2 PBIST vs. Application Software-Based Testing.............................................................. 406
9.1.3 PBIST Block Diagram........................................................................................... 406
9.2 RAM Grouping and Algorithm........................................................................................... 407
9.3 PBIST Flow................................................................................................................ 408
9.3.1 PBIST Sequence................................................................................................. 409
9.4 Memory Test Algorithms on the On-chip ROM ...................................................................... 411
9.5 PBIST Control Registers ................................................................................................ 412
9.5.1 RAM Configuration Register (RAMT) ......................................................................... 413
9.5.2 Datalogger Register (DLR) ..................................................................................... 414
9.5.3 PBIST Activate/Clock Enable Register (PACT).............................................................. 415
9.5.4 PBIST ID Register ............................................................................................... 416
9.5.5 Override Register (OVER)...................................................................................... 417
9.5.6 Fail Status Fail Register (FSRF0) ............................................................................. 418
9.5.7 Fail Status Count Registers (FSRC0 and FSRC1).......................................................... 419
9.5.8 Fail Status Address Registers (FSRA0 and FSRA1) ....................................................... 420
9.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ........................................................ 421
9.5.10 ROM Mask Register (ROM)................................................................................... 422

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9.5.11 ROM Algorithm Mask Register (ALGO) ..................................................................... 423
9.5.12 RAM Info Mask Lower Register (RINFOL) .................................................................. 424
9.5.13 RAM Info Mask Upper Register (RINFOU).................................................................. 425
9.6 PBIST Configuration Example .......................................................................................... 426
9.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM..................... 426
9.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups................ 427
10 Self-Test Controller (STC) Module....................................................................................... 428
10.1 General Description ...................................................................................................... 429
10.1.1 Self-Test Controller Features ................................................................................. 429
10.1.2 Terminology ..................................................................................................... 430
10.1.3 STC Block Diagram ............................................................................................ 430
10.2 STC Module Assignments............................................................................................... 436
10.3 STC Programmers Flow ................................................................................................. 437
10.4 Application Self-Test Flow............................................................................................... 438
10.4.1 STC Module Configuration .................................................................................... 438
10.4.2 Context Saving - CPU.......................................................................................... 438
10.4.3 Entering CPU Idle Mode....................................................................................... 439
10.4.4 Entering nHET Idle Mode...................................................................................... 439
10.4.5 Self-Test Completion and Error Generation................................................................. 439
10.5 STC1 Segment 0 (CPU) Test Coverage and Duration .............................................................. 441
10.6 STC1 Segment 1 (µSCU) Test Coverage and Duration............................................................. 444
10.7 STC2 (nHET) Test Coverage and Duration........................................................................... 444
10.8 STC Control Registers ................................................................................................... 446
10.8.1 STC Global Control Register 0 (STCGCR0)................................................................ 447
10.8.2 STC Global Control Register 1 (STCGCR1)................................................................ 448
10.8.3 Self-Test Run Timeout Counter Preload Register (STCTPR) ............................................ 449
10.8.4 STC Current ROM Address Register - CORE1 (STCCADDR1) ......................................... 450
10.8.5 STC Current Interval Count Register (STCCICR).......................................................... 450
10.8.6 Self-Test Global Status Register (STCGSTAT) ............................................................ 451
10.8.7 Self-Test Fail Status Register (STCFSTAT) ................................................................ 452
10.8.8 CORE1 Current MISR Registers (CORE1_CURMISR[3:0]) .............................................. 453
10.8.9 CORE2 Current MISR Registers (CORE2_CURMISR[3:0]) .............................................. 454
10.8.10 Signature Compare Self-Check Register (STCSCSCR)................................................. 455
10.8.11 STC Current ROM Address Register - CORE2 (STCCADDR2)........................................ 455
10.8.12 STC Clock Prescalar Register (STCCLKDIV)............................................................. 456
10.8.13 Segment Interval Preload Register (STCSEGPLR) ...................................................... 457
10.9 STC Configuration Example............................................................................................. 458
10.9.1 Example: STC1 Self-Test Run................................................................................ 458
10.10 Self-Test Controller Diagnostics........................................................................................ 459
11 System Memory Protection Unit (NMPU).............................................................................. 460
11.1 Overview................................................................................................................... 461
11.1.1 Features.......................................................................................................... 461
11.1.2 Safety Diagnostic ............................................................................................... 461
11.1.3 Block Diagram................................................................................................... 462
11.2 Module Operation......................................................................................................... 463
11.2.1 Functional Mode ................................................................................................ 463
11.2.2 Diagnostic Mode................................................................................................ 465
11.2.3 Functional Fail Safe ............................................................................................ 465
11.3 How to Use NMPU ....................................................................................................... 466
11.3.1 How to Use NMPU in Functional Mode...................................................................... 466
11.3.2 How to Use Diagnostics ....................................................................................... 468
11.4 NMPU Registers .......................................................................................................... 471
11.4.1 MPU Revision ID Register (MPUREV)....................................................................... 472

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11.4.2 MPU Lock Register (MPULOCK)............................................................................. 472
11.4.3 MPU Diagnostics Control Register (MPUDIAGCTRL)..................................................... 473
11.4.4 MPU Diagnostic Address Register (MPUDIAGADDR) .................................................... 474
11.4.5 MPU Error Status Register (MPUERRSTAT)............................................................... 474
11.4.6 MPU Error Address Register (MPUERRADDR)............................................................ 476
11.4.7 MPU Control Register 1 (MPUCTRL1) ...................................................................... 476
11.4.8 MPU Control Register 2 (MPUCTRL2) ...................................................................... 477
11.4.9 MPU Type Register (MPUTYPE)............................................................................. 478
11.4.10 MPU Region Base Address Register (MPUREGBASE) ................................................. 479
11.4.11 MPU Region Size and Enable Register (MPUREGSENA) .............................................. 479
11.4.12 MPU Region Access Control Register (MPUREGACR) ................................................. 481
11.4.13 MPU Region Number Register (MPUREGNUM) ......................................................... 482
12 Error Profiling Controller (EPC).......................................................................................... 483
12.1 Overview................................................................................................................... 484
12.2 Module Operation......................................................................................................... 484
12.2.1 Uncorrectable Fault Operation................................................................................ 485
12.2.2 Correctable Fault Operation................................................................................... 485
12.3 How to Use EPC.......................................................................................................... 487
12.3.1 Functional Mode ................................................................................................ 487
12.3.2 CAM Diagnostic Mode ......................................................................................... 488
12.4 EPC Control Registers................................................................................................... 488
12.4.1 EPC REVID Register (EPCREVID) .......................................................................... 489
12.4.2 EPC Control Register (EPCCNTRL) ......................................................................... 490
12.4.3 Uncorrectable Error Status Register (UERRSTAT) ........................................................ 491
12.4.4 EPC Error Status Register (EPCERRSTAT)................................................................ 492
12.4.5 FIFO Full Status Register (FIFOFULLSTAT) ............................................................... 493
12.4.6 IP Interface FIFO Overflow Status Register (OVRFLWSTAT)............................................ 494
12.4.7 CAM Index Available Status Register (CAMAVAILSTAT)................................................. 494
12.4.8 Uncorrectable Error Address Register n (UERR_ADDR) ................................................. 495
12.4.9 CAM Content Update Register n (CAM_CONTENT) ...................................................... 495
12.4.10 CAM Index Registers (CAM_INDEX[0-7]) ................................................................. 496
13 CPU Compare Module for Cortex-R5F (CCM-R5F)................................................................. 497
13.1 Overview................................................................................................................... 498
13.1.1 Main Features................................................................................................... 498
13.1.2 Block Diagram................................................................................................... 498
13.2 Module Operation......................................................................................................... 499
13.2.1 CPU/VIM Output Compare Diagnostic....................................................................... 500
13.2.2 CPU Input Inversion Diagnostic............................................................................... 504
13.2.3 Checker CPU Inactivity Monitor............................................................................... 505
13.2.4 Power Domain Inactivity Monitor ............................................................................. 507
13.2.5 Operation During CPU Debug Mode......................................................................... 507
13.3 Control Registers ......................................................................................................... 507
13.3.1 CCM-R5F Status Register 1 (CCMSR1) .................................................................... 508
13.3.2 CCM-R5F Key Register 1 (CCMKEYR1).................................................................... 509
13.3.3 CCM-R5F Status Register 2 (CCMSR2) .................................................................... 510
13.3.4 CCM-R5F Key Register 2 (CCMKEYR2).................................................................... 511
13.3.5 CCM-R5F Status Register 3 (CCMSR3) .................................................................... 512
13.3.6 CCM-R5F Key Register 3 (CCMKEYR3).................................................................... 513
13.3.7 CCM-R5F Polarity Control Register (CCMPOLCNTRL)................................................... 513
13.3.8 CCM-R5F Status Register 4 (CCMSR4) .................................................................... 514
13.3.9 CCM-R5F Key Register 4 (CCMKEYR4).................................................................... 515
13.3.10 CCM-R5F Power Domain Status Register 0 (CCMPDSTAT0) ......................................... 516
14 Oscillator and PLL ............................................................................................................ 517

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14.1 Introduction ................................................................................................................ 518
14.1.1 Features.......................................................................................................... 518
14.2 Quick Start................................................................................................................. 519
14.3 Oscillator................................................................................................................... 520
14.3.1 Oscillator Implementation...................................................................................... 521
14.3.2 Oscillator Enable................................................................................................ 521
14.3.3 Oscillator Disable ............................................................................................... 521
14.4 Low Power Oscillator and Clock Detect (LPOCLKDET)............................................................. 522
14.4.1 Clock Detect..................................................................................................... 522
14.4.2 Behavior on Oscillator Failure................................................................................. 522
14.4.3 Recovery from Oscillator Failure ............................................................................. 523
14.4.4 LPOCLKDET Enable........................................................................................... 523
14.4.5 LPOCLKDET Disable .......................................................................................... 524
14.4.6 Trimming the HF LPO Oscillator.............................................................................. 524
14.5 PLL ......................................................................................................................... 525
14.5.1 Modulation....................................................................................................... 527
14.5.2 PLL Output Control............................................................................................. 528
14.5.3 Behavior on PLL Fail........................................................................................... 531
14.5.4 Recovery from a PLL Failure.................................................................................. 532
14.5.5 PLL Modulation Depth Measurement........................................................................ 533
14.5.6 PLL Frequency Measurement Circuit ........................................................................ 533
14.5.7 PLL2.............................................................................................................. 533
14.6 PLL Control Registers.................................................................................................... 534
14.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)..................................... 535
14.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)............................................................ 536
14.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)............................................................ 537
14.7 Phase-Locked Loop Theory of Operation ............................................................................. 538
14.7.1 Phase-Frequency Detector.................................................................................... 538
14.7.2 Charge Pump and Loop Filter................................................................................. 539
14.7.3 Voltage-Controlled Oscillator.................................................................................. 539
14.7.4 Frequency Modulation ......................................................................................... 540
14.8 Programming Example................................................................................................... 540
15 Dual-Clock Comparator (DCC) Module ................................................................................ 542
15.1 Introduction ................................................................................................................ 543
15.1.1 Main Features................................................................................................... 543
15.1.2 Block Diagram................................................................................................... 543
15.2 Module Operation......................................................................................................... 544
15.2.1 Continuous Monitoring Mode.................................................................................. 544
15.2.2 Single-Shot Measurement Mode ............................................................................. 547
15.3 Clock Source Selection for Counter0 and Counter1 ................................................................. 548
15.4 DCC Control Registers................................................................................................... 549
15.4.1 DCC Global Control Register (DCCGCTRL) ............................................................... 550
15.4.2 DCC Revision Id Register (DCCREV) ...................................................................... 551
15.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) ......................................................... 551
15.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) .......................................................... 552
15.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) ......................................................... 552
15.4.6 DCC Status Register (DCCSTAT) ........................................................................... 553
15.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................ 554
15.4.8 DCC Valid0 Value Register (DCCVALID0) ................................................................. 555
15.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................ 555
15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) .............................. 556
15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) .............................. 557
16 Error Signaling Module (ESM) ............................................................................................ 558

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16.1 Overview................................................................................................................... 559
16.1.1 Feature List...................................................................................................... 559
16.1.2 Block Diagram................................................................................................... 559
16.2 Module Operation......................................................................................................... 561
16.2.1 Reset Behavior.................................................................................................. 561
16.2.2 ERROR Pin Timing............................................................................................. 562
16.2.3 Forcing an Error Condition .................................................................................... 563
16.3 Recommended Programming Procedure.............................................................................. 564
16.4 ESM Control Registers................................................................................................... 565
16.4.1 ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1)............................... 566
16.4.2 ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1).............................. 566
16.4.3 ESM Interrupt Enable Set/Status Register 1 (ESMIESR1)................................................ 567
16.4.4 ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1)............................................. 567
16.4.5 ESM Interrupt Level Set/Status Register 1 (ESMILSR1).................................................. 568
16.4.6 ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) ............................................... 568
16.4.7 ESM Status Register 1 (ESMSR1)........................................................................... 569
16.4.8 ESM Status Register 2 (ESMSR2)........................................................................... 569
16.4.9 ESM Status Register 3 (ESMSR3)........................................................................... 570
16.4.10 ESM ERROR Pin Status Register (ESMEPSR) .......................................................... 570
16.4.11 ESM Interrupt Offset High Register (ESMIOFFHR) ...................................................... 571
16.4.12 ESM Interrupt Offset Low Register (ESMIOFFLR) ....................................................... 572
16.4.13 ESM Low-Time Counter Register (ESMLTCR) ........................................................... 573
16.4.14 ESM Low-Time Counter Preload Register (ESMLTCPR)................................................ 573
16.4.15 ESM Error Key Register (ESMEKR)........................................................................ 574
16.4.16 ESM Status Shadow Register 2 (ESMSSR2) ............................................................. 574
16.4.17 ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) ..................................... 575
16.4.18 ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) .................................. 575
16.4.19 ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) ............................................. 576
16.4.20 ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) ........................................... 576
16.4.21 ESM Interrupt Level Set/Status Register 4 (ESMILSR4) ................................................ 577
16.4.22 ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) ............................................. 577
16.4.23 ESM Status Register 4 (ESMSR4) ......................................................................... 578
16.4.24 ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) ..................................... 579
16.4.25 ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) .................................. 579
16.4.26 ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) ............................................. 580
16.4.27 ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) ........................................... 580
16.4.28 ESM Interrupt Level Set/Status Register 7 (ESMILSR7) ................................................ 581
16.4.29 ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) ............................................. 581
16.4.30 ESM Status Register 7 (ESMSR7) ......................................................................... 582
17 Real-Time Interrupt (RTI) Module........................................................................................ 583
17.1 Overview................................................................................................................... 584
17.1.1 Features.......................................................................................................... 584
17.1.2 Industry Standard Compliance Statement................................................................... 584
17.2 Module Operation......................................................................................................... 585
17.2.1 Counter Operation.............................................................................................. 585
17.2.2 Interrupt/DMA Requests ....................................................................................... 587
17.2.3 RTI Clocking..................................................................................................... 588
17.2.4 Synchronizing Timer Events to Network Time (NTU)...................................................... 588
17.2.5 Digital Watchdog (DWD)....................................................................................... 591
17.2.6 Low Power Modes.............................................................................................. 594
17.2.7 Halting Debug Mode Behaviour............................................................................... 594
17.3 RTI Control Registers .................................................................................................... 595
17.3.1 RTI Global Control Register (RTIGCTRL)................................................................... 596

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17.3.2 RTI Timebase Control Register (RTITBCTRL) ............................................................. 597
17.3.3 RTI Capture Control Register (RTICAPCTRL).............................................................. 598
17.3.4 RTI Compare Control Register (RTICOMPCTRL) ......................................................... 599
17.3.5 RTI Free Running Counter 0 Register (RTIFRC0) ......................................................... 600
17.3.6 RTI Up Counter 0 Register (RTIUC0)........................................................................ 600
17.3.7 RTI Compare Up Counter 0 Register (RTICPUC0)........................................................ 601
17.3.8 RTI Capture Free Running Counter 0 Register (RTICAFRC0)........................................... 601
17.3.9 RTI Capture Up Counter 0 Register (RTICAUC0).......................................................... 602
17.3.10 RTI Free Running Counter 1 Register (RTIFRC1)........................................................ 602
17.3.11 RTI Up Counter 1 Register (RTIUC1) ...................................................................... 603
17.3.12 RTI Compare Up Counter 1 Register (RTICPUC1)....................................................... 604
17.3.13 RTI Capture Free Running Counter 1 Register (RTICAFRC1) ......................................... 605
17.3.14 RTI Capture Up Counter 1 Register (RTICAUC1)........................................................ 605
17.3.15 RTI Compare 0 Register (RTICOMP0)..................................................................... 606
17.3.16 RTI Update Compare 0 Register (RTIUDCP0)............................................................ 606
17.3.17 RTI Compare 1 Register (RTICOMP1)..................................................................... 607
17.3.18 RTI Update Compare 1 Register (RTIUDCP1)............................................................ 607
17.3.19 RTI Compare 2 Register (RTICOMP2)..................................................................... 608
17.3.20 RTI Update Compare 2 Register (RTIUDCP2)............................................................ 608
17.3.21 RTI Compare 3 Register (RTICOMP3)..................................................................... 609
17.3.22 RTI Update Compare 3 Register (RTIUDCP3)............................................................ 609
17.3.23 RTI Timebase Low Compare Register (RTITBLCOMP) ................................................. 610
17.3.24 RTI Timebase High Compare Register (RTITBHCOMP) ................................................ 610
17.3.25 RTI Set Interrupt Enable Register (RTISETINTENA) .................................................... 611
17.3.26 RTI Clear Interrupt Enable Register (RTICLEARINTENA) .............................................. 613
17.3.27 RTI Interrupt Flag Register (RTIINTFLAG) ................................................................ 615
17.3.28 Digital Watchdog Control Register (RTIDWDCTRL) ..................................................... 616
17.3.29 Digital Watchdog Preload Register (RTIDWDPRLD)..................................................... 617
17.3.30 Watchdog Status Register (RTIWDSTATUS) ............................................................. 618
17.3.31 RTI Watchdog Key Register (RTIWDKEY) ................................................................ 619
17.3.32 RTI Digital Watchdog Down Counter (RTIDWDCNTR) .................................................. 620
17.3.33 Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) ................................. 620
17.3.34 Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL)............................ 621
17.3.35 RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE)................................. 622
17.3.36 RTI Compare 0 Clear Register (RTICMP0CLR) .......................................................... 623
17.3.37 RTI Compare 1 Clear Register (RTICMP1CLR) .......................................................... 623
17.3.38 RTI Compare 2 Clear Register (RTICMP2CLR) .......................................................... 624
17.3.39 RTI Compare 3 Clear Register (RTICMP3CLR) .......................................................... 624
18 Cyclic Redundancy Check (CRC) Controller Module ............................................................. 625
18.1 Overview................................................................................................................... 626
18.1.1 Features.......................................................................................................... 626
18.1.2 Block Diagram................................................................................................... 626
18.2 Module Operation......................................................................................................... 628
18.2.1 General Operation.............................................................................................. 628
18.2.2 CRC Modes of Operation...................................................................................... 628
18.2.3 PSA Signature Register........................................................................................ 629
18.2.4 PSA Sector Signature Register............................................................................... 630
18.2.5 CRC Value Register............................................................................................ 631
18.2.6 Raw Data Register ............................................................................................. 631
18.2.7 Example DMA Controller Setup............................................................................... 631
18.2.8 Pattern Count Register......................................................................................... 633
18.2.9 Sector Count Register/Current Sector Register ............................................................ 633
18.2.10 Interrupt......................................................................................................... 634

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18.2.11 Power Down Mode............................................................................................ 637
18.2.12 Emulation....................................................................................................... 637
18.2.13 Peripheral Bus Interface...................................................................................... 638
18.3 Example.................................................................................................................... 638
18.3.1 Example: Auto Mode Using Time Based Event Triggering ............................................... 638
18.3.2 Example: Auto Mode Without Using Time Based Triggering ............................................. 639
18.3.3 Example: Semi-CPU Mode.................................................................................... 640
18.3.4 Example: Full-CPU Mode...................................................................................... 640
18.4 CRC Control Registers................................................................................................... 641
18.4.1 CRC Global Control Register 0 (CRC_CTRL0)............................................................. 642
18.4.2 CRC Global Control Register (CRC_CTRL1)............................................................... 642
18.4.3 CRC Global Control Register 2 (CRC_CTRL2)............................................................. 643
18.4.4 CRC Interrupt Enable Set Register (CRC_INTS) .......................................................... 644
18.4.5 CRC Interrupt Enable Reset Register (CRC_INTR) ....................................................... 646
18.4.6 CRC Interrupt Status Register (CRC_STATUS)............................................................ 648
18.4.7 CRC Interrupt Offset (CRC_INT_OFFSET_REG).......................................................... 650
18.4.8 CRC Busy Register (CRC_BUSY) ........................................................................... 651
18.4.9 CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)..................................... 651
18.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) .................................... 652
18.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1) ............................................... 652
18.4.12 CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1)........................ 653
18.4.13 CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1).................. 653
18.4.14 Channel 1 PSA Signature Low Register (PSA_SIGREGL1) ............................................ 654
18.4.15 Channel 1 PSA Signature High Register (PSA_SIGREGH1) ........................................... 654
18.4.16 Channel 1 CRC Value Low Register (CRC_REGL1)..................................................... 654
18.4.17 Channel 1 CRC Value High Register (CRC_REGH1).................................................... 655
18.4.18 Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1).............................. 655
18.4.19 Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)............................. 655
18.4.20 Channel 1 Raw Data Low Register (RAW_DATAREGL1)............................................... 656
18.4.21 Channel 1 Raw Data High Register (RAW_DATAREGH1).............................................. 656
18.4.22 CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) ................................... 656
18.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) .................................... 657
18.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2) ............................................... 657
18.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)........................ 658
18.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2).................. 658
18.4.27 Channel 2 PSA Signature Low Register (PSA_SIGREGL2) ............................................ 659
18.4.28 Channel 2 PSA Signature High Register (PSA_SIGREGH2) ........................................... 659
18.4.29 Channel 2 CRC Value Low Register (CRC_REGL2)..................................................... 659
18.4.30 Channel 2 CRC Value High Register (CRC_REGH2).................................................... 660
18.4.31 Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2).............................. 660
18.4.32 Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)............................. 660
18.4.33 Channel 2 Raw Data Low Register (RAW_DATAREGL2)............................................... 661
18.4.34 Channel 2 Raw Data High Register (RAW_DATAREGH2).............................................. 661
19 Vectored Interrupt Manager (VIM) Module............................................................................ 662
19.1 Overview................................................................................................................... 663
19.2 Dual VIM for Safety....................................................................................................... 664
19.3 Device Level Interrupt Management ................................................................................... 665
19.3.1 Interrupt Generation at the Peripheral ....................................................................... 665
19.3.2 Interrupt Handling at the CPU................................................................................. 666
19.3.3 Software Interrupt Handling Options ......................................................................... 667
19.4 Interrupt Handling Inside VIM ........................................................................................... 668
19.4.1 VIM Interrupt Channel Mapping............................................................................... 669
19.4.2 VIM Input Channel Management ............................................................................. 671

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19.5 Interrupt Vector Table (VIM RAM)...................................................................................... 672
19.5.1 Interrupt Vector Table Operation ............................................................................. 672
19.5.2 VIM ECC Syndrome............................................................................................ 673
19.5.3 Interrupt Vector Table Initialization........................................................................... 674
19.5.4 Interrupt Vector Table ECC Testing.......................................................................... 674
19.6 VIM Wakeup Interrupt.................................................................................................... 676
19.7 Capture Event Sources .................................................................................................. 677
19.8 Examples .................................................................................................................. 677
19.8.1 Examples - Configure CPU To Receive Interrupts......................................................... 677
19.8.2 Examples - Register Vector Interrupt and Index Interrupt Handling ..................................... 678
19.9 VIM Control Registers.................................................................................................... 680
19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT) ................................................ 681
19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL).................................................. 682
19.9.3 Uncorrectable Error Address Register (UERRADDR) ..................................................... 683
19.9.4 Fallback Vector Address Register (FBVECADDR)......................................................... 683
19.9.5 Single-Bit Error Address Register (SBERRADDR)......................................................... 684
19.9.6 VIM Offset Vector Registers................................................................................... 684
19.9.7 IRQ Index Offset Vector Register (IRQINDEX)............................................................. 685
19.9.8 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................ 685
19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3]) ....................................................... 686
19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3]) ............................................. 687
19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])...................................................... 688
19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3]) ................................................... 689
19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])................................................... 690
19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3])................................................ 691
19.9.15 IRQ Interrupt Vector Register (IRQVECREG)............................................................. 692
19.9.16 FIQ Interrupt Vector Register (FIQVECREG) ............................................................. 692
19.9.17 Capture Event Register (CAPEVT) ......................................................................... 693
19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31]) ..................................................... 694
20 Direct Memory Access Controller (DMA) Module .................................................................. 696
20.1 Overview................................................................................................................... 697
20.1.1 Main Features................................................................................................... 697
20.1.2 System Resources Mapping .................................................................................. 699
20.2 Module Operation......................................................................................................... 699
20.2.1 Memory Space.................................................................................................. 700
20.2.2 DMA Data Access .............................................................................................. 700
20.2.3 Addressing Modes.............................................................................................. 701
20.2.4 DMA Channel Control Packets ............................................................................... 701
20.2.5 Priority Queue................................................................................................... 705
20.2.6 Data Packing and Unpacking ................................................................................. 707
20.2.7 DMA Request ................................................................................................... 710
20.2.8 Auto-Initiation.................................................................................................... 712
20.2.9 Interrupts......................................................................................................... 712
20.2.10 Debugging...................................................................................................... 714
20.2.11 Power Management .......................................................................................... 714
20.2.12 FIFO Buffer..................................................................................................... 715
20.2.13 Channel Chaining ............................................................................................. 716
20.2.14 Request Polarity............................................................................................... 716
20.2.15 Memory Protection............................................................................................ 717
20.2.16 ECC Checking................................................................................................. 718
20.2.17 ECC Testing ................................................................................................... 719
20.2.18 Initializing RAM with ECC.................................................................................... 719
20.2.19 Transaction Errors ............................................................................................ 720

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20.3 Control Registers and Control Packets ................................................................................ 721
20.3.1 Global Configuration Registers ............................................................................... 724
20.3.2 Channel Configuration ......................................................................................... 788
21 External Memory Interface (EMIF)....................................................................................... 793
21.1 Introduction ................................................................................................................ 794
21.1.1 Purpose of the Peripheral ..................................................................................... 794
21.1.2 Features.......................................................................................................... 794
21.1.3 Functional Block Diagram ..................................................................................... 795
21.2 EMIF Module Architecture............................................................................................... 796
21.2.1 EMIF Clock Control............................................................................................. 796
21.2.2 EMIF Requests.................................................................................................. 796
21.2.3 EMIF Signal Descriptions...................................................................................... 796
21.2.4 EMIF Signal Multiplexing Control............................................................................. 797
21.2.5 SDRAM Controller and Interface ............................................................................. 798
21.2.6 Asynchronous Controller and Interface...................................................................... 810
21.2.7 Data Bus Parking............................................................................................... 822
21.2.8 Reset and Initialization Considerations ...................................................................... 823
21.2.9 Interrupt Support................................................................................................ 823
21.2.10 DMA Event Support........................................................................................... 824
21.2.11 EMIF Signal Multiplexing..................................................................................... 824
21.2.12 Memory Map................................................................................................... 824
21.2.13 Priority and Arbitration........................................................................................ 825
21.2.14 System Considerations....................................................................................... 826
21.2.15 Power Management .......................................................................................... 827
21.2.16 Emulation Considerations.................................................................................... 827
21.3 EMIF Registers............................................................................................................ 828
21.3.1 Module ID Register (MIDR) ................................................................................... 828
21.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 829
21.3.3 SDRAM Configuration Register (SDCR) .................................................................... 830
21.3.4 SDRAM Refresh Control Register (SDRCR)................................................................ 831
21.3.5 Asynchronous nConfiguration Registers (CE2CFG-CE5CFG) .......................................... 832
21.3.6 SDRAM Timing Register (SDTIMR).......................................................................... 833
21.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 834
21.3.8 EMIF Interrupt Raw Register (INTRAW)..................................................................... 835
21.3.9 EMIF Interrupt Masked Register (INTMSK)................................................................. 836
21.3.10 EMIF Interrupt Mask Set Register (INTMSKSET) ........................................................ 837
21.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR)...................................................... 838
21.3.12 Page Mode Control Register (PMCR)...................................................................... 839
21.4 Example Configuration................................................................................................... 840
21.4.1 Hardware Interface ............................................................................................. 840
21.4.2 Software Configuration......................................................................................... 840
22 Analog To Digital Converter (ADC) Module .......................................................................... 848
22.1 Overview .................................................................................................................. 849
22.1.1 Introduction ..................................................................................................... 851
22.2 Basic Operation........................................................................................................... 853
22.2.1 Basic Features and Usage of the ADC ..................................................................... 853
22.2.2 Advanced Conversion Group Configuration Options ...................................................... 860
22.2.3 ADC Module Basic Interrupts ................................................................................ 868
22.2.4 ADC Module DMA Requests ................................................................................. 869
22.2.5 ADC Magnitude Threshold Interrupts ....................................................................... 870
22.2.6 ADC Special Modes............................................................................................ 871
22.2.7 ADC Results’ RAM Special Features ........................................................................ 878
22.2.8 ADEVT Pin General Purpose I/O Functionality............................................................. 879

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22.3 ADC Registers ............................................................................................................ 881
22.3.1 ADC Reset Control Register (ADRSTCR) .................................................................. 883
22.3.2 ADC Operating Mode Control Register (ADOPMODECR) ............................................... 883
22.3.3 ADC Clock Control Register (ADCLOCKCR) .............................................................. 885
22.3.4 ADC Calibration Mode Control Register (ADCALCR) ..................................................... 885
22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR)................................ 887
22.3.6 ADC Group1 Operating Mode Control Register (ADG1MODECR) ...................................... 890
22.3.7 ADC Group2 Operating Mode Control Register (ADG2MODECR) ...................................... 893
22.3.8 ADC Event Group Trigger Source Select Register (ADEVSRC)......................................... 896
22.3.9 ADC Group1 Trigger Source Select Register (ADG1SRC) ............................................... 897
22.3.10 ADC Group2 Trigger Source Select Register (ADG2SRC).............................................. 898
22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)......................................... 899
22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)....................................... 900
22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)....................................... 901
22.3.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG).............................................. 902
22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG).................................................... 903
22.3.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG).................................................... 904
22.3.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ......................... 905
22.3.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) ............................... 905
22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) ............................... 906
22.3.20 ADC Event Group DMA Control Register (ADEVDMACR).............................................. 907
22.3.21 ADC Group1 DMA Control Register (ADG1DMACR) .................................................... 909
22.3.22 ADC Group2 DMA Control Register (ADG2DMACR) .................................................... 911
22.3.23 ADC Results Memory Configuration Register (ADBNDCR)............................................. 913
22.3.24 ADC Results Memory Size Configuration Register (ADBNDEND) ..................................... 914
22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)............................. 915
22.3.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP)................................... 915
22.3.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP)................................... 916
22.3.28 ADC Event Group Status Register (ADEVSR)............................................................ 917
22.3.29 ADC Group1 Status Register (ADG1SR) .................................................................. 918
22.3.30 ADC Group2 Status Register (ADG2SR) .................................................................. 919
22.3.31 ADC Event Group Channel Select Register (ADEVSEL)................................................ 920
22.3.32 ADC Group1 Channel Select Register (ADG1SEL) ...................................................... 921
22.3.33 ADC Group2 Channel Select Register (ADG2SEL) ...................................................... 922
22.3.34 ADC Calibration and Error Offset Correction Register (ADCALR)...................................... 923
22.3.35 ADC State Machine Status Register (ADSMSTATE) .................................................... 923
22.3.36 ADC Channel Last Conversion Value Register (ADLASTCONV) ...................................... 924
22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER) ............................................ 925
22.3.38 ADC Group1 Results FIFO Register (ADG1BUFFER)................................................... 926
22.3.39 ADC Group2 Results FIFO Register (ADG2BUFFER)................................................... 927
22.3.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER).......................... 928
22.3.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER)................................ 929
22.3.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER)................................ 930
22.3.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR) .............................................. 931
22.3.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT) ........................................ 932
22.3.45 ADC ADEVT Pin Input Value Register (ADEVTIN)....................................................... 932
22.3.46 ADC ADEVT Pin Set Register (ADEVTSET).............................................................. 933
22.3.47 ADC ADEVT Pin Clear Register (ADEVTCLR) ........................................................... 933
22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) .......................................... 934
22.3.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) ......................................... 934
22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL).......................................... 935
22.3.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) .................. 935
22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ........................ 936

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22.3.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ........................ 937
22.3.54 ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR)............................. 938
22.3.55 ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK)............................ 940
22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) .................... 941
22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR).................. 941
22.3.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG).................................. 942
22.3.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)................................ 942
22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)............................. 943
22.3.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR)................................... 943
22.3.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR)................................... 944
22.3.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) ............................. 944
22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR).................................... 945
22.3.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR).................................... 945
22.3.66 ADC Parity Control Register (ADPARCR) ................................................................. 946
22.3.67 ADC Parity Error Address Register (ADPARADDR) ..................................................... 947
22.3.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) ....................................... 947
22.3.69 ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) ...... 948
22.3.70 ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) ............ 948
22.3.71 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) ............ 949
22.3.72 ADC Event Group Current Count Register (ADEVCURRCOUNT)..................................... 950
22.3.73 ADC Event Group Maximum Count Register (ADEVMAXCOUNT) .................................... 950
22.3.74 ADC Group1 Current Count Register (ADG1CURRCOUNT) ........................................... 951
22.3.75 ADC Group1 Maximum Count Register (ADG1MAXCOUNT) .......................................... 951
22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT) ........................................... 952
22.3.77 ADC Group2 Maximum Count Register (ADG2MAXCOUNT) .......................................... 952
23 High-End Timer (N2HET) Module ........................................................................................ 953
23.1 Overview................................................................................................................... 954
23.1.1 Features.......................................................................................................... 954
23.1.2 Major Advantages .............................................................................................. 954
23.1.3 Block Diagram................................................................................................... 955
23.1.4 Timer Module Structure and Execution...................................................................... 956
23.1.5 Performance..................................................................................................... 957
23.1.6 N2HET Compared to NHET................................................................................... 957
23.1.7 NHET and N2HET Compared to HET ....................................................................... 957
23.1.8 Instructions Features........................................................................................... 958
23.1.9 Program Usage ................................................................................................. 958
23.2 N2HET Functional Description.......................................................................................... 958
23.2.1 Specialized Timer Micromachine............................................................................. 958
23.2.2 N2HET RAM Organization .................................................................................... 963
23.2.3 Time Base ....................................................................................................... 966
23.2.4 Host Interface ................................................................................................... 969
23.2.5 I/O Control....................................................................................................... 970
23.2.6 Suppression Filters............................................................................................. 986
23.2.7 Interrupts and Exceptions ..................................................................................... 987
23.2.8 Hardware Priority Scheme..................................................................................... 988
23.2.9 N2HET Requests to DMA and HTU.......................................................................... 990
23.3 Angle Functions........................................................................................................... 990
23.3.1 Software Angle Generator..................................................................................... 990
23.3.2 Hardware Angle Generator (HWAG)......................................................................... 995
23.4 N2HET Control Registers .............................................................................................. 1017
23.4.1 Global Configuration Register (HETGCR) ................................................................. 1018
23.4.2 Prescale Factor Register (HETPFR) ....................................................................... 1020
23.4.3 N2HET Current Address Register (HETADDR)........................................................... 1021

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23.4.4 Offset Index Priority Level 1 Register (HETOFF1)........................................................ 1021
23.4.5 Offset Index Priority Level 2 Register (HETOFF2)........................................................ 1022
23.4.6 Interrupt Enable Set Register (HETINTENAS)............................................................ 1023
23.4.7 Interrupt Enable Clear Register (HETINTENAC) ......................................................... 1023
23.4.8 Exception Control Register 1 (HETEXC1) ................................................................. 1024
23.4.9 Exception Control Register 2 (HETEXC2) ................................................................. 1025
23.4.10 Interrupt Priority Register (HETPRY)...................................................................... 1026
23.4.11 Interrupt Flag Register (HETFLG)......................................................................... 1026
23.4.12 AND Share Control Register (HETAND) ................................................................. 1027
23.4.13 HR Share Control Register (HETHRSH) ................................................................. 1028
23.4.14 XOR Share Control Register (HETXOR) ................................................................. 1029
23.4.15 Request Enable Set Register (HETREQENS)........................................................... 1030
23.4.16 Request Enable Clear Register (HETREQENC) ........................................................ 1030
23.4.17 Request Destination Select Register (HETREQDS) .................................................... 1031
23.4.18 NHET Direction Register (HETDIR)....................................................................... 1032
23.4.19 N2HET Data Input Register (HETDIN).................................................................... 1033
23.4.20 N2HET Data Output Register (HETDOUT) .............................................................. 1033
23.4.21 NHET Data Set Register (HETDSET) .................................................................... 1034
23.4.22 N2HET Data Clear Register (HETDCLR) ................................................................ 1034
23.4.23 N2HET Open Drain Register (HETPDR) ................................................................. 1035
23.4.24 N2HET Pull Disable Register (HETPULDIS)............................................................. 1035
23.4.25 N2HET Pull Select Register (HETPSL)................................................................... 1036
23.4.26 Parity Control Register (HETPCR) ........................................................................ 1037
23.4.27 Parity Address Register (HETPAR) ....................................................................... 1038
23.4.28 Parity Pin Register (HETPPR) ............................................................................. 1039
23.4.29 Suppression Filter Preload Register (HETSFPRLD).................................................... 1040
23.4.30 Suppression Filter Enable Register (HETSFENA) ...................................................... 1040
23.4.31 Loop Back Pair Select Register (HETLBPSEL) ......................................................... 1041
23.4.32 Loop Back Pair Direction Register (HETLBPDIR)....................................................... 1042
23.4.33 N2HET Pin Disable Register (HETPINDIS).............................................................. 1043
23.5 HWAG Registers ........................................................................................................ 1044
23.5.1 HWAG Pin Select Register (HWAPINSEL)................................................................ 1045
23.5.2 HWAG Global Control Register 0 (HWAGCR0)........................................................... 1046
23.5.3 HWAG Global Control Register 1 (HWAGCR1)........................................................... 1046
23.5.4 HWAG Global Control Register 2 (HWAGCR2)........................................................... 1047
23.5.5 HWAG Interrupt Enable Set Register (HWAENASET)................................................... 1048
23.5.6 HWAG Interrupt Enable Clear Register (HWAENACLR) ................................................ 1049
23.5.7 HWAG Interrupt Level Set Register (HWALVLSET)...................................................... 1050
23.5.8 HWAG Interrupt Level Clear Register (HWALVLCLR)................................................... 1050
23.5.9 HWAG Interrupt Flag Register (HWAFLG) ................................................................ 1051
23.5.10 HWAG Interrupt Offset Register 0 (HWAOFF0)......................................................... 1052
23.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1)......................................................... 1053
23.5.12 HWAG Angle Value Register (HWAACNT) .............................................................. 1054
23.5.13 HWAG Previous Tooth Period Value Register (HWAPCNT1)......................................... 1055
23.5.14 HWAG Current Tooth Period Value Register (HWAPCNT)............................................ 1055
23.5.15 HWAG Step Width Register (HWASTWD)............................................................... 1056
23.5.16 HWAG Teeth Number Register (HWATHNB)............................................................ 1057
23.5.17 HWAG Current Teeth Number Register (HWATHVL) .................................................. 1057
23.5.18 HWAG Filter Register (HWAFIL) .......................................................................... 1058
23.5.19 HWAG Filter Register 2 (HWAFIL2)....................................................................... 1058
23.5.20 HWAG Angle Increment Register (HWAANGI).......................................................... 1059
23.6 Instruction Set ........................................................................................................... 1060
23.6.1 Instruction Summary.......................................................................................... 1060

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23.6.2 Abbreviations, Encoding Formats and Bits ............................................................... 1062
23.6.3 Instruction Description ....................................................................................... 1065
24 High-End Timer Transfer Unit (HTU) Module....................................................................... 1131
24.1 Overview.................................................................................................................. 1132
24.1.1 Features........................................................................................................ 1132
24.2 Module Operation ....................................................................................................... 1133
24.2.1 Data Transfers between Main RAM and N2HET RAM................................................... 1135
24.2.2 Arbitration of HTU Elements and Frames.................................................................. 1139
24.2.3 Conditions for Frame Transfer Interruption ................................................................ 1140
24.2.4 HTU Overload and Request Lost Detection ............................................................... 1140
24.2.5 Memory Protection............................................................................................ 1143
24.2.6 Control Packet RAM Parity Checking ...................................................................... 1143
24.3 Use Cases................................................................................................................ 1145
24.3.1 Example: Single Element Transfer with One Trigger Request.......................................... 1145
24.3.2 Example: Multiple Element Transfer with One Trigger Request........................................ 1145
24.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields.............................................. 1147
24.4 HTU Control Registers.................................................................................................. 1148
24.4.1 Global Control Register (HTU GC).......................................................................... 1149
24.4.2 Control Packet Enable Register (HTU CPENA)........................................................... 1150
24.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0)..................................................... 1151
24.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1)..................................................... 1152
24.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2)..................................................... 1152
24.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3)..................................................... 1153
24.4.7 Active Control Packet and Error Register (HTU ACPE).................................................. 1153
24.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)...................................... 1155
24.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS)................................................ 1156
24.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC)............................................ 1156
24.4.11 Interrupt Mapping Register (HTU INTMAP).............................................................. 1157
24.4.12 Interrupt Offset Register 0 (HTU INTOFF0).............................................................. 1158
24.4.13 Interrupt Offset Register 1 (HTU INTOFF1).............................................................. 1159
24.4.14 Buffer Initialization Mode Register (HTU BIM)........................................................... 1160
24.4.15 Request Lost Flag Register (HTU RLOSTFL) ........................................................... 1162
24.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ..................................................... 1162
24.4.17 BER Interrupt Flag Register (HTU BERINTFL).......................................................... 1163
24.4.18 Memory Protection 1 Start Address Register (HTU MP1S)............................................ 1164
24.4.19 Memory Protection 1 End Address Register (HTU MP1E)............................................. 1164
24.4.20 Debug Control Register (HTU DCTRL)................................................................... 1165
24.4.21 Watch Point Register (HTU WPR) ........................................................................ 1166
24.4.22 Watch Mask Register (HTU WMR)........................................................................ 1166
24.4.23 Module Identification Register (HTU ID).................................................................. 1167
24.4.24 Parity Control Register (HTU PCR) ....................................................................... 1168
24.4.25 Parity Address Register (HTU PAR) ...................................................................... 1169
24.4.26 Memory Protection Control and Status Register (HTU MPCS)........................................ 1170
24.4.27 Memory Protection Start Address Register 0 (HTU MP0S)............................................ 1173
24.4.28 Memory Protection End Address Register (HTU MP0E)............................................... 1173
24.5 Double Control Packet Configuration Memory ...................................................................... 1174
24.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1175
24.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1175
24.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT) ....................................... 1176
24.5.4 Initial Transfer Count Register (HTU ITCOUNT).......................................................... 1177
24.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1178
24.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1179
24.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1180

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24.6 Examples................................................................................................................. 1181
24.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ..................... 1181
24.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B ........................ 1181
24.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt................................... 1182
25 General-Purpose Input/Output (GIO) Module ...................................................................... 1183
25.1 Overview.................................................................................................................. 1184
25.2 Quick Start Guide ....................................................................................................... 1185
25.3 Functional Description of GIO Module................................................................................ 1187
25.3.1 I/O Functions................................................................................................... 1187
25.3.2 Interrupt Function ............................................................................................. 1188
25.3.3 GIO Block Diagram ........................................................................................... 1188
25.4 Device Modes of Operation............................................................................................ 1190
25.4.1 Emulation Mode ............................................................................................... 1190
25.4.2 Power-Down Mode (Low-Power Mode).................................................................... 1190
25.5 GIO Control Registers .................................................................................................. 1191
25.5.1 GIO Global Control Register (GIOGCR0).................................................................. 1192
25.5.2 GIO Interrupt Detect Register (GIOINTDET) .............................................................. 1193
25.5.3 GIO Interrupt Polarity Register (GIOPOL) ................................................................. 1194
25.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) ..................................... 1195
25.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)....................................... 1197
25.5.6 GIO Interrupt Flag Register (GIOFLG) ..................................................................... 1200
25.5.7 GIO Offset Register 1 (GIOOFF1) .......................................................................... 1201
25.5.8 GIO Offset B Register (GIOOFF2).......................................................................... 1202
25.5.9 GIO Emulation A Register (GIOEMU1) .................................................................... 1203
25.5.10 GIO Emulation B Register (GIOEMU2)................................................................... 1204
25.5.11 GIO Data Direction Registers (GIODIR[A-B])............................................................ 1205
25.5.12 GIO Data Input Registers (GIODIN[A-B])................................................................. 1205
25.5.13 GIO Data Output Registers (GIODOUT[A-B]) ........................................................... 1206
25.5.14 GIO Data Set Registers (GIODSET[A-B])................................................................ 1206
25.5.15 GIO Data Clear Registers (GIODCLR[A-B]) ............................................................. 1207
25.5.16 GIO Open Drain Registers (GIOPDR[A-B]) .............................................................. 1207
25.5.17 GIO Pull Disable Registers (GIOPULDIS[A-B]).......................................................... 1208
25.5.18 GIO Pull Select Registers (GIOPSL[A-B])................................................................ 1208
25.6 I/O Control Summary ................................................................................................... 1209
26 FlexRay Module .............................................................................................................. 1210
26.1 Overview.................................................................................................................. 1211
26.1.1 Feature List .................................................................................................... 1211
26.1.2 FlexRay Module Block Diagram............................................................................. 1211
26.1.3 FlexRay Module Blocks ...................................................................................... 1214
26.2 Module Operation ....................................................................................................... 1215
26.2.1 Transfer Unit................................................................................................... 1215
26.2.2 Communication Cycle ........................................................................................ 1226
26.2.3 Communication Modes....................................................................................... 1227
26.2.4 Clock Synchronization........................................................................................ 1228
26.2.5 Error Handling ................................................................................................. 1229
26.2.6 Communication Controller States........................................................................... 1231
26.2.7 Network Management ........................................................................................ 1243
26.2.8 Filtering and Masking......................................................................................... 1243
26.2.9 Transmit Process.............................................................................................. 1246
26.2.10 Receive Process............................................................................................. 1248
26.2.11 FIFO Function................................................................................................ 1249
26.2.12 Message Handling........................................................................................... 1250
26.2.13 Module RAMs ................................................................................................ 1258

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26.2.14 Interrupts...................................................................................................... 1269
26.2.15 Minimum Peripheral Clock Frequency.................................................................... 1274
26.2.16 Assignment of FlexRay Configuration Parameters...................................................... 1275
26.2.17 Emulation/Debug Support .................................................................................. 1276
26.3 FlexRay Module Registers............................................................................................. 1277
26.3.1 Transfer Unit Registers....................................................................................... 1277
26.3.2 Communication Controller Registers ....................................................................... 1325
27 Controller Area Network (DCAN) Module............................................................................ 1417
27.1 Overview.................................................................................................................. 1418
27.1.1 Features........................................................................................................ 1418
27.1.2 Functional Description........................................................................................ 1418
27.2 CAN Blocks .............................................................................................................. 1419
27.2.1 CAN Core ...................................................................................................... 1419
27.2.2 Message RAM................................................................................................. 1419
27.2.3 Message Handler ............................................................................................. 1419
27.2.4 Message RAM Interface...................................................................................... 1420
27.2.5 Register and Message Object Access ..................................................................... 1420
27.2.6 Dual Clock Source ............................................................................................ 1420
27.3 CAN Bit Timing .......................................................................................................... 1421
27.3.1 Bit Time and Bit Rate......................................................................................... 1421
27.3.2 DCAN Bit Timing Registers.................................................................................. 1423
27.4 CAN Module Configuration............................................................................................. 1425
27.4.1 DCAN RAM Initialization Through Hardware.............................................................. 1425
27.4.2 CAN Module Initialization .................................................................................... 1425
27.5 Message RAM........................................................................................................... 1428
27.5.1 Structure of Message Objects............................................................................... 1428
27.5.2 Addressing Message Objects in RAM...................................................................... 1430
27.5.3 Message RAM Representation in Debug/Suspend Mode ............................................... 1431
27.5.4 Message RAM Representation in Direct Access Mode.................................................. 1431
27.5.5 ECC RAM ...................................................................................................... 1432
27.6 Message Interface Register Sets ..................................................................................... 1433
27.6.1 Message Interface Register Sets 1 and 2 ................................................................. 1433
27.6.2 Using Message Interface Register Sets 1 and 2.......................................................... 1434
27.6.3 Message Interface Register 3 ............................................................................... 1435
27.7 Message Object Configurations....................................................................................... 1436
27.7.1 Configuration of a Transmit Object for Data Frames..................................................... 1436
27.7.2 Configuration of a Transmit Object for Remote Frames ................................................. 1436
27.7.3 Configuration of a Single Receive Object for Data Frames ............................................. 1436
27.7.4 Configuration of a Single Receive Object for Remote Frames.......................................... 1437
27.7.5 Configuration of a FIFO Buffer .............................................................................. 1437
27.7.6 Reconfiguration of Message Objects for the Reception of Frames..................................... 1437
27.7.7 Reconfiguration of Message Objects for the Transmission of Frames................................. 1437
27.8 Message Handling ...................................................................................................... 1438
27.8.1 Message Handler Overview ................................................................................. 1438
27.8.2 Receive/Transmit Priority..................................................................................... 1438
27.8.3 Transmission of Messages in Event Driven CAN Communication ..................................... 1439
27.8.4 Updating a Transmit Object.................................................................................. 1439
27.8.5 Changing a Transmit Object................................................................................. 1439
27.8.6 Acceptance Filtering of Received Messages.............................................................. 1440
27.8.7 Reception of Data Frames................................................................................... 1440
27.8.8 Reception of Remote Frames .............................................................................. 1440
27.8.9 Reading Received Messages ............................................................................... 1440
27.8.10 Requesting New Data for a Receive Object............................................................. 1441