Texas Instruments MSP430F22x4 Series User manual

MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
1FEATURES
23• Low Supply Voltage Range: 1.8 V to 3.6 V • Two Configurable Operational Amplifiers
(MSP430F22x4 Only)
• Ultra-Low Power Consumption • Brownout Detector
– Active Mode: 270 µA at 1 MHz, 2.2 V • Serial Onboard Programming, No External
– Standby Mode: 0.7 µA Programming Voltage Needed, Programmable
– Off Mode (RAM Retention): 0.1 µA Code Protection by Security Fuse
• Ultra-Fast Wake-Up From Standby Mode in • Bootstrap Loader
Less Than 1 µs • On-Chip Emulation Module
• 16-Bit RISC Architecture, 62.5-ns Instruction • Family Members Include:
Cycle Time – MSP430F2232
• Basic Clock Module Configurations – 8KB + 256B Flash Memory
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1% – 512B RAM
– Internal Very-Low-Power Low-Frequency – MSP430F2252
Oscillator – 16KB + 256B Flash Memory
– 32-kHz Crystal – 512B RAM
– High-Frequency (HF) Crystal up to 16 MHz – MSP430F2272
– Resonator – 32KB + 256B Flash Memory
– External Digital Clock Source – 1KB RAM
– External Resistor – MSP430F2234
• 16-Bit Timer_A With Three Capture/Compare – 8KB + 256B Flash Memory
Registers – 512B RAM
• 16-Bit Timer_B With Three Capture/Compare – MSP430F2254
Registers – 16KB + 256B Flash Memory
• Universal Serial Communication Interface – 512B RAM
– Enhanced UART Supporting Auto-Baudrate – MSP430F2274
Detection (LIN) – 32KB + 256B Flash Memory
– IrDA Encoder and Decoder – 1KB RAM
– Synchronous SPI • Available in a 38-Pin Thin Shrink Small-Outline
– I2C™ Package (TSSOP) (DA), 40-Pin QFN Package
• 10-Bit 200-ksps Analog-to-Digital (A/D) (RHA), and 49-Pin Ball Grid Array Package
Converter With Internal Reference, Sample- (YFF) (See Table 1)
and-Hold, Autoscan, and Data Transfer • For Complete Module Descriptions, See the
Controller MSP430x2xx Family User's Guide (SLAU144)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MSP430 is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features a
powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.
The MSP430F22x4/MSP430F22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16-
bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data
transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O
pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front
ends are another area of application.
Table 1. Available Options
PACKAGED DEVICES(1)(2)
TAPLASTIC 49-PIN BGA PLASTIC 38-PIN TSSOP PLASTIC 40-PIN QFN
(YFF) (DA) (RHA)
MSP430F2232IYFF MSP430F2232IDA MSP430F2232IRHA
MSP430F2252IYFF MSP430F2252IDA MSP430F2252IRHA
MSP430F2272IYFF MSP430F2272IDA MSP430F2272IRHA
-40°C to 85°C MSP430F2234IYFF MSP430F2234IDA MSP430F2234IRHA
MSP430F2254IYFF MSP430F2254IDA MSP430F2254IRHA
MSP430F2274IYFF MSP430F2274IDA MSP430F2274IRHA
MSP430F2232TDA MSP430F2232TRHA
MSP430F2252TDA MSP430F2252TRHA
MSP430F2272TDA MSP430F2272TRHA
-40°C to 105°C MSP430F2234TDA MSP430F2234TRHA
MSP430F2254TDA MSP430F2254TRHA
MSP430F2274TDA MSP430F2274TRHA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support
All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
• Debugging and Programming Interface
– MSP-FET430UIF (USB)
– MSP-FET430PIF (Parallel Port)
• Debugging and Programming Interface with Target Board
– MSP-FET430U38 (DA package)
• Production Programmer
– MSP-GANG430
2Copyright © 2006–2012, Texas Instruments Incorporated

1TEST/SBWTCK
2DVCC
3P2.5/ROSC
4
XOUT/P2.7 5
XIN/P2.6 6
RST/NMI/SBWTDIO 7
P2.0/ACLK/A0/OA0I0 8
P2.1/TAINCLK/SMCLK/A1/OA0O 9
P2.2/TA0/A2/OA0I1 10
P3.0/UCB0STE/UCA0CLK/A5 11
P3.1/UCB0SIMO/UCB0SDA 12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE 14
P4.0/TB0
15
P4.1/TB1
16
P4.2/TB2
17
P4.3/TB0/A12/OA0O
18 P4.4/TB1/A13/OA1O
19
38 P1.7/TA2/TDO/TDI
37 P1.6/TA1/TDI
36 P1.5/TA0/TMS
35 P1.4/SMCLK/TCK
34 P1.3/TA2
33 P1.2/TA1
32 P1.1/TA0
31 P1.0/TACLK/ADC10CLK
30 P2.4/TA2/A4/VREF+/VeREF+/OA1I0
29 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
28 P3.7/A7/OA1I2
27 P3.6/A6/OA0I2
26 P3.5/UCA0RXD/UCA0SOMI
25 P3.4/UCA0TXD/UCA0SIMO
24
23AVCC
22
AVSS
21
P4.7/TBCLK
20
P4.6/TBOUTH/A15/OA1I3
DVSS
P4.5/TB2/A14/OA0I3
1TEST/SBWTCK
2DVCC
3P2.5/ROSC
4
XOUT/P2.7 5
XIN/P2.6 6
RST/NMI/SBWTDIO 7
P2.0/ACLK/A0 8
P2.1/TAINCLK/SMCLK/A1 9
P2.2/TA0/A2 10
P3.0/UCB0STE/UCA0CLK/A5 11
P3.1/UCB0SIMO/UCB0SDA 12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE 14
P4.0/TB0
15
P4.1/TB1
16
P4.2/TB2
17
P4.3/TB0/A12
18 P4.4/TB1/A13
19
38 P1.7/TA2/TDO/TDI
37 P1.6/TA1/TDI
36 P1.5/TA0/TMS
35 P1.4/SMCLK/TCK
34 P1.3/TA2
33 P1.2/TA1
32 P1.1/TA0
31 P1.0/TACLK/ADC10CLK
30 P2.4/TA2/A4/VREF+/VeREF+
29 P2.3/TA1/A3/VREF−/VeREF−
28 P3.7/A7
27 P3.6/A6
26 P3.5/UCA0RXD/UCA0SOMI
25 P3.4/UCA0TXD/UCA0SIMO
24
23AVCC
22
AVSS
21
P4.7/TBCLK
20
P4.6/TBOUTH/A15
DVSS
P4.5/TB2/A14
MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x2 Device Pinout, DA Package
MSP430F22x4 Device Pinout, DA Package
Copyright © 2006–2012, Texas Instruments Incorporated 3

1DVSS
P1.5/TA0/TMS
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK
13
P2.4/TA2/A4/VREF+/VeREF+
P2.5/ROSC DVCC TEST/SBWTCK P1.6/TA1/TDI/TCLK
2
3
4
5
6
7
8
10
9
12 14 15 16 17 18 19
30
29
28
27
26
25
24
23
21
22
3839 37 36 35 34 33 32
XOUT/P2.7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0
P2.1/TAINCLK/SMCLK/A1
P2.2/TA0/A2
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
DVCC P1.7/TA2/TDO/TDI
P2.3/TA1/A3/VREF−/VeREF−
P3.7/A7
P3.6/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
AVCC
AVSS
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0/A12 P4.4/TB1/A13
P4.5/TB2/A14
P4.6/TBOUTH/A15
P4.7/TBCLK
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
MSP430F22x2 Device Pinout, RHA Package
4Copyright © 2006–2012, Texas Instruments Incorporated

1DVSS
P1.5/TA0/TMS
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK
13
P2.4/TA2/A4/VREF+/VeREF+/OA1I0
P2.5/ROSC DVCC TEST/SBWTCK P1.6/TA1/TDI/TCLK
2
3
4
5
6
7
8
10
9
12 14 15 16 17 18 19
30
29
28
27
26
25
24
23
21
22
3839 37 36 35 34 33 32
XOUT/P2.7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0/OA0I0
P2.1/TAINCLK/SMCLK/A1/OA0O
P2.2/TA0/A2/OA0I1
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
DVCC P1.7/TA2/TDO/TDI
P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O
P3.7/A7/OA1I2
P3.6/A6/OA0I2
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
AVCC
AVSS
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O
P4.5/TB2/A14/OA0I3
P4.6/TBOUTH/A15/OA1I3
P4.7/TBCLK
MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x4 Device Pinout, RHA Package
Copyright © 2006–2012, Texas Instruments Incorporated 5

A1 A2 A4A3 A5 A6 A7
TOP VIEW
B1 B2 B4B3 B5 B6 B7
C1 C2 C4C3 C5 C6 C7
D1 D2 D4D3 D5 D6 D7
E1 E2 E4E3 E5 E6 E7
F1 F2 F4F3 F5 F6 F7
G1 G2 G4G3 G5 G6 G7
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package
Package Dimensions
The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this
data sheet for more details.
Table 2. YFF Package Dimensions
PACKAGED DEVICES D E
MSP430F22x2 3.33 ± 0.03 mm 3.49 ± 0.03 mm
MSP430F22x4
6Copyright © 2006–2012, Texas Instruments Incorporated

Basic Clock
System+
RAM
1kB
512B
512B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
32kB
16kB
8kB
ACLK
XIN
MDB
MAB
Spy−Bi Wire
Timer_B3
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
OA0, OA1
2 Op Amps
ADC10
10−Bit
12
Channels,
Autoscan,
DTC
Ports P1/P2
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
Ports P3/P4
2x8 I/O
pull−up/down
resistors
P1.x/P2.x
2x8
P3.x/P4.x
2x8
Basic Clock
System+
RAM
1kB
512B
512B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3 CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
32kB
16kB
8kB
ACLK
XIN
MDB
MAB
Spy−Bi Wire
Timer_B3
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
ADC10
10−Bit
12
Channels,
Autoscan,
DTC
Ports P1/P2
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
Ports P3/P4
2x8 I/O
pull−up/down
resistors
P1.x/P2.x
2x8
P3.x/P4.x
2x8
MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
MSP430F22x2 Functional Block Diagram
MSP430F22x4 Functional Block Diagram
Copyright © 2006–2012, Texas Instruments Incorporated 7

MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
Table 3. Terminal Functions, MSP430F22x2
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
General-purpose digital I/O pin
P1.2/TA1 E2 33 31 I/O Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P1.3/TA2 G1 34 32 I/O Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
P1.7/TA2/TDO/TDI(1) D2 38 36 I/O Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
P2.0/ACLK/A0 A4 8 6 I/O ACLK output
ADC10, analog input A0
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/A1 B4 9 7 I/O SMCLK signal output
ADC10, analog input A1
General-purpose digital I/O pin
P2.2/TA0/A2 A5 10 8 I/O Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
P2.3/TA1/A3/VREF-/ VeREF- F3 29 27 I/O ADC10, analog input A3
Negative reference voltage input
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
P2.4/TA2/A4/VREF+/ VeREF+ G3 30 28 I/O ADC10, analog input A4
Positive reference voltage output or input
General-purpose digital I/O pin
P2.5/ROSC C2 3 40 I/O Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
XIN/P2.6 A2 6 3 I/O General-purpose digital I/O pin
(1) TDO or TDI is selected via JTAG instruction.
8Copyright © 2006–2012, Texas Instruments Incorporated

MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
Output terminal of crystal oscillator
XOUT/P2.7 A1 5 2 I/O General-purpose digital I/O pin(2)
General-purpose digital I/O pin
USCI_B0 slave transmit enable
P3.0/UCB0STE/UCA0CLK/ B5 11 9 I/O
A5 USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/ A6 12 10 I/O USCI_B0 SPI mode: slave in/master out
UCB0SDA USCI_B0 I2C mode: SDA I2C data
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
General-purpose digital I/O pin
P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/ G6 25 23 I/O USCI_A0 UART mode: transmit data output
UCA0SIMO USCI_A0 SPI mode: slave in/master out
General-purpose digital I/O pin
P3.5/UCA0RXD/ G5 26 24 I/O USCI_A0 UART mode: receive data input
UCA0SOMI USCI_A0 SPI mode: slave out/master in
General-purpose digital I/O pin
P3.6/A6 F4 27 25 I/O ADC10 analog input A6
General-purpose digital I/O pin
P3.7/A7 G4 28 26 I/O ADC10 analog input A7
General-purpose digital I/O pin
P4.0/TB0 D6 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
P4.1/TB1 D7 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P4.2/TB2 E6 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P4.3/TB0/A12 E7 20 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
General-purpose digital I/O pin
P4.4/TB1/A13 F7 21 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
General-purpose digital I/O pin
P4.5/TB2/A14 F6 22 20 I/O Timer_B, compare: OUT2 output
ADC10 analog input A14
General-purpose digital I/O pin
P4.6/TBOUTH/A15 G7 23 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Copyright © 2006–2012, Texas Instruments Incorporated 9

MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
Table 3. Terminal Functions, MSP430F22x2 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
P4.7/TBCLK F5 24 22 I/O Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
RST/NMI/SBWTDIO B3 7 5 I Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
TEST/SBWTCK D1 1 37 I Spy-Bi-Wire test clock input during programming and test
C1,
D3,
DVCC 2 38, 39 Digital supply voltage
D4,
E4, E5
C6,
AVCC C7, 16 14 Analog supply voltage
D5
A3,
B1,
DVSS B2, 4 1, 4 Digital ground reference
C3,
C4
B7,
AVSS 15 13 Analog ground reference
C5
QFN Pad NA NA Pad NA QFN package pad; connection to DVSS recommended.
10 Copyright © 2006–2012, Texas Instruments Incorporated

MSP430F22x2
MSP430F22x4
www.ti.com SLAS504G –JULY 2006–REVISED AUGUST 2012
Table 4. Terminal Functions, MSP430F22x4
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input
ADC10, conversion clock
General-purpose digital I/O pin
P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output
BSL transmit
General-purpose digital I/O pin
P1.2/TA1 E2 33 31 I/O Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P1.3/TA2 G1 34 32 I/O Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
P1.7/TA2/TDO/TDI(1) D2 38 36 I/O Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
ACLK output
P2.0/ACLK/A0/OA0I0 A4 8 6 I/O ADC10, analog input A0
OA0, analog input IO
General-purpose digital I/O pin
Timer_A, clock signal at INCLK
P2.1/TAINCLK/SMCLK/ B4 9 7 I/O SMCLK signal output
A1/OA0O ADC10, analog input A1
OA0, analog output
General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
P2.2/TA0/A2/OA0I1 A5 10 8 I/O ADC10, analog input A2
OA0, analog input I1
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
P2.3/TA1/A3/ VREF-/VeREF-/F3 29 27 I/O
OA1I1/OA1O Negative reference voltage input
OA1, analog input I1
OA1, analog output
(1) TDO or TDI is selected via JTAG instruction.
Copyright © 2006–2012, Texas Instruments Incorporated 11

MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
P2.4/TA2/A4/ G3 30 28 I/O ADC10, analog input A4
VREF+/VeREF+/OA1I0 Positive reference voltage output or input
OA1, analog input I/O
General-purpose digital I/O pin
P2.5/ROSC C2 3 40 I/O Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
XIN/P2.6 A2 6 3 I/O General-purpose digital I/O pin
Output terminal of crystal oscillator
XOUT/P2.7 A1 5 2 I/O General-purpose digital I/O pin(2)
General-purpose digital I/O pin
USCI_B0 slave transmit enable
P3.0/UCB0STE/UCA0CLK/ B5 11 9 I/O
A5 USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/ A6 12 10 I/O USCI_B0 SPI mode: slave in/master out
UCB0SDA USCI_B0 I2C mode: SDA I2C data
General-purpose digital I/O pin
P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in
USCI_B0 I2C mode: SCL I2C clock
General-purpose digital I/O pin
P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/ G6 25 23 I/O USCI_A0 UART mode: transmit data output
UCA0SIMO USCI_A0 SPI mode: slave in/master out
General-purpose digital I/O pin
P3.5/UCA0RXD/ G5 26 24 I/O USCI_A0 UART mode: receive data input
UCA0SOMI USCI_A0 SPI mode: slave out/master in
General-purpose digital I/O pin
P3.6/A6/OA0I2 F4 27 25 I/O ADC10 analog input A6
OA0 analog input I2
General-purpose digital I/O pin
P3.7/A7/OA1I2 G4 28 26 I/O ADC10 analog input A7
OA1 analog input I2
General-purpose digital I/O pin
P4.0/TB0 D6 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
P4.1/TB1 D7 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
P4.2/TB2 E6 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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MSP430F22x4
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Table 4. Terminal Functions, MSP430F22x4 (continued)
TERMINAL
NO. I/O DESCRIPTION
NAME YFF DA RHA
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
P4.3/TB0/A12/OA0O E7 20 18 I/O ADC10 analog input A12
OA0 analog output
General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
P4.4/TB1/A13/OA1O F7 21 19 I/O ADC10 analog input A13
OA1 analog output
General-purpose digital I/O pin
Timer_B, compare: OUT2 output
P4.5/TB2/A14/OA0I3 F6 22 20 I/O ADC10 analog input A14
OA0 analog input I3
General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
P4.6/TBOUTH/A15/OA1I3 G7 23 21 I/O ADC10 analog input A15
OA1 analog input I3
General-purpose digital I/O pin
P4.7/TBCLK F5 24 22 I/O Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
RST/NMI/SBWTDIO B3 7 5 I Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
TEST/SBWTCK D1 1 37 I Spy-Bi-Wire test clock input during programming and test
C1,
D3,
DVCC 2 38, 39 Digital supply voltage
D4,
E4, E5
C6,
AVCC C7, 16 14 Analog supply voltage
D5
A3,
B1,
DVSS B2, 4 1, 4 Digital ground reference
C3,
C4
B7,
AVSS 15 13 Analog ground reference
C5
QFN Pad NA NA Pad NA QFN package pad; connection to DVSS recommended.
Copyright © 2006–2012, Texas Instruments Incorporated 13

General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F22x2
MSP430F22x4
SLAS504G –JULY 2006–REVISED AUGUST 2012 www.ti.com
SHORT-FORM DESCRIPTION
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Instruction Set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 5 shows examples of the three types of
instruction formats; Table 6 shows the address
modes.
Table 5. Instruction Word Formats
INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 →R5
Single operands, destination only CALL R8 PC →(TOS), R8 →PC
Relative jump, unconditional/conditional JNE Jump-on-equal bit = 0
Table 6. Address Mode Descriptions
ADDRESS MODE S (1) D(2) SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 →R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) →M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) →M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) →M(TCDAT)
Indirect ✓MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) →M(Tab+R6)
M(R10) →R11
Indirect autoincrement ✓MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 →R10
Immediate ✓MOV #X,TONI MOV #45,TONI #45 →M(TONI)
(1) S = source
(2) D = destination
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MSP430F22x4
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active. MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
– ACLK remains active.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– ACLK remains active.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK is disabled.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
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MSP430F22x2
MSP430F22x4
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 7. Interrupt Vector Addresses
SYSTEM
INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY
INTERRUPT
Power-up PORIFG
External reset RSTIFG
Watchdog Reset 0FFFEh 31, highest
WDTIFG
Flash key violation KEYV(2)
PC out-of-range(1)
NMI NMIIFG (non)-maskable,
Oscillator fault OFIFG (non)-maskable, 0FFFCh 30
Flash memory access violation ACCVIFG(2)(3) (non)-maskable
Timer_B3 TBCCR0 CCIFG(4) maskable 0FFFAh 29
TBCCR1 and TBCCR2 CCIFGs,
Timer_B3 maskable 0FFF8h 28
TBIFG(2)(4)
0FFF6h 27
Watchdog Timer WDTIFG maskable 0FFF4h 26
Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25
TACCR1 CCIFG
Timer_A3 TACCR2 CCIFG maskable 0FFF0h 24
TAIFG(2)(4)
USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG(2) maskable 0FFEEh 23
USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG(2) maskable 0FFECh 22
ADC10 ADC10IFG(4) maskable 0FFEAh 21
0FFE8h 20
I/O Port P2 P2IFG.0 to P2IFG.7(2)(4) maskable 0FFE6h 19
(eight flags)
I/O Port P1 P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18
(eight flags) 0FFE2h 17
0FFE0h 16
(5) 0FFDEh 15
(6) 0FFDCh to 0FFC0h 14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(4) Interrupt flags are located in the module.
(5) This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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MSP430F22x2
MSP430F22x4
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw Bit can be read and written.
rw-0, 1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), (1) Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 8. Interrupt Enable 1
Address 7 6 5 4 3 2 1 0
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Table 9. Interrupt Enable 2
Address 7 6 5 4 3 2 1 0
01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw-0 rw-0 rw-0 rw-0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
Table 10. Interrupt Flag Register 1
Address 7 6 5 4 3 2 1 0
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)
WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
PORIFG Power-on reset interrupt flag. Set on VCC power up.
NMIIFG Set via RST/NMI pin
Table 11. Interrupt Flag Register 2
Address 7 6 5 4 3 2 1 0
03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
rw-1 rw-0 rw-1 rw-0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
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MSP430F22x2
MSP430F22x4
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Memory Organization
Table 12. Memory Organization
MSP430F223x MSP430F225x MSP430F227x
Memory Size 8KB Flash 16KB Flash 32KB Flash
Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h
Main: code memory Flash 0FFFFh-0E000h 0FFFFh-0C000h 0FFFFh-08000h
Size 256 Byte 256 Byte 256 Byte
Information memory Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h
Size 1KB 1KB 1KB
Boot memory ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h
512 Byte 512 Byte 1KB
RAM Size 03FFh-0200h 03FFh-0200h 05FFh-0200h
16-bit 01FFh-0100h 01FFh-0100h 01FFh-0100h
Peripherals 8-bit 0FFh-010h 0FFh-010h 0FFh-010h
8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide (SLAU319).
Table 13. BSL Function Pins
BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS YFF PACKAGE PINS
Data transmit 32 - P1.1 30 - P1.1 G3 - P1.1
Data receive 10 - P2.2 8 - P2.2 A5 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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MSP430F22x2
MSP430F22x4
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal very-
low-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 14. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS
CALBC1_1MHZ byte 010FFh
1 MHz CALDCO_1MHZ byte 010FEh
CALBC1_8MHZ byte 010FDh
8 MHz CALDCO_8MHZ byte 010FCh
CALBC1_12MHZ byte 010FBh
12 MHz CALDCO_12MHZ byte 010FAh
CALBC1_16MHZ byte 010F9h
16 MHz CALDCO_16MHZ byte 010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and
write data is ignored.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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MSP430F22x2
MSP430F22x4
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 15. Timer_A3 Signal Connections
INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER
MODULE
INPUT INPUT OUTPUT
BLOCK
DA RHA YFF DA RHA YFF
SIGNAL NAME SIGNAL
31 - P1.0 29 - P1.0 F2 - P1.0 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
9 - P2.1 7 - P2.1 B4 - P2.1 TAINCLK INCLK
32 - P1.1 30 - P1.1 G2 - P1.1 TA0 CCI0A CCR0 TA0 32 - P1.1 30 - P1.1 G2 - P1.1
10 - P2.2 8 - P2.2 A5 - P2.2 TA0 CCI0B 10 - P2.2 8 - P2.2 A5 - P2.2
VSS GND 36 - P1.5 34 - P1.5 E1 - P1.5
VCC VCC
33 - P1.2 31 - P1.2 E2 - P1.2 TA1 CCI1A CCR1 TA1 33 - P1.2 31 - P1.2 E2 - P1.2
29 - P2.3 27 - P2.3 F3 - P2.3 TA1 CCI1B 29 - P2.3 27 - P2.3 F3 - P2.3
VSS GND 37 - P1.6 35 - P1.6 E3 - P1.6
VCC VCC
34 - P1.3 32 - P1.3 G1 - P1.3 TA2 CCI2A CCR2 TA2 34 - P1.3 32 - P1.3 G1 - P1.3
ACLK CCI2B 30 - P2.4 28 - P2.4 G3 - P2.4
(internal)
VSS GND 38 - P1.7 36 - P1.7 D2 - P1.7
VCC VCC
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