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CC1020
SWRS046H –NOVEMBER 2006–REVISED MARCH 2015
CC1020 Low-Power RF Transceiver for Narrowband Systems
1 Device Overview
1.1 Features
1
• True Single Chip UHF RF Transceiver • Pb-Free Package
• Frequency Range 402 MHz to 470 MHz • Digital RSSI and Carrier Sense Indicator
and 804 MHz to 960 MHz • Data Rate up to 153.6 kBaud
• High Sensitivity • OOK, FSK, and GFSK Data Modulation
– Up to –118 dBm for a 12.5 kHz Channel • Integrated Bit Synchronizer
• Programmable Output Power • Image Rejection Mixer
• Low Current Consumption • Programmable Frequency and AFC Make Crystal
– RX: 19.9 mA Temperature Drift Compensation Possible Without
TCXO
• Low Supply Voltage • Suitable for Frequency Hopping Systems
– 2.3 V to 3.6 V • Suited for Systems Targeting Compliance With
• No External IF Filter Needed EN 300 220, FCC CFR47 Part 15, ARIB STD-T67,
• Low-IF Receiver and ARIB STD-T96
• Very Few External Components Required • Development Kit Available
• Small Size • Easy-to-Use Software for Generating the CC1020
– QFN 32 Package Configuration Data
1.2 Applications
• Narrowband Low-Power UHF Wireless Data • AMR – Automatic Meter Reading
Transmitters and Receivers With Channel • Wireless Alarm and Security Systems
Spacing as Low as 12.5 and 25 kHz • Home Automation
• 402-, 424-, 426-, 429-, 433-, 447-, 449-, 469-, • Low Power Telemetry
868-, 915-, 960-MHz ISM/SRD Band Systems
1.3 Description
CC1020 is a true single-chip UHF transceiver designed for very low-power and very low-voltage wireless
applications. The circuit is mainly intended for the ISM (Industrial, Scientific, and Medical) and SRD (Short
Range Device) frequency bands at 402-, 424-, 426-, 429-, 433-, 447-, 449-, 469-, 868-, 915-, and 960-
MHz, but can easily be programmed for multichannel operation at other frequencies in the 402- to 470-
MHz and 804- to 960-MHz range.
The CC1020 device is especially suited for narrow-band systems with channel spacing of 12.5 or 25 kHz
complying with ARIB STD-T67 and EN 300 220.
The main operating parameters of the CC1020 device can be programmed with a serial bus, thus making
CC1020 a very flexible and easy-to-use transceiver.
In a typical system, the CC1020 device will be used together with a microcontroller and a few external
passive components.
TI recommends using the latest RF performance line device CC1120 as successor of CC1020:
www.ti.com/rfperformanceline
Table 1-1. Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CC1020 VQFNP (32) 7.00 mm × 7.00 mm
(1) For more information, see Section 8,Mechanical Packaging and Orderable Information.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

RF_IN LNA
FREQ
SYNTH
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
BIAS
Power
Control
DIGITAL
INTERFACE
TO mC
CONTROL
LOGIC
PA
ADC
ADC
RF_OUT
R_BIAS XOSC_Q1 XOSC_Q2
PDO
XOSC
VC CHP_OUT
LNA 2
0
90 :2
0
90 :2
Multiplexer
Multiplexer
PA_EN LNA_EN
PCLK
PDI
PSEL
CC1020
SWRS046H –NOVEMBER 2006–REVISED MARCH 2015 www.ti.com
1.4 Functional Block Diagram
Figure 1-1 shows the system block diagram of the CC1020 device.
Figure 1-1. Functional Block Diagram
2Device Overview Copyright © 2006–2015, Texas Instruments Incorporated
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Table of Contents
1 Device Overview ......................................... 15.7 Data Rate Programming ............................ 24
1.1 Features .............................................. 15.8 Frequency Programming............................ 26
1.2 Applications........................................... 15.9 Receiver............................................. 27
1.3 Description............................................ 15.10 Transmitter .......................................... 39
1.4 Functional Block Diagram ............................ 25.11 Input and Output Matching and Filtering............ 42
2 Revision History ......................................... 45.12 Frequency Synthesizer.............................. 45
3 Terminal Configuration and Functions.............. 55.13 VCO and LNA Current Control...................... 51
3.1 Pin Diagram .......................................... 55.14 Power Management................................. 51
3.2 Pin Configuration ..................................... 55.15 On-Off Keying (OOK) ............................... 53
4 Specifications ............................................ 75.16 Crystal Oscillator .................................... 55
4.1 Absolute Maximum Ratings .......................... 75.17 Built-in Test Pattern Generator ..................... 56
4.2 ESD Ratings.......................................... 75.18 Interrupt on Pin DCLK............................... 56
4.3 Recommended Operating Conditions................ 75.19 PA_EN and LNA_EN Digital Output Pins ........... 57
4.4 RF Transmit .......................................... 85.20 System Considerations and Guidelines............. 58
4.5 RF Receive........................................... 95.21 Antenna Considerations............................. 61
4.6 RSSI / Carrier Sense................................ 12 5.22 Configuration Registers ............................. 62
4.7 Intermediate Frequency (IF) ........................ 12 6 Applications, Implementation, and Layout........ 83
4.8 Crystal Oscillator.................................... 13 6.1 Application Information.............................. 83
4.9 Frequency Synthesizer.............................. 14 6.2 Design Requirements ............................... 85
4.10 Digital Inputs and Outputs .......................... 15 6.3 PCB Layout Recommendations..................... 86
4.11 Current Consumption ............................... 16 7 Device and Documentation Support ............... 87
4.12 Thermal Resistance Characteristics for VQFNP 7.1 Device Support...................................... 87
Package ............................................. 16 7.2 Documentation Support ............................. 87
5 Detailed Description ................................... 17 7.3 Trademarks.......................................... 88
5.1 Overview ............................................ 17 7.4 Electrostatic Discharge Caution..................... 88
5.2 Functional Block Diagram........................... 17 7.5 Export Control Notice ............................... 88
5.3 Configuration Overview ............................. 18 7.6 Glossary............................................. 88
5.4 Microcontroller Interface............................. 19 8 Mechanical Packaging and Orderable
5.5 4-wire Serial Configuration Interface................ 20 Information .............................................. 88
5.6 Signal Interface...................................... 21 8.1 Packaging Information .............................. 88
Copyright © 2006–2015, Texas Instruments Incorporated Table of Contents 3
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2 Revision History
This data manual revision history highlights the changes made to the SWRS046F device-specific data
manual to make it an SWRS046G revision.
Changes from Revision F (January 2006) to Revision G Page
• Converted document to new TI standards......................................................................................... 1
• Added Thermal Resistance Characteristics for VQFNP Package. ........................................................... 16
• Changed Register table format to new TI standards. .......................................................................... 62
Changes from January 19, 2015 to February 19, 2015 Page
• Updated RUZ package to RSS. ................................................................................................... 87
4Revision History Copyright © 2006–2015, Texas Instruments Incorporated
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PCLK 1VC
24 AVDD
23 AVDD
22 RF_OUT
21 AVDD
20 RF_IN
19 AVDD
18 R_BIAS
17
AVDD
16
PA_EN
15
LNA_EN
14
AVDD
13
AVDD
12
XOSC_Q2
11
XOSC_Q1
10
LOCK
9
DIO 8
DCLK 7
DGND 6
DVDD 5
DGND 4
PDO 3
PDI 2
32
PSEL
31
DVDD
30
DGND
29
AVDD
28
CHP_OUT
27
AVDD
26
AD_REF
25
AGND
AGND
Exposed die
attached pad
CC1020
www.ti.com SWRS046H –NOVEMBER 2006–REVISED MARCH 2015
3 Terminal Configuration and Functions
3.1 Pin Diagram
Figure 3-1 shows pin names and locations for the CC1020 device.
The CC1020 comes in a QFN 32-type package.
Figure 3-1. Package 7-mm × 7-mm VQFNP (Top View)
3.2 Pin Configuration
Table 3-1 provides an overview of the CC1020 pinout.
Table 3-1. Pin Attributes(1)(2)
PIN NO. PIN NAME TYPE DESCRIPTION
Exposed die attached pad. Must be soldered to a solid ground plane as
— AGND Ground (analog) this is the ground connection for all analog modules. See Section 6.3 for
more details.
1 PCLK Digital input Programming clock for SPI configuration interface
2 PDI Digital input Programming data input for SPI configuration interface
3 PDO Digital output Programming data output for SPI configuration interface
4 DGND Ground (digital) Ground connection (0 V) for digital modules and digital I/O
5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O
6 DGND Ground (digital) Ground connection (0 V) for digital modules (substrate)
Clock for data in both receive and transmit mode.
7 DCLK Digital output Can be used as receive data output in asynchronous mode
Data input in transmit mode; data output in receive mode.
8 DIO Digital input/output Can also be used to start power-up sequencing in receive
PLL Lock indicator, active low. Output is asserted (low) when PLL is in
9 LOCK Digital output lock. The pin can also be used as a general digital output, or as receive
data output in synchronous NRZ/Manchester mode
10 XOSC_Q1 Analog input Crystal oscillator or external clock input
11 XOSC_Q2 Analog output Crystal oscillator
12 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator
13 AVDD Power (analog) Power supply (3 V typical) for the IF VGA
General digital output. Can be used for controlling an external LNA if
14 LNA_EN Digital output higher sensitivity is needed.
(1) DCLK, DIO and LOCK are high-impedance (3-state) in power down (BIAS_PD = 1 in the MAIN register).
(2) The exposed die attached pad must be soldered to a solid ground plane as this is the main ground connection for the chip.
Copyright © 2006–2015, Texas Instruments Incorporated Terminal Configuration and Functions 5
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Table 3-1. Pin Attributes(1)(2) (continued)
PIN NO. PIN NAME TYPE DESCRIPTION
General digital output. Can be used for controlling an external PA if higher
15 PA_EN Digital output output power is needed.
16 AVDD Power (analog) Power supply (3 V typical) for global bias generator and IF anti-alias filter
17 R_BIAS Analog output Connection for external precision bias resistor (82 kΩ, ±1%)
18 AVDD Power (analog) Power supply (3 V typical) for LNA input stage
19 RF_IN RF Input RF signal input from antenna (external AC-coupling)
20 AVDD Power (analog) Power supply (3 V typical) for LNA
21 RF_OUT RF output RF signal output to antenna
Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA
22 AVDD Power (analog) stage
23 AVDD Power (analog) Power supply (3 V typical) for VCO
24 VC Analog input VCO control voltage input from external loop filter
25 AGND Ground (analog) Ground connection (0 V) for analog modules (guard)
26 AD_REF Power (analog) 3 V reference input for ADC
27 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector
28 CHP_OUT Analog output PLL charge pump output to external loop filter
29 AVDD Power (analog) Power supply (3 V typical) for ADC
30 DGND Ground (digital) Ground connection (0 V) for digital modules (guard)
31 DVDD Power (digital) Power supply connection (3 V typical) for digital modules
Programming chip select, active low, for configuration interface. Internal
32 PSEL Digital input pullup resistor.
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4 Specifications
4.1 Absolute Maximum Ratings(1)
PARAMETER MIN MAX UNIT CONDITION
All supply pins must have the same
Supply voltage, VDD –0.3 5.0 V voltage
VDD + 0.3,
Voltage on any pin –0.3 V
max 5.0
Input RF level 10 dBm
Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020(2)
Humidity non-condensing 5% 85%
Storage temperature range, Tstg –50 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under general characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD_020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”.
4.2 ESD Ratings
VALUE UNIT
All pads except RF ±1 kV
Human Body Model (HBM), per
Electrostatic discharge (ESD) ANSI/ESDA/JEDEC JS001(1)(2)
VESD RF Pads ±0.4 kV
performance: Charged-device Model (CDM) 250 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) According to JEDEC STD 22, method A114, Human Body Model
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT CONDITION
402 470 MHz Programmable in < 300 Hz steps
RF Frequency Range 804 960 MHz Programmable in < 600 Hz steps
Operating ambient temperature range –40 85 °C The same supply voltage should be used for digital
(DVDD) and analog (AVDD) power.
Supply voltage 2.3 3.0 3.6 V A 3.0 ±0.1 V supply is recommended to meet the
ARIB STD-T67 selectivity and output power tolerance
requirements.
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4.4 RF Transmit
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
The data rate is programmable. See
Section 5.7 for details.
NRZ or Manchester encoding can be
used. 153.6 kBaud equals 153.6 kbps
Transmit data rate 0.45 153.6 kBaud using NRZ coding and 76.8 kbps using
Manchester coding. See Section 5.4.2
for details.
Minimum data rate for OOK is 2.4 kBaud
in 402 to 470 MHz range 0 108 kHz 108/216 kHz is the maximum specified
Binary FSK separation at 1.84 MHz reference
frequency frequency. Larger separations can be
in 804 to 960 MHz range 0 216 kHz
separation achieved at higher reference
frequencies.
433 MHz –20 to +10 dBm Delivered to 50 Ωsingle-ended load. The
output power is programmable and
should not be programmed to exceed
Output power +10/+5 dBm at 433/868 MHz under any
868 MHz –20 to +5 dBm operating conditions (refer to CC1020
Errata Note 003 in the CC1020 product
folder). See Section 5.11 for details.
At 2.3 V, +85°C –4 dB
Output power At maximum output power
tolerance At 3.6 V, –40°C 3 dB
2nd harmonic, 433 MHz, –50 dBc
+10 dBm Harmonics are measured as EIRP
3rd harmonic, 433 MHz, –50 dBc values according to EN 300 220. The
+10 dBm
Harmonics, antenna (SMAFF-433 and SMAFF-868
radiated CW 2nd harmonic, 868 MHz, from R.W. Badland) plays a part in
–50 dBc
+5 dBm attenuating the harmonics.
3rd harmonic, 868 MHz, –50 dBc
+5 dBm
12.5 kHz channel spacing, For 12.5 kHz channel spacing ACP is
–46 dBc
433 MHz measured in a ±4.25 kHz bandwidth at
±12.5 kHz offset. Modulation: 2.4 kBaud
25 kHz channel spacing, –52 dBc NRZ PN9 sequence, ±2.025 kHz
433 MHz
Adjacent channel frequency deviation.
power (GFSK) For 25 kHz channel spacing ACP is
measured in a ±8.5 kHz bandwidth at
25 kHz channel spacing, –49 dBc ±25 kHz offset. Modulation: 4.8 kBaud
868 MHz NRZ PN9 sequence, ±2.475 kHz
frequency deviation.
12.5 kHz channel spacing, Bandwidth for 99.5% of total average
7.5 kHz
433 MHz power.
Modulation for 12.5 channel spacing:
25 kHz channel spacing,
Occupied 9.6 kHz 2.4 kBaud NRZ PN9 sequence,
433 MHz
bandwidth ±2.025 kHz frequency deviation.
(99.5%,GFSK) Modulation for 25 kHz channel spacing:
25 kHz channel spacing, 9.6 kHz 4.8 kBaud NRZ PN9 sequence,
868 MHz ±2.475 kHz frequency deviation.
19.2 kBaud, ±9.9 kHz Bandwidth where the power envelope of
48 kHz
Modulation frequency deviation modulation equals –36 dBm. Spectrum
bandwidth, analyzer
38.4 kBaud, ±19.8 kHz
868 MHz 106 kHz RBW = 1 kHz.
frequency deviation
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RF Transmit (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
47 to 74, 87.5 to 118, 174 to At maximum output power, +10/+5 dBm
–54 dBm
230, 470 to 862 MHz at 433/868 MHz.
To comply with EN 300 220, FCC
9 kHz to 1 GHz –36 dBm CFR47 part 15 and ARIB STD-T96 an
external (antenna) filter, as implemented
in the application circuit in Section 5.11,
must be used and tailored to each
individual design to reduce out-of-band
spurious emission levels.
Spurious emissions can be measured as
EIRP values according to EN 300 220.
The antenna (SMAFF-433 and SMAFF-
Spurious emission, 868 from R.W. Badland) plays a part in
radiated CW attenuating the spurious emissions.
1 to 4 GHz –30 dBm If the output power is increased using an
external PA, a filter must be used to
attenuate spurs below 862 MHz when
operating in the 868 MHz frequency
band in Europe. Application Note AN036
CC1020/1021 Reducing Spurious
Emission (SWRA057) presents and
discusses a solution that reduces the TX
mode spurious emission close to 862
MHz by increasing the REF_DIV from 1
to 7.
433 MHz 54 + j44 Ω
Optimum load Transmit mode. For matching details see
868 MHz 15 + j24 Ω
impedance Section 5.11.
915 MHz 20 + j35 Ω
4.5 RF Receive
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
12.5 kHz channel spacing, optimized Sensitivity is measured with PN9
–114 dBm
selectivity, ±2.025 kHz freq. deviation sequence at BER = 10−3
12.5 kHz channel spacing:
12.5 kHz channel spacing, optimized
Receiver sensitivity, –118 dBm 2.4 kBaud, Manchester coded data.
sensitivity, ±2.025 kHz freq. deviation
433 MHz, FSK 25 kHz channel spacing:
25 kHz channel spacing –112 dBm 4.8 kBaud, NRZ coded data, ±2.475
kHz frequency deviation.
500 kHz channel spacing –96 dBm 500 kHz channel spacing:
12.5 kHz channel spacing, ±2.475 kHz 153.6 kBaud, NRZ coded data, ±72
–116 dBm
freq. deviation kHz frequency deviation.
Receiver sensitivity, See Table 5-6 and Table 5-7 for
25 kHz channel spacing –111 dBm
868 MHz, FSK typical sensitivity figures at other
500 kHz channel spacing –94 dBm data rates.
2.4 kBaud –116 dBm Sensitivity is measured with PN9
Receiver sensitivity, sequence at BER = 10−3
433 MHz, OOK 153.6 kBaud –81 dBm Manchester coded data.
4.8 kBaud –107 dBm
Receiver sensitivity, See Table 5-14 for typical sensitivity
868 MHz, OOK figures at other data rates.
153.6 kBaud –87 dBm
Saturation FSK: Manchester/NRZ coded data
(maximum input FSK and OOK 10 dBm OOK: Manchester coded data
level) BER = 10−3
The receiver channel filter 6 dB
System noise bandwidth is programmable from
9.6 to 307.2 kHz
bandwidth 9.6 kHz to 307.2 kHz. See
Section 5.9.2.
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RF Receive (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Noise figure, 433 and 868 MHz 7 dB NRZ coded data
cascaded –23 dBm LNA2 maximum gain
433 MHz, 102.4 kHz –18 dBm LNA2 medium gain
channel filter BW –16 dBm LNA2 minimum gain
Input IP3(1) –18 dBm LNA2 maximum gain
868 MHz, 102.4 kHz –15 dBm LNA2 medium gain
channel filter BW –13 dBm LNA2 minimum gain
12.5 kHz channel spacing, 433 MHz –11 dB Wanted signal 3 dB above the
Co-channel sensitivity level, FM jammer (1 kHz
25 kHz channel spacing, 433 MHz –11 dB
rejection, FSK and sine, ±2.5 kHz deviation) at
OOK 25 kHz channel spacing, 868 MHz –11 dB operating frequency, BER = 10–3.
12.5 kHz channel spacing, 433 MHz 32 dB Wanted signal 3 dB above the
sensitivity level, FM jammer (1 kHz
Adjacent channel sine, ±2.5 kHz deviation) at adjacent
25 kHz channel spacing, 433 MHz 37 dB
rejection (ACR) channel. BER = 10–3.
25 kHz channel spacing, 868 MHz 32 dB
No I/Q gain and Wanted signal 3 dB above the
26/31 dB
phase calibration sensitivity level, CW jammer at
Image channel image frequency, BER = 10−3.
433/868 MHz
rejection Image rejection after calibration will
I/Q gain and phase 49/52 dB depend on temperature and supply
calibrated voltage. Refer to Section 5.9.6.
12.5 kHz channel spacing, 433 MHz 41 dB Wanted signal 3 dB above the
sensitivity level. CW jammer is
25 kHz channel spacing, 433 MHz 41 dB swept in 12.5 kHz/25 kHz steps to
Selectivity(2) within ±1 MHz from wanted channel.
25 kHz channel spacing, 868 MHz 39 dB BER = 10–3. Adjacent channel and
image channel are excluded.
±1 MHz 50/57 dB Wanted signal 3 dB above the
sensitivity level, CW jammer at ±1,
±2 MHz 64/71 dB 2, 5 and 10 MHz offset. BER = 10–3.
Blocking / ±5 MHz 64/71 dB
433/868 MHz 12.5 kHz/25 kHz channel spacing at
Desensitization(3) 433/868 MHz.
Complying with EN 300 220, class 2
±10 MHz 75/78 dB receiver requirements.
No I/Q gain and Ratio between sensitivity for a
36/41 dB
phase calibration signal at the image frequency to the
sensitivity in the wanted channel.
Image frequency Image frequency is RF- 2 IF. The
433/868 MHz
suppression signal source is a 2.4 kBaud,
I/Q gain and phase 59/62 dB Manchester coded data, ±2.025 kHz
calibrated frequency deviation, signal level for
BER = 10–3.
Ratio between sensitivity for an
unwanted frequency to the
sensitivity in the wanted channel.
Spurious rejection 40 dB The signal source is swept over all
frequencies 100 MHz to 2 GHz.
Signal level for BER = 10−3.
102.4 kHz channel filter bandwidth.
(1) Two tone test (+10 MHz and +20 MHz)
(2) Close-in spurious response rejection.
(3) Out-of-band spurious response rejection.
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RF Receive (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
12.5 kHz channel spacing, 433 MHz 30 dB Wanted signal 3 dB above the
sensitivity level, two CW jammers at
Intermodulation +2Ch and +4Ch where Ch is
rejection (1) 25 kHz channel spacing, 868 MHz 30 dB channel spacing 12.5 kHz or
25 kHz. BER = 10–2.
12.5 kHz channel spacing, 433 MHz 56 dB Wanted signal 3 dB above the
Intermodulation sensitivity level, two CW jammers at
rejection (2) +10 MHz and +20 MHz offset.
25 kHz channel spacing, 868 MHz 55 dB BER = 10–2.
LO leakage 433/868 MHz < –80/–66 dBm VCO frequency resides between
VCO leakage –64 dBm 1608 and 1880 MHz.
9 kHz to 1 GHz < –60 dBm Complying with EN 300 220, FCC
CFR47 part 15 and ARIB STD-T96.
Spurious emission, Spurious emissions can be
radiated CW 1 to 4 GHz < –60 dBm measured as EIRP values
according to EN 300 220.
433 MHz 58 – j10 ΩReceive mode. See Section 5.11 for
Input impedance details.
868 MHz 54 – j22 Ω
433 MHz –14 dB Using application circuit matching
Matched input network. See Section 5.11 for
impedance, S11 868 MHz –12 dB details.
433 MHz 39 – j14 ΩUsing application circuit matching
Matched input network. See Section 5.11 for
impedance 868 MHz 32 – j10 Ωdetails.
The maximum bit rate offset
tolerated by the bit synchronization
Bit synchronization offset 8000 ppm circuit for 6 dB degradation
(synchronous modes only).
NRZ mode 4 Baud Time from clocking the data on the
Data latency transmitter DIO pin until data is
Manchester mode 8 Baud available on receiver DIO pin.
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4.6 RSSI / Carrier Sense
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER TYP UNIT CONDITION
RSSI dynamic range 55 dB 12.5 and 25 kHz channel spacing
RSSI accuracy ±3 dB See Section 5.9.5 for details.
RSSI linearity ±1 dB
2.4 kBaud, 12.5 kHz channel spacing 3.8 ms Shorter RSSI attach times can be traded for
lower RSSI accuracy. See Section 5.9.5 for
4.8 kBaud, 25 kHz channel spacing 1.9 ms details.
RSSI attach time Shorter RSSI attach times can also be traded
for reduced sensitivity and selectivity by
153.6 kBaud, 500 kHz channel spacing 140 µs increasing the receiver channel filter
bandwidth.
Carrier sense programmable range 40 dB Accuracy is as for RSSI
12.5 kHz channel spacing –72 dBm At carrier sense level –110 dBm, FM jammer
(1 kHz sine, ±2.5 kHz deviation) at adjacent
channel.
Adjacent channel carrier Adjacent channel carrier sense is measured
sense 25 kHz channel spacing –72 dBm by applying a signal on the adjacent channel
and observe at which level carrier sense is
indicated.
At carrier sense level –110 dBm, 100 MHz to
Spurious carrier sense –70 dBm 2 GHz. Adjacent channel and image channel
are excluded.
4.7 Intermediate Frequency (IF)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER TYP UNIT CONDITION
Intermediate frequency (IF) 307.2 kHz See Section 5.9.1 for details.
The channel filter 6 dB bandwidth is
Digital channel filter bandwidth 9.6 to 307.2 kHz programmable from 9.6 kHz to 307.2 kHz. See
Section 5.9.2 for details.
At 2.4 kBaud
AFC resolution 150 Hz Given as Baud rate / 16. See Section 5.9.3 for
details.
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4.8 Crystal Oscillator
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Recommended frequency is
Crystal Oscillator Frequency 4.9152 14.7456 19.6608 MHz 14.7456 MHz. See Section 5.16 for
details.
±5.7 ppm 433 MHz (EN 300 220)
868 MHz (EN 300 220)
Must be less than ±5.7 / ±2.8 ppm to
±2.8 ppm
Reference frequency comply with EN 300 220 25 kHz channel
accuracy requirement(1)(2) spacing at 433/868 MHz.
Must be less than ±4 ppm to comply with
±4 ppm Japanese 12.5 kHz channel spacing
regulations (ARIB STD-T67).
C4 and C5 are loading capacitors. See
Crystal operation Parallel Section 5.16 for details.
4.9 to 6 MHz, 22 pF 12 22 30 pF
recommended
Crystal load 6 to 8 MHz, 16 pF 12 16 30 pF
capacitance recommended
8 to 19.6 MHz, 16 pF 12 16 16 pF
recommended
4.9152 MHz, 12 pF load 1.55 ms
7.3728 MHz, 12 pF load 1.0 ms
9.8304 MHz, 12 pF load 0.90 ms
Crystal oscillator
start-up time 14.7456 MHz, 16 pF load 0.95 ms
17.2032 MHz, 12 pF load 0.60 ms
19.6608 MHz, 12 pF load 0.63 ms The external clock signal must be
connected to XOSC_Q1 using a DC
block (10 nF). Set XOSC_BYPASS = 0 in
External clock signal drive, sine wave 300 mVpp the INTERFACE register when using an
external clock signal with low amplitude
or a crystal.
The external clock signal must be
connected to XOSC_Q1. No DC block
External clock signal drive, full-swing digital 0 – VDD V shall be used. Set XOSC_BYPASS = 1 in
external clock the INTERFACE register when using a
full-swing digital external clock.
(1) The reference frequency accuracy (initial tolerance) and drift (aging and temperature dependency) will determine the frequency
accuracy of the transmitted signal.
(2) Crystal oscillator temperature compensation can be done using the fine step PLL frequency programmability and the AFC feature. See
Section 5.9.13 for details.
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4.9 Frequency Synthesizer
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER TYP UNIT CONDITION
At 12.5 kHz offset from carrier –90 dBc/Hz Unmodulated carrier.
At 25 kHz offset from carrier –100 dBc/Hz
Phase noise, Measured using loop filter components
402 to 470 MHz At 50 kHz offset from carrier –105 dBc/Hz given in Table 6-2. The phase noise will
12.5 kHz channel spacing be higher for larger PLL loop filter
At 100 kHz offset from carrier –110 dBc/Hz bandwidth.
At 1 MHz offset from carrier –114 dBc/Hz
At 12.5 kHz offset from carrier –85 dBc/Hz Unmodulated carrier.
At 25 kHz offset from carrier –95 dBc/Hz
Phase noise, Measured using loop filter components
804 to 960 MHz At 50 kHz offset from carrier –101 dBc/Hz given in Table 6-2. The phase noise will
25 kHz channel spacing be higher for larger PLL loop filter
At 100 kHz offset from carrier –109 dBc/Hz bandwidth.
At 1 MHz offset from carrier –118 dBc/Hz
12.5 kHz channel spacing, 433 MHz 2.7 kHz After PLL and VCO calibration. The PLL
PLL loop bandwidth loop bandwidth is programmable.
25 kHz channel spacing, 868 MHz 8.3 kHz
12.5 kHz channel spacing, 433 MHz 900 µs 307.2 kHz frequency step to RF frequency
within ±10% of channel spacing. Depends
25 kHz channel spacing, 868 MHz 640 µs
PLL lock time on loop filter component values and
(RX / TX turn time) PLL_BW register setting. See Table 5-13
500 kHz channel spacing 14 µs for more details.
12.5 kHz channel spacing, 433 MHz 3.2 ms Time from writing to registers to RF
PLL turn-on time. frequency within ±10% of channel
25 kHz channel spacing, 868 MHz 2.5 ms
From power down mode spacing. Depends on loop filter
with crystal oscillator component values and PLL_BW register
500 kHz channel spacing 700 µs
running. setting. See Table 5-12 for more details.
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4.10 Digital Inputs and Outputs
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Logic "0" input voltage 0 0.3 × VDD V
Logic "1" input voltage 0.7 × VDD VDD V Output current –2.0 mA,
Logic "0" output voltage 0 0.4 V 3.0-V supply voltage
Output current 2.0 mA,
Logic "1" output voltage 2.5 VDD V 3.0-V supply voltage
Input signal equals GND.
PSEL has an internal pullup
Logic “0” input current N/A –1 µA resistor and during
configuration the current will
be –350 µA.
Logic “1” input current N/A 1 µA Input signal equals VDD
TX mode, minimum time DIO
must be ready before the
DIO setup time 20 ns positive edge of DCLK. Data
should be set up on the
negative edge of DCLK.
TX mode, minimum time DIO
must be held after the
DIO hold time 10 ns positive edge of DCLK. Data
should be set up on the
negative edge of DCLK.
Serial interface (PCLK, PDI, PDO and PSEL) timing See Table 5-1 for more
specification details
0 V on LNA_EN, PA_EN 0.90 mA
pins
0.5 V on LNA_EN, 0.87 mA
PA_EN pins
Source current 1.0 V on LNA_EN, 0.81 mA
PA_EN pins
1.5 V on LNA_EN, 0.69 mA
Pin drive, PA_EN pins See Figure 5-32 for more
LNA_EN, details.
3.0 V on LNA_EN,
PA_EN 0.93 mA
PA_EN pins
2.5 V on LNA_EN, 0.92 mA
PA_EN pins
Sink current 2.0 V on LNA_EN, 0.89 mA
PA_EN pins
1.5 V on LNA_EN, 0.79 mA
PA_EN pins
Copyright © 2006–2015, Texas Instruments Incorporated Specifications 15
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4.11 Current Consumption
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V,
fC= 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Power Down mode 0.2 1.8 µA Oscillator core off
Current Consumption, 19.9 mA
receive mode 433 and 868 MHz P = –20 dBm 12.3/14.5 mA The output power is
P = –5 dBm 14.4/17.0 mA delivered to a 50 Ωsingle-
Current Consumption, P = 0 dBm 16.2/20.5 mA ended load.
transmit mode 433/868 MHz: P = +5 dBm 20.5/25.1 mA See Section 5.10.2 for more
details.
P = +10 dBm 27.1 mA
(433 MHz only) 14.7456 MHz, 16 pF load
Current Consumption, crystal oscillator 77 µA crystal
14.7456 MHz, 16 pF load
Current Consumption, crystal oscillator and bias 500 µA crystal
14.7456 MHz, 16 pF load
Current Consumption, crystal oscillator, bias and synthesizer 7.5 mA crystal
4.12 Thermal Resistance Characteristics for VQFNP Package
NAME DESCRIPTION °C/W(1) (2)
RθJC(top) Junction-to-case (top) 16.2
RθJB Junction-to-board 6.9
RθJA Junction-to-free air 30.7
PsiJT Junction-to-package top 0.2
PsiJB Junction-to-board 6.9
RθJC(bottom) Junction-to-case (bottom) 1.0
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
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RF_IN LNA
FREQ
SYNTH
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
BIAS
Power
Control
DIGITAL
INTERFACE
TO mC
CONTROL
LOGIC
PA
ADC
ADC
RF_OUT
R_BIAS XOSC_Q1 XOSC_Q2
PDO
XOSC
VC CHP_OUT
LNA 2
0
90 :2
0
90 :2
Multiplexer
Multiplexer
PA_EN LNA_EN
PCLK
PDI
PSEL
CC1020
www.ti.com SWRS046H –NOVEMBER 2006–REVISED MARCH 2015
5 Detailed Description
5.1 Overview
A simplified block diagram of CC1020 is shown in Figure 5-1. Only signal pins are shown.
CC1020 features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA
and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q
signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain control, fine
channel filtering, demodulation and bit synchronization is performed digitally. CC1020 outputs the digital
demodulated data on the DIO pin. A synchronized data clock is available at the DCLK pin. RSSI is
available in digital format and can be read via the serial interface. The RSSI also features a programmable
carrier sense indicator.
In transmit mode, the synthesized RF frequency is fed directly to the power amplifier (PA). The RF output
is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian
filter can be used to obtain Gaussian FSK (GFSK).
The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for
generating the LO_I and LO_Q signals to the down-conversion mixers in receive mode. The VCO
operates in the frequency range 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and
VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal
is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.
The 4-wire SPI serial interface is used for configuration.
5.2 Functional Block Diagram
Figure 5-1. CC1020 Simplified Block Diagram
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5.3 Configuration Overview
CC1020 can be configured to achieve optimum performance for different applications. Through the
programmable configuration registers the following key parameters can be programmed:
• Receive and transmit mode
• RF output power
• Frequency synthesizer key parameters:
– RF output frequency
– FSK frequency separation
– Crystal oscillator reference frequency
• Power-down and power-up mode
• Power-down and power-up mode
• Data rate and data format (NRZ, Manchester coded or UART interface)
• Synthesizer lock indicator mode
• Digital RSSI and carrier sense
• FSK, GFSK, and OOK modulation
5.3.1 Configuration Software
TI provides users of CC1020 with a software program, SmartRF Studio (Windows interface) that
generates all necessary CC1020 configuration data based on the user’s selections of various parameters.
These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of
CC1020. In addition, the program will provide the user with the component values needed for the
input/output matching circuit, the PLL loop filter and the LC filter.
Figure 5-2 shows the user interface of the CC1020 configuration software.
Figure 5-2. SmartRF™ Studio user interface
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5.4 Microcontroller Interface
Used in a typical system, CC1020 will interface to a microcontroller. This microcontroller must be able to:
• Program CC1020 into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK
and PSEL).
• Interface to the bi-directional synchronous data signal interface (DIO and DCLK).
• Optionally, the microcontroller can do data encoding and decoding.
• Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status
or other status information.
• Optionally, the microcontroller can read back the digital RSSI value and other status information via the
4-wire serial interface.
5.4.1 Configuration Interface
The microcontroller interface is shown in Figure 5-3. The microcontroller uses 3 or 4 I/O pins for the
configuration interface (PDI, PDO, PCLK and PSEL). PDO should be connected to a microcontroller input.
PDI, PCLK and PSEL must be microcontroller outputs. One I/O pin can be saved if PDI and PDO are
connected together and a bi-directional pin is used at the microcontroller.
The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the
configuration interface is not used. PDI, PDO and PCLK are high impedance inputs as long as PSEL is
not activated (active low).
PSEL has an internal pullup resistor and should be left open (tri-stated by the microcontroller) or set to a
high level during power down mode in order to prevent a trickle current flowing in the pullup.
5.4.2 Signal Interface
A bi-directional pin is usually used for data (DIO) to be transmitted and data received. DCLK providing the
data timing should
As an option, the data output in receive mode can be made available on a separate pin. See Section 5.6
for further details.
5.4.3 PLL Lock Signal
Optionally, one microcontroller pin can be used to monitor the LOCK signal. This signal is at low logic
level when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test
signals.
Figure 5-3. Microcontroller Interface
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PCLK
PDI
PSEL
Address Write mode
6543210 765432 1 0
Data byte
THD
TSS
TCL,min TCH,min
THS
W
TSD
PDO
CC1020
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5.5 4-wire Serial Configuration Interface
CC1020 is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and PSEL) where
CC1020 is the slave. There are 8-bit configuration registers, each addressed by a 7-bit address. A
Read/Write bit initiates a read or write operation. A full configuration of CC1020 requires sending 33 data
frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration
depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less
than 53 ms. Setting the device in power down mode requires sending one frame only and will in this case
take less than 2 ms. All registers are also readable.
During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data
frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the
first bit. The next bit is the R/W bit (high for write, low for read). The 8 data-bits are then transferred
(D7:0). During address and data transfer the PSEL (Program Select) must be kept low. See Figure 5-4.
The timing for the programming is also shown in Figure 5-4 with reference to Table 5-1. The clocking of
the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of
PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is
loaded into the internal configuration register.
The configuration data will be retained during a programmed power down mode, but not when the power
supply is turned off. The registers can be programmed in any order.
The configuration registers can also be read by the microcontroller via the same configuration interface.
The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. CC1020 then
returns the data from the addressed register. PDO is used as the data output and must be configured as
an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be sampled at
the positive edge. The read operation is illustrated in Figure 5-5.
PSEL must be set high between each read/write operation.
Figure 5-4. Configuration Registers Write Operation
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