Texas Instruments TRF7970A BoosterPack User manual

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRF7970A
SLOS743L –AUGUST 2011–REVISED MARCH 2017
TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication
(NFC) Transceiver IC
1 Device Overview
1
1.1 Features
1
• Supports Near Field Communication (NFC)
Standards NFCIP-1 (ISO/IEC 18092) and NFCIP‑2
(ISO/IEC 21481)
• Completely Integrated Protocol Handling for
ISO/IEC 15693, ISO/IEC 18000-3, ISO/IEC 14443
A and B, and FeliCa™
• Integrated Encoders, Decoders, and Data Framing
for NFC Initiator, Active and Passive Target
Operation for All Three Bit Rates (106 kbps,
212 kbps, 424 kbps), and Card Emulation
• RF Field Detector With Programmable Wake-up
Levels for NFC Passive Transponder Emulation
Operation
• RF Field Detector for NFC Physical Collision
Avoidance
• Integrated State Machine for ISO/IEC 14443 A
Anticollision (Broken Bytes) Operation
(Transponder Emulation or NFC Passive Target)
• Input Voltage Range: 2.7 VDC to 5.5 VDC
• Programmable Output Power: +20 dBm (100 mW),
+23 dBm (200 mW)
• Programmable I/O Voltage Levels From 1.8 VDC
to 5.5 VDC
• Programmable System Clock Frequency Output
(RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz
Crystal or Oscillator
• Integrated Voltage Regulator Output for Other
System Components (MCU, Peripherals,
Indicators), 20 mA (Max)
• Programmable Modulation Depth
• Dual Receiver Architecture With RSSI for
Elimination of "Read Holes" and Adjacent Reader
System or Ambient In-Band Noise Detection
• Programmable Power Modes for Ultra Low-Power
System Design (Power Down <1 µA)
• Parallel or SPI Interface (With 127-Byte FIFO)
• Temperature Range: –40°C to 110°C
• 32-Pin QFN Package (5 mm × 5 mm)
1.2 Applications
• Mobile Devices (Tablets, Handsets)
• Secure Pairing ( Bluetooth®, Wi-Fi®, Other Paired
Wireless Networks)
• Public Transport or Event Ticketing
• Passport or Payment (POS) Reader Systems
• Short-Range Wireless Communication Tasks
(Firmware Updates)
• Product Identification or Authentication
• Medical Equipment or Consumables
• Access Control, Digital Door Locks
• Sharing of Electronic Business Cards
1.3 Description
The TRF7970A device is an integrated analog front end (AFE) and multiprotocol data-framing device for a
13.56-MHz NFC/RFID system supporting all three NFC operation modes – reader/writer, peer-to-peer, and
card emulation according to ISO/IEC 14443 A and B, Sony FeliCa, ISO/IEC 15693, NFCIP-1
(ISO/IEC 18092), and NFCIP-2 (ISO/IEC 21481). Built-in programming options make the device suitable
for a wide range of applications for NFC, proximity, and vicinity identification systems.
The device is configured by selecting the desired protocol in the control registers. Direct access to all
control registers allows fine tuning of various reader parameters as needed.
The TRF7970A device supports data rates up to 848 kbps with all framing and synchronization tasks for
the ISO protocols onboard. The TRF7970A device also supports reader and writer mode for NFC Forum
tag types 1, 2, 3, 4, and 5. Other standards and even custom protocols can be implemented by using one
of the direct modes the device offers. These direct modes let the user fully control the AFE and also gain
access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated
(extracted) clock signal.

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Device Overview Copyright © 2011–2017, Texas Instruments Incorporated
The receiver system has a dual-input receiver architecture to maximize communication robustness. The
receivers also include various automatic and manual gain control options. The received signal strength
from transponders, ambient sources, or internal levels is available in the RSSI register.
A SPI or parallel interface can be used for the communication between the MCU and the TRF7970A
device. When the built-in hardware encoders and decoders are used, transmit and receive functions use a
127-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be
bypassed so the MCU can process the data in real time.
The TRF7970A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication
levels from 1.8 V to 5.5 V for the MCU I/O interface.
The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm)
equivalent into a 50-Ωload when using a 5-V supply and supports OOK and ASK modulation with
selectable modulation depth.
The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and
additional external circuits within the reader system.
Integrated RF field detector with programmable wake-up levels, eight selectable power modes, and ultra-
low power operation enable easy development of robust and cost-efficient designs for long battery life.
Start evaluating the TRF7970A multiprotocol transceiver IC with the TRF7970AEVM,TRF7970ATB, or
DLP-7970ABP.
Device Information
PART NUMBER PACKAGE BODY SIZE
TRF7970ARHB VQFN (32) 5 mm × 5 mm

MUX
RX_IN1
RX_IN2
Phase and
Amplitude
Detector
Gain RSSI
(AUX)
Logic
Level Shifter
State
Control
Logic
(Control
Registers and
Command
Logic)
127-Byte
FIFO
MCU
Interface
VDD_I/O
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
IRQ
SYS_CLK
DATA_CLK
ISO
Protocol
Handling Decoder
RSSI
(External)
Gain
RSSI
(Main)
Filter
and AGC Digitizer
Bit
Framing
Framing
Serial
Conversion
CRC and Parity
Transmitter
Analog Front End
TX_OUT
VDD_PA
VSS_PA
Digital Control
State Machine
Crystal or Oscillator
Timing System
EN
EN2
ASK/OOK
MOD
OSC_IN
OSC_OUT
Voltage Supply Regulator Systems
(Supply Regulators and Reference Voltages)
VSS_A
VSS_RF
VDD_RF
VDD_X
VSS_D
VSS
VIN
VDD_A
BAND_GAP
RF Level
Detector
Phase and
Amplitude
Detector
Copyright © 2017, Texas Instruments Incorporated
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Device OverviewCopyright © 2011–2017, Texas Instruments Incorporated
1.4 Functional Block Diagram
Figure 1-1 shows the block diagram.
Figure 1-1. Block Diagram

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Table of Contents Copyright © 2011–2017, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 3
2 Revision History ......................................... 5
3 Device Characteristics.................................. 7
3.1 Related Products ..................................... 7
4 Terminal Configuration and Functions.............. 8
4.1 Pin Diagram .......................................... 8
4.2 Signal Descriptions................................... 8
5 Specifications........................................... 10
5.1 Absolute Maximum Ratings ........................ 10
5.2 ESD Ratings ........................................ 10
5.3 Recommended Operating Conditions............... 10
5.4 Electrical Characteristics............................ 11
5.5 Thermal Resistance Characteristics ................ 12
5.6 Switching Characteristics ........................... 12
6 Detailed Description ................................... 13
6.1 Overview ............................................ 13
6.2 System Block Diagram.............................. 16
6.3 Power Supplies...................................... 16
6.4 Receiver – Analog Section.......................... 22
6.5 Receiver – Digital Section........................... 23
6.6 Oscillator Section ................................... 28
6.7 Transmitter – Analog Section ....................... 29
6.8 Transmitter – Digital Section........................ 30
6.9 Transmitter – External Power Amplifier and
Subcarrier Detector ................................. 31
6.10 TRF7970A IC Communication Interface ............ 31
6.11 TRF7970A Initialization ............................. 49
6.12 Special Direct Mode for Improved MIFARE™
Compatibility......................................... 50
6.13 NFC Modes.......................................... 50
6.14 Direct Commands from MCU to Reader ............ 52
6.15 Register Description................................. 56
7 Applications, Implementation, and Layout........ 76
7.1 TRF7970A Reader System Using SPI With SS
Mode ................................................ 76
7.2 Layout Considerations .............................. 77
7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω...... 77
7.4 Reader Antenna Design Guidelines ................ 78
8 Device and Documentation Support ............... 79
8.1 Getting Started and Next Steps..................... 79
8.2 Device Nomenclature ............................... 79
8.3 Tools and Software ................................. 80
8.4 Documentation Support............................. 80
8.5 Community Resources.............................. 81
8.6 Trademarks.......................................... 81
8.7 Electrostatic Discharge Caution..................... 81
8.8 Glossary............................................. 81
9 Mechanical, Packaging, and Orderable
Information .............................................. 82

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Revision HistoryCopyright © 2011–2017, Texas Instruments Incorporated
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from April 18, 2014 to March 27, 2017 Page
• Corrected the designation of ISO/IEC standards throughout document; for example, changed ISO14443 to
ISO/IEC 14443........................................................................................................................ 1
• Changed the contents of Section 1.3,Description ............................................................................... 1
• Added Section 3.1,Related Products ............................................................................................. 7
• Moved TSTG from Section 5.2 to Section 5.1,Absolute Maximum Ratings.................................................. 10
• Moved Section 5.2 and changed title from Handling Ratings to ESD Ratings.............................................. 10
• Added VOL and VOH to Section 5.4,Electrical Characteristics ................................................................ 11
• Changed the TYP value of the fD_CLKmax parameter from 8 to 4 MHz in Section 5.4,Electrical Characteristics ....... 11
• Throughout document, removed support for application control of Automatic Gain Control (AGC) and Receiver
Gain Adjust, because these features were designed for test functionality and not for production use.................. 13
• Added NFC Type 5 tags to supported list in Section 6.1.1,RFID and NFC Operation – Reader and Writer........... 13
• Removed the paragraph that started "The desired system of operation (bit rate) is achieved by..." from
Section 6.1.2,NFC Device Operation – Initiator ................................................................................ 14
• Removed the paragraph that started "The desired system of operation (bit rate) is achieved by..." from
Section 6.1.3,NFC Device Operation – Target ................................................................................. 14
• Throughout document, changed "tag" emulation or emulator to "card" emulation or emulator........................... 14
• Added the sentence that starts "For interoperability purposes, TI recommends..." in the first bulleted list item in
Section 6.1.3,NFC Device Operation – Target ................................................................................. 15
• Changed POLLING to SENSF_REQ in the bulleted list item that starts "If the first command is a
SENSF_REQ..." and deleted the sentence that started "The POLLING response is sent in..." in Section 6.1.3,
NFC Device Operation – Target................................................................................................... 15
• Updated the bulleted list item that starts "If the first command is ATR_REQ..." in Section 6.1.3,NFC Device
Operation – Target ................................................................................................................. 15
• Changed "coded as ISO14443" to "SENSB_REQ" in the bulleted list item that starts "If the first command is a
SENSB_REQ..." in Section 6.1.3,NFC Device Operation – Target.......................................................... 15
• Changed "FeliCa" to "peer-to-peer" in Section 6.1.3.1,Active Target, and Section 6.1.3.2,Passive Target........... 15
• Updated the paragraph that starts "The transmission of a response must occur after RF collision avoidance..." in
Section 6.1.3.1,Active Target .................................................................................................... 15
• Updated the paragraph that starts "The transmit system in passive target mode..." in Section 6.1.3.2,Passive
Target................................................................................................................................. 15
• Updated the description in Section 6.1.3.3,Card Emulation .................................................................. 16
• Added the sentence that starts "For applications in which the TRF7970A may be subjected..." in the second
paragraph of Section 6.3,Power Supplies....................................................................................... 16
• Changed VDD_A to VDD_X in the last sentence that reads "The VDD_X output current should not exceed 20 mA." in
the NOTE in Analog Supply Regulator: VDD_A................................................................................... 17
• Removed the paragraph that started "The RF power amplifier regulator..." from Digital Supply Regulator: VDD_X .... 17
• Changed 250 mV to 400 mV in "...a "Delta Voltage" of 400 mV below VIN..." .............................................. 17
• Added the paragraph that starts "As VDD_RF is increased, the system..." in Section 6.3.2,Supply Regulator
Settings .............................................................................................................................. 19
• Removed the paragraphs that started "The main receiver also has..." and "By default, the AGC window
comparator..." from Section 6.4.2,Receiver Gain and Filter Stages ........................................................ 22
• Changed Table 6-5 to match Table 6-37......................................................................................... 23
• Updated Section 6.5,Receiver – Digital Section, to clarify and remove duplicate content................................ 23
• Updated the description in Section 6.5.1.2,External RSSI.................................................................... 27
• Removed "Equivalent Series Resistance" from Table 6-9,Minimum Crystal Recommendations........................ 29
• Removed mention of 3-wire SPI and replaced "IRQ" with "Slave Select" in the first paragraph of Section 6.10.1,
General Introduction ................................................................................................................ 31
• Updated the description of FIFO level interrupts in Section 6.10.1.4,FIFO Operation.................................... 35
• Added "but recommended" to "It is optional but recommended to read the FIFO Status register..." in
Section 6.10.3,Reception of Air Interface Data................................................................................. 37
• Changed the title of Section 6.10.4,Data Transmission From MCU to TRF7970A........................................ 38
• Removed the sentence that started "The choice of one of these modes over another..." from Section 6.10.5,
Serial Interface Communication (SPI)............................................................................................ 38
• Updated the paragraph that starts "TI recommends resetting the FIFO after receiving data..." in

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Revision History Copyright © 2011–2017, Texas Instruments Incorporated
Section 6.10.5.1,Serial Interface Mode With Slave Select (SS).............................................................. 43
• Added the NOTE that starts "An additional direct mode..." in Section 6.10.6,Direct Mode............................... 44
• Added Section 6.11,TRF7970A Initialization ................................................................................... 49
• Changed the application report that is referenced in Section 6.12,Special Direct Mode for Improved MIFARE™
Compatibility ......................................................................................................................... 50
• Changed POLLING to SENSF_REQ and updated description in the list item that starts "If the first command is a
SENSF_REQ..." ..................................................................................................................... 51
• Updated the description in the list item that starts "If the first command is ATR_REQ..."................................. 51
• Corrected description of B1 Irq_col in Table 6-18,IRQ Status Register (0x0C) for NFC and Card Emulation
Operation: changed from "(as defined in register 0x01)" to "(as defined in register 0x10)" .............................. 52
• Removed mention of collision avoidance commands from Section 6.13.2,Initiator........................................ 52
• Added and updated comments in Table 6-19,Address and Command Word Bit Distribution............................ 52
• Removed command code 0x15, Close Slot Sequence, from Table 6-19,Address and Command Word Bit
Distribution .......................................................................................................................... 52
• Added the sentence that starts "This command should be sent after a Software Initialization command..." in
Section 6.14.1.1,Idle (0x00)....................................................................................................... 53
• Changed the description in Section 6.14.1.3,Initial RF Collision Avoidance (0x04)....................................... 54
• Changed the description in Section 6.14.1.4,Response RF Collision Avoidance (0x05) ................................. 54
• Changed the description in Section 6.14.1.5,Response RF Collision Avoidance (0x06, n = 0) ......................... 54
• Added "This is used by the ISO/IEC 15693 protocol" to Section 6.14.1.11,Transmit Next Time Slot (0x14).......... 55
• Corrected description of B1 Irq_col in Table 6-43,IRQ Status Register (0x0C): changed from "(as defined in
register 0x01)" to "(as defined in register 0x10)" ............................................................................... 67
• Changed the description of B5:B3 in Table 6-47 from "...Auxiliary RSSI represents the signal level at RX_IN2" to
"...Auxiliary RSSI represents the signal level at RX_IN1"...................................................................... 69
• Removed former Section 7.1, TRF7970A Reader System Using Parallel Microcontroller Interface..................... 76
• Changed Figure 7-1,Application Schematic – SPI With SS Mode MCU Interface ........................................ 76
• Updated the description in Section 7.1.2,Schematic .......................................................................... 76
• Added Section 8.1,Getting Started and Next Steps ........................................................................... 79
• Added Section 8.2,Device Nomenclature ....................................................................................... 79
• Added Section 8.3,Tools and Software.......................................................................................... 80
• Updated Section 8.4,Documentation Support .................................................................................. 80

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Device CharacteristicsCopyright © 2011–2017, Texas Instruments Incorporated
(1) 848 kbps applies to reader/writer mode only.
3 Device Characteristics
Table 3-1 lists the supported modes of operation for the TRF7970A device.
Table 3-1. Supported Modes of Operation
P2P INITIATOR OR READER/WRITER CARD EMULATION P2P TARGET
TECHNOLOGY BIT RATE
(kbps) TECHNOLOGY BIT RATE (kbps) TECHNOLOGY BIT RATE (kbps)
NFC-A and NFC-B
(ISO/IEC 14443 A and B) 106, 212, 424, 848(1) NFC-A, NFC-B 106 NFC-A 106
NFC-F (JIS: X6319-4) 212, 424 N/A N/A NFC-F 212, 424
NFC-V (ISO/IEC 15693) 6.7, 26.7 N/A N/A N/A N/A
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Wireless Connectivity Connect more with the industry’s broadest wireless connectivity
portfolio.
Products for NFC / RFID TI provides one of the industry’s most differentiated NFC and RFID product
portfolios and is your solution to meet a broad range of NFC connectivity and RFID
identification needs.
Companion Products for TRF7970A Review products that are frequently purchased or used with this
product.
Reference Designs for TRF7970A The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.

VDD_A
VIN
VDD_RF
VDD_PA
TX_OUT
VSS_PA
VSS_RX
RX_IN1
I/O_7
RX_IN2 VSS BG
ASK/OOK
IRQ MOD VSS_A VDD_I/O
Pad
VDD_X
OSC_IN
OSC_OUT
VSS_D
EN
SYS_CLK
DATA_CLK
EN2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
I/O_6
I/O_5
I/O_4
I/O_3
I/O_2
I/O_1
I/O_0
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Terminal Configuration and Functions Copyright © 2011–2017, Texas Instruments Incorporated
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output
4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the pinout for the 32-pin RHB package.
Figure 4-1. 32-Pin RHB Package (Top View)
4.2 Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Terminal Functions
TERMINAL TYPE (1) DESCRIPTION
NAME NO.
VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
VIN 2 SUP External supply input to chip (2.7 V to 5.5 V)
VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4)
VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)
TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V)
VSS_PA 6 SUP Negative supply for PA; normally connected to circuit ground
VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground
RX_IN1 8 INP Main RX input
RX_IN2 9 INP Auxiliary RX input
VSS 10 SUP Chip substrate ground
BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference
ASK/OOK 12 BID Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 or 1.
Can be configured as an output to provide the received analog signal output.

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Terminal Configuration and FunctionsCopyright © 2011–2017, Texas Instruments Incorporated
Table 4-1. Terminal Functions (continued)
TERMINAL TYPE (1) DESCRIPTION
NAME NO.
IRQ 13 OUT Interrupt request
MOD 14 INP External data modulation input for direct mode 0 or 1
OUT Subcarrier digital data output (see registers 0x1A and 0x1B)
VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND
VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.
I/O_0 17 BID I/O pin for parallel communication
I/O_1 18 BID I/O pin for parallel communication
I/O_2 19 BID I/O pin for parallel communication
TX enable (in special direct mode)
I/O_3 20 BID I/O pin for parallel communication
TX data (in special direct mode)
I/O_4 21 BID I/O pin for parallel communication
Slave select signal in SPI mode
I/O_5 22 BID I/O pin for parallel communication
Data clock output in direct mode 1 and special direct mode
I/O_6 23 BID I/O pin for parallel communication MISO for serial communication (SPI)
Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0
I/O_7 24 BID I/O pin for parallel communication.
MOSI for serial communication (SPI)
EN2 25 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power
down mode 2 (for example, to supply the MCU).
DATA_CLK 26 INP Data clock input for MCU communication (parallel and serial)
SYS_CLK 27 OUT
If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal
that is used, options are as follows (see register 0x09):
13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz
27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode).
VSS_D 29 SUP Negative supply for internal digital circuits
OSC_OUT 30 OUT Crystal or oscillator output
OSC_IN 31 INP Crystal or oscillator input
OUT Crystal oscillator output
VDD_X 32 OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example,
an MCU)
Thermal Pad PAD SUP Chip substrate ground

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Specifications Copyright © 2011–2017, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to substrate ground terminal VSS.
(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability or lifetime of the device.
5 Specifications
5.1 Absolute Maximum Ratings(1) (2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN Input voltage range –0.3 6 V
IIN Maximum current VIN 150 mA
TJMaximum operating virtual junction temperature Any condition 140 °C
Continuous operation, long-term reliability(3) 125 °C
TSTG Storage temperature –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
5.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all
pins(2) ±500 V
Machine model (MM) ±200 V
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
VIN Operating input voltage 2.7 5 5.5 V
TAOperating ambient temperature –40 25 110 °C
TJOperating virtual junction temperature –40 25 125 °C
VIL Input voltage, logic low I/O lines, IRQ, SYS_CLK, DATA_CLK,
EN, EN2, ASK/OOK, MOD 0.2 × VDD_I/O V
VIH Input voltage threshold, logic high I/O lines, IRQ, SYS_CLK, DATA_CLK,
EN, EN2, ASK/OOK, MOD 0.8 × VDD_I/O V

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SpecificationsCopyright © 2011–2017, Texas Instruments Incorporated
(1) Antenna driver output resistance
(2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.
(3) Depends on the crystal parameters and components
(4) TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω(12-ns time constant when 30-pF load used).
5.4 Electrical Characteristics
TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOL Low-level output voltage 0.2 ×
VDD_I/O V
VOH High-level output voltage 0.8 ×
VDD_I/O V
IPD1 Supply current in power down mode 1 All building blocks disabled, including supply-voltage regulators; measured after
500-ms settling time (EN = 0, EN2 = 0) 0.5 5 µA
IPD2 Supply current in power down mode 2
(sleep mode)
The SYS_CLK generator and VDD_X
remain active to support external circuitry;
measured after 100-ms settling time
(EN = 0, EN2 = 1) 120 200 µA
ISTBY Supply current in stand-by mode Oscillator running, supply-voltage regulators in low-consumption mode
(EN = 1, EN2 = x) 1.9 3.5 mA
ION1 Supply current without antenna driver
current Oscillator, regulators, RX and AGC active, TX is off 10.5 14 mA
ION2 Supply current, TX (half power) Oscillator, regulators, RX and AGC and
TX active, POUT = 100 mW 70 78 mA
ION3 Supply current, TX (full power) Oscillator, regulators, RX and AGC and
TX active, POUT = 200 mW 130 150 mA
VPOR Power-on-reset voltage Input voltage at VIN 1.4 2 2.6 V
VBG Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V
VDD_A Regulated output voltage for analog
circuitry (pin 1) VIN = 5 V 3.1 3.4 3.8 V
VDD_X Regulated supply for external circuitry Output voltage pin 32, VIN = 5 V 3.1 3.4 3.8 V
IVDD_Xmax Maximum output current of VDD_X Output current pin 32, VIN = 5 V 20 mA
RRFOUT Antenna driver output resistance (1) Half-power mode, VIN = 2.7 V to 5.5 V 8 12 Ω
Full-power mode, VIN = 2.7 V to 5.5 V 4 6
RRFIN RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ
VRF_INmax Maximum RF input voltage at RX_IN1
and RX_IN2 VRF_INmax should not exceed VIN 3.5 Vpp
VRF_INmin Minimum RF input voltage at RX_IN1
and RX_IN2 (input sensitivity)(2) fSUBCARRIER = 424 kHz 1.4 2.5 mVpp
fSUBCARRIER = 848 kHz 2.1 3
fSYS_CLK SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz
fCCarrier frequency Defined by external crystal 13.56 MHz
tCRYSTAL Crystal run-in time Time until oscillator stable bit is set
(register 0x0F)(3) 3 ms
fD_CLKmax Maximum DATA_CLK frequency(4) Depends on capacitive load on the I/O
lines, TI recommends 2 MHz(4) 2 4 10 MHz
ROUT Output resistance I/O_0 to I/O_7 500 800 Ω
RSYS_CLK Output resistance RSYS_CLK 200 400 Ω

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(1) This data was taken using the JEDEC standard high-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase
substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best
performance and long-term reliability.
5.5 Thermal Resistance Characteristics
PACKAGE θJC θJA(1) POWER RATING(2)
TA≤25°C TA≤85°C
RHB (32 pin) 31°C/W 36.4°C/W 2.7 W 1.1 W
(1) TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω(12-ns time constant when 30-pF load used).
5.6 Switching Characteristics
TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLO/HI DATA_CLK time high or low, one half of DATA_CLK at
50% duty cycle Depends on capacitive load on the I/O lines(1) 250 62.5 50 ns
tSTE,LEAD Slave select lead time, slave select low to clock 200 ns
tSTE,LAG Slave select lag time, last clock to slave select high 200 ns
tSTE,DIS Slave select disable time, slave select rising edge to
next slave select falling edge 300 ns
tSU,SI MOSI input data setup time 15 ns
tHD,SI MOSI input data hold time 15 ns
tSU,SO MISO input data setup time 15 ns
tHD,SO MISO input data hold time 15 ns
tVALID,SO MISO output data valid time DATA_CLK edge to MISO valid,
CL≤30 pF 30 50 75 ns

TRF7970A MCU
(MSP430 or ARM)
Matching
VDD_X VDD_I/O
TX_OUT
RX_IN 1
RX_IN2 VSS VIN
Parallel
or SPI
Supply: 2.7 V to 5.5 V
VDD
VDD
Crystal
13.56 MHz
XIN
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Detailed DescriptionCopyright © 2011–2017, Texas Instruments Incorporated
6 Detailed Description
6.1 Overview
6.1.1 RFID and NFC Operation – Reader and Writer
The TRF7970A is a high-performance 13.56-MHz HF RFID and NFC transceiver IC composed of an
integrated analog front end (AFE) and a built-in data framing engine for ISO/IEC 15693, ISO/IEC 14443 A
and B, and FeliCa. This includes data rates up to 848 kbps for ISO/IEC 14443 with all framing and
synchronization tasks on board (in default mode). The TRF7970A also supports NFC tag type 1, 2, 3, 4,
and 5 operations. This architecture lets the customer build a complete cost-effective yet high-performance
multiprotocol 13.56-MHz RFID and NFC system together with a low-cost microcontroller.
Other standards and even custom protocols can be implemented by using either of the direct modes that
the device offers. These direct modes (0 and 1) allow the user to fully control the analog front end (AFE)
and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the
associated (extracted) clock signal.
The receiver system has a dual input receiver architecture. The receivers also include various automatic
and manual gain control options. The received input bandwidth can be selected to cover a broad range of
input subcarrier signal options.
The received signal strength from transponders, ambient sources, or internal levels is available through
the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the
integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data
clock as outputs.
The TRF7970A also includes a receiver framing engine. This receiver framing engine performs the CRC
or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO/IEC 14443 A
and B, ISO/IEC 15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU)
through a 127-byte FIFO register.
Figure 6-1. Application Block Diagram
A parallel or serial interface (SPI) can be used for the communication between the MCU and the
TRF7970A reader. When the built-in hardware encoders and decoders are used, transmit and receive
functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and
decoders can be bypassed so that the MCU can process the data in real time. The TRF7970A supports
data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has
selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ωload
when using a 5-V supply.

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The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7970A also
includes a data transmission engine that comprises low-level encoding for ISO/IEC 15693, ISO/IEC 14443
A and B, and FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame
(SOF), End Of Frame (EOF), Cyclic Redundancy Check (CRC), and parity bits.
Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete
reader system. The built-in programmable auxiliary voltage regulator VDD_X (pin 32), is able to deliver up to
20 mA to supply a microcontroller and additional external circuits within the reader system.
6.1.2 NFC Device Operation – Initiator
The transmitting system includes an RF level detector (programmable level) which is used for initial (or
response) RF collision avoidance. The RF collision avoidance sequence is started by sending a direct
command. If successful, the NFC initiator can send the data or commands, the MCU has loaded in the
FIFO register. The coding of this data is done by hardware coders in ISO/IEC 14443 A and B, or FeliCa
format. The coders also provide CRC and parity bits (if required) and automatically add preambles, SOF,
EOF, and synchronization bytes as defined by selected protocol.
The receiver system offers the same analog features (AGC, AM or PM, bandwidth selection, and so on)
as described previously in RFID and NFC reader and writer description. The system comprises integrated
decoders for passive targets (ISO/IEC 14443 A or ISO/IEC 14443 B tag or FeliCa) or active targets
(ISO/IEC 14443 A or ISO/IEC 14443 B reader or FeliCa). For all this options, the system also supports
framing including CRC and parity check and removal of SOF, EOF, and synchronization bytes as
specified by the selected protocol.
6.1.3 NFC Device Operation – Target
The activation of NFC target is done when a sufficient RF field level is detected on the antenna. The level
needed for wake-up is selectable and is stored in a nonvolatile register.
When the activation occurs, the system performs automatic power-up and waits for the first command to
be received. Based on this command, the system knows if it should operate as passive or active target
and at what bit rate. After activation, the receiver system offers the same analog features (for example,
AGC, AM/PM, and bandwidth selection) as in the case of an RFID reader.
When used as the NFC target, the chip is typically in a power down or standby mode. If EN2 = H, the chip
keeps the supply system on. If EN2 = L and EN = L, the chip is in complete power down. To operate as
NFC target or card emulator, the MCU must load a value different from zero (0) in the Target Detection
Level register (B0-B2) to enable the RF measurement system (supplied by VEXT, so it can also operate
during complete power down and consume only 3.5 µA). The RF measurement constantly monitors the
RF signal on the antenna input. When the RF level on the antenna input exceeds the level defined in the
in Target Detection Level register, the chip is automatically activated (EN is internally forced high).
When the voltage supply system and the oscillator are started and are stable, osc_ok goes high (B6 of
RSSI Level and Oscillator Status register) and IRQ is sent with bit B2 = 1 of IRQ register (field change).
Bit B7 NFC Target Protocol in register directly displays the status of RF level detection (running constantly
also during normal operation). This informs the MCU that the chip should start operation as NFC TARGET
device. When the first command from the INITIATOR is received, another IRQ sent with B6 (RX start) set
in the IRQ register. The MCU must set EN = H (confirm the power up) in the time between the two IRQs,
because the internal power-up ends after the second IRQ. The type and coding of the first initiator (or
reader in the case of a card emulator) command defines the communication protocol type that the target
must use. Therefore, the communication protocol type is available in the NFC Target Protocol register
immediately after receiving the first command.

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Based on the first command from the INITIATOR, the following actions are taken:
• If the first command is SENS_REQ or ALL_REQ, the TARGET must enter the SDD protocol for 106-
kbps passive communication to begin; afterward, the baud rate can be changed to 212 kbps or 424
kbps, which is determined by the NFC initiator device. If bit B5 in the NFC Target Detection Level
register is not set, the MCU handles the SDD and the command received is send to FIFO. For
interoperability purposes, TI recommends allowing the MCU to handle the SDD process rather than
use the TRF7970A Auto-SDD feature to ensure interoperability with other NFC devices. If the RF field
is turned off (B7 in NFC Target Protocol register is low) at any time, the system sends an IRQ to the
MCU with bit B2 (RF field change) in the IRQ register set high. This informs the MCU that the
procedure was aborted and the system must be reset. The clock extractor is automatically activated in
this mode.
• If the command is SENS_REQ or ALL_REQ and the card emulation bit in ISO Control register is set,
the system emulates an ISO/IEC 14443 A or ISO/IEC 14443 B tag. The procedure does not differ from
the one previously described for the case of a passive target at 106 kbps. The clock extractor is
automatically activated in this mode.
• If the first command is a SENSF_REQ, the system becomes the TARGET in passive communication
using 212 kbps or 424 kbps. The SDD is relatively simple and is handled by the MCU directly.
• If the first command is ATR_REQ, the system operates as an active TARGET using the same
communication speed and bit coding as used by the INITIATOR. Again, all of the replies are handled
by the MCU. The MCU should handle the timing requirements for collision avoidance. This is done by
using external RSSI to detect external RF fields before enabling RF on the TRF7970A.
• If the first command is a SENSB_REQ request and the card emulation bit is set in the ISO Control
register, the system enters ISO/IEC 14443 B emulation mode. The anticollision must be handled by the
MCU, and the chip provides all physical level coding, decoding, and framing for this protocol.
6.1.3.1 Active Target
If the first command received by the RF interface defines the system as an active target, then the receiver
selects the appropriate data decoders (ISO/IEC 14443 A or ISO/IEC 14443 B reader or peer-to-peer) and
framing option. Only the raw (decoded) data is forwarded to the MCU through the FIFO. SOF, EOF,
preamble, sync bytes, CRC, and parity bytes are checked by the framer and discarded.
The transmission of a response must occur after RF collision avoidance has been processed. The
recommended method for RF collision avoidance is to use external RSSI to detect any external RF field. If
successful, the NFC initiator can send the data that the MCU has loaded in the FIFO register. The coding
of this data is done by hardware coders either in ISO/IEC 14443 A format (106-kbps system) or in peer-to-
peer format for (212-kbps and 424-kbps systems). The coders also provide CRC and parity bits (if
required) and automatically add preambles, SOF, EOF, and synchronization bytes as defined by selected
protocol.
6.1.3.2 Passive Target
If the first command received by the RF interface defines the system as a passive target, then the receiver
selects the appropriate data decoders (ISO/IEC 14443 A or ISO/IEC 14443 B reader or peer-to-peer) and
framing option. Again, only the raw (decoded) data is forwarded to the MCU through the FIFO; SOF, EOF,
preamble, sync bytes, CRC, and parity bytes are checked by the framer and discarded. The receiver
works same as in the case of an active target.
The transmit system in passive target mode differs from active target and operates similar to the standard
tag. There is no RF collision avoidance sequence, and encoders are used to code the data for
ISO/IEC 14443 A or ISO/IEC 14443 B tag (at 106 kbps, to start) or peer-to-peer (at 212 kbps, to start)
format. The coding system adds all of the SOF, EOF, CRC, parity bits, and synchronization bytes that are
required by protocol. The response is transmitted over-the-air with a method known as load modulation.

MUX
RX_IN1
RX_IN2
Phase and
Amplitude
Detector
Gain RSSI
(AUX)
Logic
Level Shifter
State
Control
Logic
(Control
Registers and
Command
Logic)
127-Byte
FIFO
MCU
Interface
VDD_I/O
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
IRQ
SYS_CLK
DATA_CLK
ISO
Protocol
Handling Decoder
RSSI
(External)
Gain
RSSI
(Main)
Filter
and AGC Digitizer
Bit
Framing
Framing
Serial
Conversion
CRC and Parity
Transmitter
Analog Front End
TX_OUT
VDD_PA
VSS_PA
Digital Control
State Machine
Crystal or Oscillator
Timing System
EN
EN2
ASK/OOK
MOD
OSC_IN
OSC_OUT
Voltage Supply Regulator Systems
(Supply Regulators and Reference Voltages)
VSS_A
VSS_RF
VDD_RF
VDD_X
VSS_D
VSS
VIN
VDD_A
BAND_GAP
RF Level
Detector
Phase and
Amplitude
Detector
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6.1.3.3 Card Emulation
The chip can enter this mode by setting appropriate option bits. The chip can emulate ISO/IEC 14443 A
and B card types. For ISO/IEC 14443 A and B, the emulation supports 106-kbps data rate to start. For
ISO/IEC 14443 A, the anticollision algorithm can be performed using an internal state machine, which
relieves the MCU of any real-time tasks; however, this method can present interoperability challenges with
other NFC devices due to timing requirements. To ensure best interoperability, TI recommends allowing
the MCU to manage the anticollision process, instead. The unique ID required for anticollision is provided
by the MCU after wakeup of the system.
6.2 System Block Diagram
Figure 6-2 shows a block diagram of the TRF7970A.
Figure 6-2. System Block Diagram
6.3 Power Supplies
The TRF7970A positive supply input VIN (pin 2) sources three internal regulators with output voltages
VDD_RF, VDD_A and VDD_X. All regulators use external bypass capacitors for supply noise filtering and must
be connected as indicated in reference schematics. These regulators provide a high power supply reject
ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN (pin 2).
The regulators are not independent and have common control bits in register 0x0B for output voltage
setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B,
bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the
highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode
allows the user to manually configure the regulator settings. For applications in which the TRF7970A may
be subjected to external noise, manually reducing the regulator settings can improve RF performance.

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6.3.1 Supply Arrangements
Regulator Supply Input: VIN
The positive supply at VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. VIN provides the supply
input sources for three internal regulators with the output voltages VDD_RF, VDD_A, and VDD_X. External
bypass capacitors for supply noise filtering must be used (per reference schematics).
NOTE
VIN must be the highest voltage supplied to the TRF7970A.
RF Power Amplifier Regulator: VDD_RF
The VDD_RF (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for
either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per
reference schematics). When configured for 5-V manual-operation, the VDD_RF output voltage can be set
from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to
3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V
operation is 100 mA.
Analog Supply Regulator: VDD_A
Regulator VDD_A (pin 1) supplies the analog circuits of the device. The output voltage setting depends on
the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation,
the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per
reference schematics). When configured for 3-V manual-operation, the VDD_A output can be set from 2.7 V
to 3.4 V in 100-mV steps (see Table 6-2).
NOTE
The configuration of VDD_A and VDD_X regulators are not independent from each other. The
VDD_X output current should not exceed 20 mA.
Digital Supply Regulator: VDD_X
The digital supply regulator VDD_X (pin 32) provides the power for the internal digital building blocks and
can also be used to supply external electronics within the reader system. When configured for 3-V
operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for
supply noise filtering must be used (per reference schematics).
NOTE
The configuration of the VDD_A and VDD_X regulators are not independent from each other.
The VDD_X output current should not exceed 20 mA.
By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are
automatically set every time the system is activated by setting EN input High or each time the automatic
regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This
means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit
is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.
By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 400 mV below
VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_A.

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Power Amplifier Supply: VDD_PA
The power amplifier of the TRF7970A is supplied through VDD_PA (pin 4). The positive supply pin for the
RF power amplifier is externally connected to the regulator output VDD_RF (pin 3).
I/O Level Shifter Supply: VDD_I/O
The TRF7970A has a separate supply input VDD_I/O (pin 16) for the built-in I/O level shifter. The supported
input voltage ranges from 1.8 V to VIN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins
(I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is
directly connected to VDD_X, while VDD_X also supplies the MCU. This ensures that the I/O signal levels of
the MCU match the logic levels of the TRF7970A.
Negative Supply Connections: VSS, VSS_TX, VSS_RX, VSS_A, VSS_PA
The negative supply connections VSS_X of each functional block are all externally connected to GND.
The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative
supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the negative supply for
the RF receiver VSS_RX (pin 7).

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(1) x = Don't care
6.3.2 Supply Regulator Settings
The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control
register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default
configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply
voltage is below 4.3 V, the 3-V configuration should be used.
As VDD_RF is increased, the system can become more susceptible to noise coupling on the RX lines. For
minimum noise coupling, TI recommends using the value of 0x00. For improved range, higher VDD_RF
voltages may be set, but complete system testing is required to determine the value which provides
optimal performance.
The various regulators can be configured to operate in automatic or manual mode. This is done in the
Regulator and I/O Control register (0x0B), as shown in Table 6-1 and Table 6-2.
Table 6-1. Supply Regulator Setting: 5-V System
REGISTER
ADDRESS
(hex)
OPTION BITS SETTING IN REGULATOR CONTROL REGISTER (1)
COMMENTS
B7 B6 B5 B4 B3 B2 B1 B0
Automatic Mode (default)
0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference
Manual Mode
0B 0 x x x x 1 1 1 VDD_RF = 5 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.4 V, VDD_X = 3.4 V
(1) x = Don't care
Table 6-2. Supply Regulator Setting: 3-V System
REGISTER
ADDRESS
(hex)
OPTION BITS SETTING IN REGULATOR CONTROL REGISTER (1)
COMMENTS
B7 B6 B5 B4 B3 B2 B1 B0
Automatic Mode (default)
0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference
Manual Mode
0B 0 x x x x 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V
0B 0 x x x x 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V
0B 0 x x x x 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V
0B 0 x x x x 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V
0B 0 x x x x 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V
0B 0 x x x x 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V
0B 0 x x x x 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V
0B 0 x x x x 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V
The regulator configuration function adjusts the regulator outputs by default to 400 mV below VIN level, but
not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible supply
voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).

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(1) X = Don't care
6.3.3 Power Modes
The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits
in the chip status control register (0x00) (see Table 6-3 and Table 6-4).
Table 6-3. 3.3-V Operation Power Modes(1)
MODE EN2 EN
CHIP
STATUS
CONTROL
REGISTER
(0x00)
REGULATOR
CONTROL
REGISTER
(0x0B)
TRANSMITTER RECEIVER SYS_CLK
(13.56 MHz) SYS_CLK (60 kHz) VDD_X
TYPICAL
CURRENT
(mA)
TYPICAL
POWER
OUT (dBm)
Power down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 -
Sleep mode 1 0 XX XX OFF OFF OFF ON ON 0.120 -
Standby mode at +3.3 VDC X 1 80 00 OFF OFF ON X ON 2 -
Mode 1 at +3.3 VDC X 1 00 00 OFF OFF ON X ON 3 -
Mode 2 at +3.3 VDC X 1 02 00 OFF ON ON X ON 9 -
Mode 3 (half power) at
+3.3 VDC X 1 30 07 ON ON ON X ON 53 14.5
Mode 4 (full power) at
+3.3 VDC X 1 20 07 ON ON ON X ON 67 17
(1) X = Don't care
Table 6-4. 5-V Operation Power Modes(1)
MODE EN2 EN
CHIP
STATUS
CONTROL
REGISTER
(0x00)
REGULATOR
CONTROL
REGISTER
(0x0B)
TRANSMITTER RECEIVER SYS_CLK
(13.56 MHz) SYS_CLK (60 kHz) VDD_X
TYPICAL
CURRENT
(mA)
TYPICAL
POWER
OUT (dBm)
Power down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 -
Sleep mode 1 0 XX XX OFF OFF OFF ON ON 0.120 -
Standby mode at +5 VDC X 1 81 07 OFF OFF ON X ON 3 -
Mode 1 at +5 VDC X 1 01 07 OFF OFF ON X ON 5 -
Mode 2 at +5 VDC X 1 03 07 OFF ON ON X ON 10.5 -
Mode 3 (half power) at
+5 VDC X 1 31 07 ON ON ON X ON 70 20
Mode 4 (full power) at
+5 VDC X 1 21 07 ON ON ON X ON 130 23
Table 6-3 and Table 6-4 show the configuration for the different power modes when using a 3.3-V or 5-V
system supply, respectively. The main reader enable signal is pin EN. When EN is set high, all of the
reader regulators are enabled, the 13.56-MHz oscillator is running and the SYS_CLK (output clock for
external microcontroller) is also available.
The input pin EN2 has two functions:
• A direct connection from EN2 to VIN to ensure the availability of the regulated supply VDD_X and an
auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is
intended for systems in which the MCU is also being supplied by the reader supply regulator (VDD_X)
and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and
clock to be available during sleep mode.
• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this
case the EN input is being controlled by the MCU (or other system device) that is without supply
voltage during complete power down (thus unable to control the EN input). A rising edge applied to the
EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56-
MHz oscillator (identical to condition EN = 1).
When user MCU is controlling EN and EN2, a delay of 1 ms between EN and EN2 must be used. If the
MCU controls only EN, TI recommends connecting EN2 to either VIN or GND, depending on the
application MCU requirements for VDD_X and SYS_CLK.