Texas Instruments CC1021 User manual

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC1021
SWRS045F –JANUARY 2006–REVISED NOVEMBER 2018
CC1021 Single-Chip Low-Power RF Transceiver for Narrowband Systems
Not Recommended for New Designs NRND
1 Device Overview
1
1.1 Features
1
• True Single-Chip UHF RF Transceiver
• Frequency Range 402 MHz to 470 MHz and
804 MHz to 930 MHz
• High Sensitivity
– Up to –112 dBm for 38.4 kHz Receiver Channel
Filter Bandwidth
– Up to –106 dBm for 102.4 kHz Receiver
Channel Filter Bandwidth
• Programmable Output Power
• Low Current Consumption
– RX: 19.9 mA
• Low Supply Voltage
– From 2.3 V to 3.6 V
• Very Few External Components Required
• Small Size
– QFN 32 Package
• Pb-Free Package
• Digital RSSI and Carrier Sense Indicator
• Data Rate Up to 153.6 kBaud
• OOK, FSK, and GFSK Data Modulation
• Integrated Bit Synchronizer
• Image Rejection Mixer
• Programmable Frequency
• Automatic Frequency Control (AFC)
• Suitable for Frequency Hopping Systems
• Suited for Systems Targeting Compliance With
EN 300 220 and FCC CFR47 Part 15
• Easy-to-Use Software for Generating the CC1021
Configuration Data
• Fully Compatible With CC1020 for Receiver
Channel Filter Bandwidths of 38.4 kHz and Higher
1.2 Applications
• Low-Power UHF Wireless Data Transmitters and
Receivers With Channel Spacings
of 50 kHz or Higher
• 433-, 868-, 915-, 930-MHz ISM/SRD Band
Systems
• AMR – Automatic Meter Reading
• Wireless Alarm and Security Systems
• Home Automation
• Low-Power Telemetry
• Automotive (RKE/TPMS)
1.3 Description
The CC1021 device is a true single-chip UHF transceiver designed for very low power and very low
voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical)
and SRD (Short Range Device) frequency bands at 433 MHz, 868 MHz, and 915 MHz, but can easily be
programmed for multichannel operation at other frequencies in the 402- to 470-MHz and 804- to 930-MHz
range.
The CC1021 device is especially suited for narrowband systems with channel spacing of 50 kHz and
higher complying with EN 300 220 and CC CFR47 part 15.
The CC1021 device main operating parameters can be programmed through a serial bus, thus making the
CC1021 device a very flexible and easy to use transceiver.
In a typical system, the CC1021 device is used together with a microcontroller and a few external passive
components.
(1) For more information, see Section 8,Mechanical Packaging and Orderable Information.
Table 1-1. Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
CC1021 VQFNP (32) 7.00 mm × 7.00 mm

DIO
LOCK
DCLK
RF_IN LNA
FREQ
SYNTH
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
BIAS
Power
Control
DIGITAL
INTERFACE
TO mC
CONTROL
LOGIC
PA
ADC
ADC
RF_OUT
R_BIAS XOSC_Q1 XOSC_Q2
PDO
XOSC
VC CHP_OUT
LNA 2
0
90 :2
0
90 :2
Multiplexer
Multiplexer
PA_EN LNA_EN
PCLK
PDI
PSEL
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1.4 Functional Block Diagram
Figure 1-1 shows the system block diagram of the CC1021 device.
Figure 1-1. Functional Block Diagram

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Revision HistoryCopyright © 2006–2018, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 2
2 Revision History ......................................... 3
3 Terminal Configuration and Functions.............. 4
3.1 Pin Diagram .......................................... 4
3.2 Pin Configuration ..................................... 4
4 Specifications ............................................ 6
4.1 Absolute Maximum Ratings .......................... 6
4.2 ESD Ratings.......................................... 6
4.3 Recommended Operating Conditions................ 6
4.4 RF Transmit .......................................... 6
4.5 RF Receive........................................... 8
4.6 RSSI / Carrier Sense................................ 10
4.7 Intermediate Frequency (IF) ........................ 11
4.8 Crystal Oscillator.................................... 11
4.9 Frequency Synthesizer.............................. 12
4.10 Digital Inputs / Outputs.............................. 12
4.11 Current Consumption ............................... 13
4.12 Thermal Resistance Characteristics for VQFNP
Package ............................................. 14
5 Detailed Description ................................... 15
5.1 Overview ............................................ 15
5.2 Functional Block Diagram........................... 15
5.3 Configuration Overview ............................. 16
5.4 Microcontroller Interface............................. 17
5.5 4-wire Serial Configuration Interface................ 18
5.6 Signal Interface...................................... 20
5.7 Data Rate Programming ............................ 22
5.8 Frequency Programming............................ 24
5.9 Receiver............................................. 25
5.10 Transmitter .......................................... 38
5.11 Input and Output Matching and Filtering............ 40
5.12 Frequency Synthesizer.............................. 44
5.13 VCO and LNA Current Control...................... 48
5.14 Power Management................................. 48
5.15 On-Off Keying (OOK) ............................... 50
5.16 Crystal Oscillator.................................... 51
5.17 Built-in Test Pattern Generator ..................... 53
5.18 Interrupt on Pin DCLK............................... 54
5.19 PA_EN and LNA_EN Digital Output Pins ........... 54
5.20 System Considerations and Guidelines............. 55
5.21 Antenna Considerations............................. 58
5.22 Configuration Registers ............................. 59
6 Applications, Implementation, and Layout........ 78
6.1 Application Information.............................. 78
6.2 Design Requirements ............................... 80
6.3 PCB Layout Guidelines ............................. 81
7 Device and Documentation Support ............... 82
7.1 Device Support...................................... 82
7.2 Documentation Support ............................. 82
7.3 Trademarks.......................................... 83
7.4 Electrostatic Discharge Caution..................... 83
7.5 Export Control Notice ............................... 83
7.6 Glossary............................................. 83
8 Mechanical Packaging and Orderable
Information .............................................. 83
8.1 Packaging Information .............................. 83
2 Revision History
Changes from August 20, 2016 to November 30, 2018 Page
• Global: Changed upper frequency from 960 MHz to 930 MHz................................................................. 1
• Global: Removed references to ARIB STD-T96.................................................................................. 1

PCLK 1VC
24 AVDD
23 AVDD
22 RF_OUT
21 AVDD
20 RF_IN
19 AVDD
18 R_BIAS
17
AVDD
16
PA_EN
15
LNA_EN
14
AVDD
13
AVDD
12
XOSC_Q2
11
XOSC_Q1
10
LOCK
9
DIO 8
DCLK 7
DGND 6
DVDD 5
DGND 4
PDO 3
PDI 2
32
PSEL
31
DVDD
30
DGND
29
AVDD
28
CHP_OUT
27
AVDD
26
AD_REF
25
AGND
AGND
Exposed die
attached pad
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Terminal Configuration and Functions Copyright © 2006–2018, Texas Instruments Incorporated
(1) DCLK, DIO and LOCK are high-impedance (3-state) in power down (BIAS_PD = 1 in the MAIN register).
(2) The exposed die attached pad must be soldered to a solid ground plane as this is the main ground connection for the chip.
3 Terminal Configuration and Functions
3.1 Pin Diagram
Figure 3-1 shows pin names and locations for the CC1021 device.
Figure 3-1. Package 7-mm × 7-mm VQFNP (Top View)
3.2 Pin Configuration
Table 3-1. Pin Attributes(1)(2)
PIN NO. PIN NAME TYPE DESCRIPTION
— AGND Ground (analog) Exposed die attached pad. Must be soldered to a solid ground plane as this is the
ground connection for all analog modules. See Section 6.3 for more details.
1 PCLK Digital input Programming clock for SPI configuration interface
2 PDI Digital input Programming data input for SPI configuration interface
3 PDO Digital output Programming data output for SPI configuration interface
4 DGND Ground (digital) Ground connection (0 V) for digital modules and digital I/O
5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O
6 DGND Ground (digital) Ground connection (0 V) for digital modules (substrate)
7 DCLK Digital output Clock for data in both receive and transmit mode
Can be used as receive data output in asynchronous mode
8 DIO Digital input/output Data input in transmit mode; data output in receive mode
Can also be used to start power-up sequencing in receive
9 LOCK Digital output PLL Lock indicator, active low. Output is asserted (low) when PLL is in lock. The pin can also be used as a general digital output, or as receive data output in
synchronous NRZ/Manchester mode
10 XOSC_Q1 Analog input Crystal oscillator or external clock input
11 XOSC_Q2 Analog output Crystal oscillator
12 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator
13 AVDD Power (analog) Power supply (3 V typical) for the IF VGA
14 LNA_EN Digital output General digital output. Can be used for controlling an external LNA if higher
sensitivity is needed.
15 PA_EN Digital output General digital output. Can be used for controlling an external PA if higher output
power is needed.

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Table 3-1. Pin Attributes(1)(2) (continued)
PIN NO. PIN NAME TYPE DESCRIPTION
16 AVDD Power (analog) Power supply (3 V typical) for global bias generator and IF anti-alias filter
17 R_BIAS Analog output Connection for external precision bias resistor (82 kΩ, ±1%)
18 AVDD Power (analog) Power supply (3 V typical) for LNA input stage
19 RF_IN RF Input RF signal input from antenna (external AC-coupling)
20 AVDD Power (analog) Power supply (3 V typical) for LNA
21 RF_OUT RF output RF signal output to antenna
22 AVDD Power (analog) Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA stage
23 AVDD Power (analog) Power supply (3 V typical) for VCO
24 VC Analog input VCO control voltage input from external loop filter
25 AGND Ground (analog) Ground connection (0 V) for analog modules (guard)
26 AD_REF Power (analog) 3 V reference input for ADC
27 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector
28 CHP_OUT Analog output PLL charge pump output to external loop filter
29 AVDD Power (analog) Power supply (3 V typical) for ADC
30 DGND Ground (digital) Ground connection (0 V) for digital modules (guard)
31 DVDD Power (digital) Power supply connection (3 V typical) for digital modules
32 PSEL Digital input Programming chip select, active low, for configuration interface. Internal pullup
resistor.

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Specifications Copyright © 2006–2018, Texas Instruments Incorporated
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD_020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”.
4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT CONDITION
Supply voltage, VDD –0.3 5 V All supply pins must have the same
voltage
Voltage on any pin –0.3 VDD + 0.3, max 5.0 V
Input RF level 10 dBm
Package body temperature 260 °C Norm: IPC/JEDEC J-STD-020(2)
Humidity non-condensing 5% 85%
Storage temperature range, Tstg –50 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) According to JEDEC STD 22, method A114, Human Body Model
4.2 ESD Ratings
VALUE UNIT
VESD Electrostatic discharge (ESD)
performance:
Human Body Model (HBM), per
ANSI/ESDA/JEDEC JS001(1)(2) All pads except RF ±1 kV
RF Pads ±0.4 kV
Charged Device Model (CDM) 250 V
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT CONDITION
RF Frequency Range 402 470 MHz Programmable in < 300 Hz steps
804 930 MHz Programmable in < 600 Hz steps
Operating ambient temperature range –40 85 °C
Supply voltage 2.3 3.0 3.6 V The same supply voltage should be used for digital
(DVDD) and analog (AVDD) power.
4.4 RF Transmit
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Transmit data rate 0.45 153.6 kBaud
Minimum data rate for OOK is
2.4 kBaud NRZ or Manchester
encoding can be used. 153.6 kBaud
equals 153.6 kbps using NRZ coding
and 76.8 kbps using Manchester
coding. See Section 5.4.2 for details
The data rate is programmable. See
Section 5.7 for details.
Binary FSK
frequency
separation
in 402 to 470 MHz range 0 108 kHz 108/216 kHz is the maximum
specified separation at 1.84 MHz
reference frequency. Larger
separations can be achieved at
higher reference frequencies.
in 804 to 930 MHz range 0 216 kHz

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RF Transmit (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Output power
433 MHz –20 to +10 dBm Delivered to 50 Ωsingle-ended load.
The output power is programmable
and should not be programmed to
exceed +10/+5 dBm at 433/868 MHz
under any operating conditions. See
Section 5.11 for details.
868 MHz –20 to +5 dBm
Output power
tolerance At 2.3 V, +85°C –4 dB At maximum output power
At 3.6 V, –40°C 3 dB
Harmonics,
radiated CW
2nd harmonic, 433 MHz,
+10 dBm –50 dBc
Harmonics are measured as EIRP
values according to EN 300 220. The
antenna (SMAFF-433 and SMAFF-
868 from R.W. Badland) plays a part
in attenuating the harmonics.
3rd harmonic, 433 MHz,
+10 dBm –50 dBc
2nd harmonic, 868 MHz,
+5 dBm –50 dBc
3rd harmonic, 868 MHz,
+5 dBm –50 dBc
Adjacent channel
power (GFSK)
433 MHz –46 dBc ACP is measured in a 100 kHz
bandwidth at ±100 kHz offset.
Modulation: 19.2 kBaud NRZ PN9
sequence, ±19.8 kHz frequency
deviation.
868 MHz –42 dBc
Occupied
bandwidth
(99.5%,GFSK)
433 MHz 60 kHz Bandwidth for 99.5% of total average
power.
Modulation: 19.2 kBaud NRZ PN9
sequence, ±19.8 kHz frequency
deviation.
868 MHz 60 kHz
Modulation
bandwidth,
868 MHz
19.2 kBaud, ±9.9 kHz
frequency deviation 48 kHz Bandwidth where the power
envelope of modulation equals
–36 dBm. Spectrum analyzer
RBW = 1 kHz.
38.4 kBaud, ±19.8 kHz
frequency deviation 106 kHz
Spurious emission,
radiated CW
47 to 74 MHz,
87.5 to 118 MHz,
174 to 230 MHz,
470 to 862 MHz –54 dBm At maximum output power,
+10/+5 dBm at 433/868 MHz.
To comply with EN 300 220 and FCC
CFR47 part 15, an external
(antenna) filter, as implemented in
the application circuit in Figure 5-22,
must be used and tailored to each
individual design to reduce out-of-
band spurious emission levels.
Spurious emissions can be
measured as EIRP values according
to EN 300 220. The antenna
(SMAFF-433 and SMAFF-868 from
R.W. Badland) plays a part in
attenuating the spurious emissions.
If the output power is increased using
an external PA, a filter must be used
to attenuate spurs below 862 MHz
when operating in the 868 MHz
frequency band in Europe.
Application Note Application Note
AN036 CC1020/1021 Reducing
Spurious Emission (SWRA057)
presents and discusses a solution
that reduces the TX mode spurious
emission close to 862 MHz by
increasing the REF_DIV from 1 to 7.
9 kHz to 1 GHz –36 dBm
1 to 4 GHz –30 dBm

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RF Transmit (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Optimum load
impedance
433 MHz 54 + j44 ΩTransmit mode. For matching details
see Section 5.11.
868 MHz 15 + j24 Ω
915 MHz 20 + j35 Ω
(1) Two tone test (+10 MHz and +20 MHz)
4.5 RF Receive
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Receiver Sensitivity,
433 MHz, FSK
38.4 kHz channel filter BW (1) –109 dBm Sensitivity is measured with PN9
sequence at BER = 10−3
(1) 38.4 kHz receiver channel filter
bandwidth: 4.8 kBaud, NRZ coded
data, ±4.95 kHz frequency
deviation.
(2) 102.4 kHz receiver channel
filter bandwidth: 19.2 kBaud, NRZ
coded data, ±19.8 kHz frequency
deviation.
(3) 102.4 kHz receiver channel
filter bandwidth: 38.4 kBaud, NRZ
coded data, ±19.8 kHz frequency
deviation.
(4) 307.2 kHz receiver channel
filter bandwidth: 153.6 kBaud, NRZ
coded data, ±72 kHz frequency
deviation.
See Table 5-6 and Table 5-7 or
typical sensitivity figures at other
channel filter bandwidths.
102.4 kHz channel filter BW (2) –104 dBm
102.4 kHz channel filter BW (3) –104 dBm
307.2 kHz channel filter BW (4) –96 dBm
Receiver Sensitivity,
868 MHz, FSK
38.4 kHz channel filter BW (1) –108 dBm
102.4 kHz channel filter BW (2) –103 dBm
102.4 kHz channel filter BW (3) –103 dBm
307.2 kHz channel filter BW (4) –94 dBm
Receiver sensitivity,
433 MHz, OOK 9.6 kBaud –103 dBm Manchester coded data.
See Table 5-14 for typical
sensitivity figures at other data
rates. Sensitivity is measured with
PN9 sequence at
BER = 10−3
153.6 kBaud –81 dBm
Receiver sensitivity,
868 MHz, OOK
9.6 kBaud –104 dBm
153.6 kBaud –87 dBm
Saturation
(maximum input
level) FSK and OOK 10 dBm FSK: Manchester/NRZ coded data
OOK: Manchester coded data
BER = 10−3
System noise
bandwidth 38.4 to 307.2 kHz
The receiver channel filter 6 dB
bandwidth is programmable from
38.4 kHz to
307.2 kHz. See Section 5.9.2 for
details.
Noise figure,
cascaded 433 and 868 MHz 7 dB NRZ coded data
Input IP3(1)
433 MHz, 102.4 kHz
channel filter BW
–23 dBm LNA2 maximum gain
–18 dBm LNA2 medium gain
–16 dBm LNA2 minimum gain
868 MHz, 102.4 kHz
channel filter BW
–18 dBm LNA2 maximum gain
–15 dBm LNA2 medium gain
–13 dBm LNA2 minimum gain
Co-channel
rejection, FSK and
OOK 433 MHz and 868 MHz,
102.4 kHz channel filter BW –11 dB Wanted signal 3 dB above the
sensitivity level, CW jammer at
operating frequency, BER = 10−3

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RF Receive (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
(2) Close-in spurious response rejection.
(3) Out-of-band spurious response rejection.
Adjacent channel
rejection (ACR)
433 MHz,
102.4 kHz channel filter BW 32 dB Measured at ±100 kHz offset. See Figure 5-13 through Figure 5-
16. Wanted signal 3 dB above the
sensitivity level, CW jammer at
adjacent channel, BER = 10−3.
868 MHz,
102.4 kHz channel filter BW 30 dB
Image channel
rejection 433/868 MHz
No I/Q gain and
phase calibration 25/25 dB Wanted signal 3 dB above the sensitivity level, CW jammer at
image frequency, BER = 10−3.
102.4 kHz channel filter
bandwidth. See Figure 5-13
through Figure 5-16.
Image rejection after calibration
will depend on temperature and
supply voltage. Refer to
Section 5.9.6.
I/Q gain and
phase calibrated 50/50 dB
Selectivity(2)
433 MHz,
102.4 kHz
channel filter
BW
±200 kHz offset 45 dB Wanted signal 3 dB above the
sensitivity level. CW jammer is
swept in 20 kHz steps within ±1
MHz from wanted channel.
BER = 10−3. Adjacent channel and
image channel are excluded.
See Figure 5-13 through Figure 5-
16.
±300 kHz offset 53 dB
868 MHz,
102.4 kHz
channel filter
BW
±200 kHz offset 45 dB
±300 kHz offset 50 dB
Blocking /
Desensitization(3) 433/868 MHz
±1 MHz 52/58 dB Wanted signal 3 dB above the
sensitivity level,
CW jammer at ±1, 2, 5 and 10
MHz offset,
BER = 10−3. 102.4 kHz channel
filter bandwidth.
Complying with EN 300 220, class
2 receiver requirements.
±2 MHz 56/64 dB
±5 MHz 58/64 dB
±10 MHz 64/66 dB
Image frequency
suppression 433/868 MHz
No I/Q gain and
phase calibration 35/35 dB Ratio between sensitivity for a signal at the image frequency to
the sensitivity in the wanted
channel.
Image frequency is RF−2 IF. BER
= 10−3.
102.4 kHz channel filter
bandwidth.
I/Q gain and
phase calibrated 60/60 dB
Spurious rejection 37 dB
Ratio between sensitivity for an
unwanted frequency to the
sensitivity in the wanted channel.
The signal source is swept over all
frequencies 100 MHz to 2 GHz.
Signal level for BER = 10−3. 102.4
kHz channel filter bandwidth.
LO leakage 433/868 MHz < –80/–66 dBm
VCO leakage –64 dBm VCO frequency resides between
1608 to 1880 MHz
Spurious emission,
radiated CW
9 kHz to 1 GHz < –60 dBm Complying with EN 300 220 and
FCC CFR47 part 15.
Spurious emissions can be
measured as EIRP values
according to EN 300 220.
1 to 4 GHz < –60 dBm
Input impedance 433 MHz 58 – j10 ΩReceive mode. See Section 5.11
for details.
868 MHz 54 – j22 Ω

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RF Receive (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Matched input
impedance, S11 433 MHz –14 dB Using application circuit matching
network. See Section 5.11 for
details.
868 MHz –12 dB
Matched input
impedance 433 MHz 39 – j14 ΩUsing application circuit matching
network. See Section 5.11 for
details.
868 MHz 32 – j10 Ω
Bit synchronization offset 8000 ppm The maximum bit rate offset
tolerated by the bit synchronization
circuit for 6 dB degradation
(synchronous modes only)
Data latency NRZ mode 4 Baud Time from clocking the data on the transmitter DIO pin until data is
available on receiver DIO pin
Manchester mode 8 Baud
4.6 RSSI / Carrier Sense
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated. PARAMETER TYP UNIT CONDITION
RSSI dynamic range 55 dB See Section 5.9.5 for details.
RSSI accuracy ±3 dB See Section 5.9.5 for details.
RSSI linearity ±1 dB
RSSI attach time
51.2 kHz channel filter BW 730 µs Shorter RSSI attach times can be traded
for lower RSSI accuracy. See
Section 5.9.5 for details.
Shorter RSSI attach times can also be
traded for reduced sensitivity and
selectivity by increasing the receiver
channel filter bandwidth.
102.4 kHz channel filter BW 380 µs
307.2 kHz channel filter BW 140 µs
Carrier sense programmable range 40 dB Accuracy is as for RSSI
Carrier sense
at ±100 kHz and
±200 kHz offset
102.4 kHz channel filter BW,
433 MHz ±100 kHz –57 dBm At carrier sense level –98 dBm, CW
jammer at ±100 kHz and ±200 kHz
offset.
Carrier sense is measured by applying a
signal at ±100 kHz and ±200 kHz offset
and observe at which level carrier sense
is indicated.
±200 kHz –44 dBm
102.4 kHz channel filter BW,
868 MHz
±100 kHz –60 dBm
±200 kHz –44 dBm

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4.7 Intermediate Frequency (IF)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER TYP UNIT CONDITION
Intermediate frequency (IF) 307.2 kHz See Section 5.9.1 for details.
Digital channel filter bandwidth 38.4 to 307.2 kHz The channel filter 6 dB bandwidth is programmable from 9.6 kHz to 307.2 kHz. See Section 5.9.2 for
details.
AFC resolution 1200 Hz At 19.2 kBaud Given as Baud rate / 16. See Section 5.9.13 for
details.
4.8 Crystal Oscillator
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Crystal Oscillator Frequency 4.9152 14.7456 19.6608 MHz Recommended frequency is 14.7456 MHz. See
Section 5.16 for details.
Crystal operation Parallel C4 and C5 are loading capacitors. See Section 5.16
for details.
Crystal load capacitance
4.9 to 6 MHz,
22 pF recommended 12 22 30 pF
6 to 8 MHz,
16 pF recommended 12 16 30 pF
8 to 19.6 MHz,
16 pF recommended 12 16 16 pF
Crystal oscillator
start-up time
4.9152 MHz, 12 pF load 1.55 ms
7.3728 MHz, 12 pF load 1 ms
9.8304 MHz, 12 pF load 0.9 ms
14.7456 MHz, 16 pF load 0.95 ms
17.2032 MHz, 12 pF load 0.6 ms
19.6608 MHz, 12 pF load 0.63 ms
External clock signal drive, sine wave 300 mVpp
The external clock signal must
be connected to XOSC_Q1
using a DC block (10 nF). Set
XOSC_BYPASS = 0 in the
INTERFACE register when
using an external clock signal
with low amplitude or a
crystal.
External clock signal drive, full-swing digital external clock 0 – VDD V
The external clock signal must
be connected to XOSC_Q1.
No DC block shall be used.
Set XOSC_BYPASS = 1 in
the INTERFACE register
when using a full-swing digital
external clock.

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4.9 Frequency Synthesizer
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated. PARAMETER TYP UNIT CONDITION
Phase noise, 402 to 470 MHz
At 12.5 kHz offset from carrier –79 dBc/Hz Unmodulated carrier
Measured using loop filter
components given in Table 6-2. The
phase noise will be higher for larger
PLL loop filter bandwidth.
At 25 kHz offset from carrier –80 dBc/Hz
At 50 kHz offset from carrier –87 dBc/Hz
At 100 kHz offset from carrier –100 dBc/Hz
At 1 MHz offset from carrier –105 dBc/Hz
Phase noise, 804 to 930 MHz
At 12.5 kHz offset from carrier –73 dBc/Hz Unmodulated carrier
Measured using loop filter
components given in Table 6-2. The
phase noise will be higher for larger
PLL loop filter bandwidth.
At 25 kHz offset from carrier –74 dBc/Hz
At 50 kHz offset from carrier –81 dBc/Hz
At 100 kHz offset from carrier –94 dBc/Hz
At 1 MHz offset from carrier –111 dBc/Hz
PLL loop filter bandwidth
Loop filter 2, up to 19.2 kBaud 15 kHz After PLL and VCO calibration.
The PLL loop bandwidth is
programmable.
See Table 5-12 for loop filter
component values.
Loop filter 3, up to 38.4 kBaud 30.5 kHz
PLL lock time (RX / TX turn
time)
Loop filter 2, up to 19.2 kBaud 140 µs 307.2 kHz frequency step to RF
frequency within ±10 kHz, ±15 kHz,
±50 kHz settling accuracy for loop
filter 2, 3 and 5 respectively.
Depends on loop filter component
values and PLL_BW register
setting. See Table 5-13 for more
details.
Loop filter 3, up to 38.4 kBaud 75 µs
Loop filter 5, up to 153.6 kBaud 14 µs
PLL turn-on time.
From power down mode with
crystal oscillator running.
Loop filter 2, up to 19.2 kBaud 1300 µs Time from writing to registers to RF
frequency within ±10 kHz, ±15 kHz,
±50 kHz settling accuracy for loop
filter 2, 3 and 5 respectively.
Depends on loop filter component
values and PLL_BW register
setting. See Table 5-12 for more
details.
Loop filter 3, up to 38.4 kBaud 1080 µs
Loop filter 5, up to 153.6 kBaud 700 µs
4.10 Digital Inputs / Outputs
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Logic "0" input voltage 0 0.3 × VDD V
Logic "1" input voltage 0.7 × VDD VDD V
Logic "0" output voltage 0 0.4 V Output current –2.0 mA,
3.0 V supply voltage
Logic "1" output voltage 2.5 VDD V Output current 2.0 mA,
3.0 V supply voltage
Logic "0" input current N/A –1 µA
Input signal equals GND.
PSEL has an internal pullup
resistor and during
configuration the current
will be –350 mA.
Logic "1" input current N/A 1 µA Input signal equals VDD
DIO setup time 20 ns
TX mode, minimum time
DIO must be ready before
the positive edge of DCLK.
Data should be set up on
the negative edge of DCLK.

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Digital Inputs / Outputs (continued)
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
DIO hold time 10 ns
TX mode, minimum time
DIO must be held after the
positive edge of DCLK.
Data should be set up on
the negative edge of DCLK.
Serial interface
(PCLK, PDI, PDO and PSEL)
timing specification See Table 5-1 for more
details
Pin drive,
LNA_EN,
PA_EN
Source
current
0 V on LNA_EN, PA_EN pins 0.90 mA
See Figure 5-32 for more
details.
0.5 V on LNA_EN, PA_EN pins 0.87 mA
1.0 V on LNA_EN, PA_EN pins 0.81 mA
1.5 V on LNA_EN, PA_EN pins 0.69 mA
Sink current
3.0 V on LNA_EN, PA_EN pins 0.93 mA
2.5 V on LNA_EN, PA_EN pins 0.92 mA
2.0 V on LNA_EN, PA_EN pins 0.89 mA
1.5 V on LNA_EN, PA_EN pins 0.79 mA
4.11 Current Consumption
All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical
specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA= 25°C, AVDD = DVDD = 3.0 V, fC= 14.7456
MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Power Down mode 0.2 1.8 µA Oscillator core off
Current Consumption,
receive mode 433 and 868 MHz 19.9 mA
Current Consumption,
transmit mode 433/868 MHz
P = –20 dBm 12.3/14.5 mA
The output power is delivered to a
50 Ωsingle-ended load.
See Section 5.10.2 for more details.
P = –5 dBm 14.4/17.0 mA
P = 0 dBm 16.2/20.5 mA
P = +5 dBm 20.5/25.1 mA
P = +10 dBm
(433 MHz only) 27.1 mA
Current Consumption, crystal oscillator 77 µA 14.7456 MHz, 16 pF load crystal
Current Consumption, crystal oscillator and bias 500 µA 14.7456 MHz, 16 pF load crystal
Current Consumption, crystal oscillator, bias and synthesizer 7.5 mA 14.7456 MHz, 16 pF load crystal

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Specifications Copyright © 2006–2018, Texas Instruments Incorporated
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
4.12 Thermal Resistance Characteristics for VQFNP Package
NAME DESCRIPTION °C/W(1) (2)
RθJC(top) Junction-to-case (top) 16.2
RθJB Junction-to-board 6.9
RθJA Junction-to-free air 30.7
PsiJT Junction-to-package top 0.2
PsiJB Junction-to-board 6.9
RθJC(bottom) Junction-to-case (bottom) 1.0

DIO
LOCK
DCLK
RF_IN LNA
FREQ
SYNTH
DIGITAL
DEMODULATOR
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
DIGITAL
MODULATOR
- Modulation
- Data shaping
- Power Control
BIAS
Power
Control
DIGITAL
INTERFACE
TO mC
CONTROL
LOGIC
PA
ADC
ADC
RF_OUT
R_BIAS XOSC_Q1 XOSC_Q2
PDO
XOSC
VC CHP_OUT
LNA 2
0
90 :2
0
90 :2
Multiplexer
Multiplexer
PA_EN LNA_EN
PCLK
PDI
PSEL
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Detailed DescriptionCopyright © 2006–2018, Texas Instruments Incorporated
5 Detailed Description
5.1 Overview
A simplified block diagram of the CC1021 device is shown in Figure 5-1. Only signal pins are shown.
The CC1021 device features a low-IF receiver. The received RF signal is amplified by the low-noise
amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF).
At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain
control, fine channel filtering, demodulation and bit synchronization is performed digitally. The CC1021
device outputs the digital demodulated data on the DIO pin. A synchronized data clock is available at the
DCLK pin. RSSI is available in digital format and can be read via the serial interface. The RSSI also
features a programmable carrier sense indicator.
In transmit mode, the synthesized RF frequency is fed directly to the power amplifier (PA). The RF output
is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian
filter can be used to obtain Gaussian FSK (GFSK).
The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for
generating the LO_I and LO_Q signals to the down-conversion mixers in receive mode. The VCO
operates in the frequency range 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and
VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal
is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.
The 4-wire SPI serial interface is used for configuration.
5.2 Functional Block Diagram
Figure 5-1. CC1021 Device Simplified Block Diagram

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5.3 Configuration Overview
The CC1021 device can be configured to achieve the optimum performance for different applications.
Through the programmable configuration registers the following key parameters can be programmed:
• Receive / transmit mode
• RF output power
• Frequency synthesizer key parameters:
– RF output frequency
– FSK frequency separation
– Crystal oscillator reference frequency
• Power-down / power-up mode
• Crystal oscillator power up or power down
• Data rate and data format (NRZ, Manchester coded or UART interface)
• Synthesizer lock indicator mode
• Digital RSSI and carrier sense
• FSK / GFSK / OOK modulation
5.3.1 Configuration Software
TI provides users of the CC1021 device with a software program, SmartRF™ Studio (Windows interface),
that generates all necessary CC1021 device configuration data based on the user's selections of various
parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the
configuration of the CC1021 device. In addition, the program will provide the user with the component
values needed for the input/output matching circuit, the PLL loop filter and the LC filter.
Figure 5-2 shows the user interface of the CC1021 device configuration software.
Figure 5-2. SmartRF™ Studio User Interface

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5.4 Microcontroller Interface
Used in a typical system, the CC1021 device will interface to a microcontroller. This microcontroller must
be able to:
• Program the CC1021 device into different modes via the 4-wire serial configuration interface (PDI,
PDO, PCLK and PSEL)
• Interface to the bi-directional synchronous data signal interface (DIO and DCLK)
• Optionally, the microcontroller can do data encoding / decoding
• Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status
or other status information.
• Optionally, the microcontroller can read back the digital RSSI value and other status information via the
4-wire serial interface.
5.4.1 Configuration Interface
The microcontroller interface is shown in Figure 5-3. The microcontroller uses 3 or 4 I/O pins for the
configuration interface (PDI, PDO, PCLK and PSEL). PDO should be connected to a microcontroller input.
PDI, PCLK and PSEL must be microcontroller outputs. One I/O pin can be saved if PDI and PDO are
connected together and a bi-directional pin is used at the microcontroller.
The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the
configuration interface is not used. PDI, PDO and PCLK are high impedance inputs as long as PSEL is
not activated (active low).
PSEL has an internal pullup resistor and should be left open (tri-stated by the microcontroller) or set to a
high level during power down mode in order to prevent a trickle current flowing in the pullup.
Figure 5-3. Microcontroller Interface
5.4.2 Signal Interface
A bi-directional pin is usually used for data (DIO) to be transmitted and data received. DCLK providing the
data timing should be connected to a microcontroller input.
As an option, the data output in receive mode can be made available on a separate pin. See Section 5.6
further details.
5.4.3 PLL Lock Signal
Optionally, one microcontroller pin can be used to monitor the LOCK signal. This signal is at low logic
level when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test
signals.

PCLK
PDI
PSEL
Address Write mode
6543210 765432 1 0
Data byte
THD
TSS
TCL,min TCH,min
THS
W
TSD
PDO
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5.5 4-wire Serial Configuration Interface
The CC1021 device is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and
PSEL) where the CC1021 device is the slave. There are 8-bit configuration registers, each addressed by a
7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of the CC1021
device requires sending 33 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time
needed for a full configuration depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full
configuration is done in less than 53 ms. Setting the device in power down mode requires sending one
frame only and will in this case take less than 2 ms. All registers are also readable.
During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data
frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the
first bit. The next bit is the R/W bit (high for write, low for read). The 8 data-bits are then transferred
(D7:0). During address and data transfer the PSEL (Program SELect) must be kept low. See Figure 5-4.
The timing for the programming is also shown in Figure 5-4 with reference to Table 5-1. The clocking of
the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of
PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is
loaded into the internal configuration register.
The configuration data will be retained during a programmed power down mode, but not when the power
supply is turned off. The registers can be programmed in any order.
The configuration registers can also be read by the microcontroller via the same configuration interface.
The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. The CC1021
device then returns the data from the addressed register. PDO is used as the data output and must be
configured as an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be
sampled at the positive edge. The read operation is illustrated in Figure 5-5.
PSEL must be set high between each read/write operation.
Figure 5-4. Configuration Registers Write Operation

PCLK
PDI
PSEL
Address Read mode
6 5 4 3 2 1 0
TSS
TCL,min TCH,min
THS
R
PDO 765 4 3 2 10
Data byte
TSH
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(1) The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is
valid for is 20 pF.
Figure 5-5. Configuration Registers Read Operation
Table 5-1. Serial Interface, Timing Specification(1)
PARAMETER MIN MAX UNIT CONDITIONS
FPCLK PCLK, clock frequency 10 MHz
TCL,min PCLK low pulse duration 50 ns The minimum time PCLK must be low.
TCH,min PCLK high pulse duration 50 ns The minimum time PCLK must be high.
TSS PSEL setup time 25 ns The minimum time PSEL must be low before positive
edge of PCLK.
THS PSEL hold time 25 ns The minimum time PSEL must be held low after the
negative edge of PCLK.
TSH PSEL high time 50 ns The minimum time PSEL must be high.
TSD PDI setup time 25 ns The minimum time data on PDI must be ready before the
positive edge of PCLK.
THD PDI hold time 25 ns The minimum time data must be held at PDI, after the
positive edge of PCLK.
Trise Rise time 100 ns The maximum rise time for PCLK and PSEL
Tfall Fall time 100 ns The maximum fall time for PCLK and PSEL

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5.6 Signal Interface
The CC1021 device can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-
phase-level) encoded data. The CC1021 device can also synchronize the data from the demodulator and
provide the data clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the
MODEM register.
The CC1021 device can be configured for three different data formats:
• Synchronous NRZ mode
• Transparent Asynchronous UART mode
• Synchronous Manchester encoded mode
5.6.1 Synchronous NRZ Mode
In transmit mode, the CC1021 device provides the data clock at DCLK and DIO is used as data input.
Data is clocked into the CC1021 device at the rising edge of DCLK. The data is modulated at RF without
encoding.
In receive mode, the CC1021 device performs the synchronization and provides received data clock at
DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK.
See Figure 5-6.
5.6.2 Transparent Asynchronous UART Mode
In transmit mode, DIO is used as data input. The data is modulated at RF without synchronization or
encoding.
In receive mode, the raw data signal from the demodulator is sent to the output (DIO). No synchronization
or decoding of the signal is done in the CC1021 device and should be done by the interfacing circuit.
If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data
input in transmit mode. The DCLK pin is not active and can be set to a high or low level by
DATA_FORMAT[0].
If SEP_DI_DO = 1 in the INTERFACE register, the DCLK pin is the data output in receive mode and the
DIO pin is the data input in transmit mode. In TX mode the DCLK pin is not active and can be set to a high
or low level by DATA_FORMAT[0]. See Figure 5-8.
5.6.3 Synchronous Manchester Encoded Mode
In transmit mode, the CC1021 device provides the data clock at DCLK and DIO is used as data input.
Data is clocked into the CC1021 device at the rising edge of DCLK and should be in NRZ format. The
data is modulated at RF with Manchester code. The encoding is done by the CC1021 device. In this
mode, the effective bit rate is half the baud rate due to the coding. As an example, 19.2 kBaud
Manchester encoded data corresponds to 9.6 kbps.
In receive mode, the CC102 device performs the synchronization and provides received data clock at
DCLK and data at DIO. The CC1021 device performs the decoding and NRZ data is presented at DIO.
The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 5-7.
In synchronous NRZ or Manchester mode the DCLK signal runs continuously both in RX and TX unless
the DCLK signal is gated with the carrier sense signal or the PLL lock signal. Refer to Section 5.18 for
more details.
If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data
input in transmit mode.
As an option, the data output can be made available at a separate pin. This is done by setting
SEP_DI_DO = 1 in the INTERFACE register. Then, the LOCK pin will be used as data output in
synchronous mode, overriding other use of the LOCK pin.