(2) Another connection example like one in Fig.
11-(c) can be considered when you wish to
develop the previous connection in order to
reduce the number of lines. The idea of this
connection is that switches 1 and 2 are
synchronized with each other, through which
signals A to D are transmitted in this order to
each corresponding output. In this event, the
signals delivered to the outputs 1 through 4
are the RAM signal described in section 3-2.
(3) In the example of Fig. 11-(c), one switch has
many contact points, but an actual system
uses an analog switch as shown in Fig. 11-(d),
instead of each contact point so that an
individual pair of analog switches (x and y) is
sequenced in the following order:
When the analog switches x
1
and y
1
synchro-
nized with each other are on, the signal A is
allowed to go through to the output 1, and
likewise when x
2
and y
2
are on, the signal B is
delivered to its corresponding output 2. This
continues till the signal D is sent out to its
output 4, and is again repeated from the
beginning.
Here we show the timing of each switch used in
the system of Fig. 11-(d).
Fig.12 Timing Chart
In the above timing chart, 4 different PAM signals
of Fig. 11-(d) are on a highway (H W line), the state
of which is called "being time division multi-
plexed". In Fig. 11-(d), the signals are quadplexed.
Also, the frequencies (time intervals) of sampled
pulses (i) through (iv) are all the same, which are
the sampling frequency described in section 3-4.
Fig.11-(c)
Fig.11-(d)
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