Ublox NORA-W10 Series Quick setup guide

UBX-22005601 - R04
C1-Public www.u-blox.com
NORA-W10 series
Standalone, multiradio modules with Wi-Fi 4
(802.11b/g/n) and Bluetooth Low Energy 5.0
System integration manual
Abstract
This manual provides a functional overview combined with best-practice design guidelines for
integrating NORA-W10 stand-alone Wi-Fi and Bluetooth Low Energy v5.0 modules in customer
applications. Including a powerful microcontroller, MCU, NORA-W10 is intended for custom
application software. The module has several important embedded security features, including
secure boot, which ensures the module boots with authenticated software only.

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Document information
Title
NORA-W10 series
Subtitle
Standalone, multiradio modules with Wi-Fi 4 (802.11b/g/n) and Bluetooth
Low Energy 5.0
Document type
System integration manual
Document number
UBX-22005601
Revision and date
R04
15-Mar-2023
Disclosure restriction
C1-Public
Document status description
Draft
For functional testing. Revised and supplementary data will be published later.
Objective Specification
Target values. Revised and supplementary data will be published later.
Advance Information
Data based on early testing. Revised and supplementary data will be published later.
Early Production Information
Data from product verification. Revised and supplementary data may be published later.
Production Information
Document contains the final product specification.
This document applies to the following products:
Product name
Document status
NORA-W101
Early product information
NORA-W106
Early product information
☞For information about the related hardware, software, and status of listed product types, see also
the data sheet [2].
u-blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, or modification of this document or any part thereof is only permitted with the express
written permission of u-blox. Disclosure to third parties is permitted for clearly public documents only.
The information contained herein is provided “as is”. No warranty of any kind, either express or implied, is made in relation to
the accuracy, reliability, fitness for a particular purpose or content of this document. This document may be revised by u-blox
at any time. For most recent documents, please visit www.u-blox.com.
Copyright © u-blox AG.

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Contents
Document information ......................................................................................................................2
Contents ..............................................................................................................................................3
1Module overview ..........................................................................................................................6
1.1 Module architecture .......................................................................................................................................... 6
1.1.1 Block diagram ............................................................................................................................................. 7
1.2 Pin definition ........................................................................................................................................................ 8
1.2.1 General Purpose Input and Output, GPIO pins.................................................................................. 8
1.3 Pin assignment ................................................................................................................................................... 8
1.4 Pin list..................................................................................................................................................................... 9
2Module integration ................................................................................................................... 12
2.1 CPU .......................................................................................................................................................................12
2.2 Power modes......................................................................................................................................................12
2.2.1 Low Power mode with Low Frequency Clock...................................................................................12
2.3 Power supply ......................................................................................................................................................12
2.3.1 Module supply input (VCC) ...................................................................................................................13
2.3.2 Digital I/O interfaces reference voltage (VCC_IO)..........................................................................13
2.3.3 VCC application circuits ........................................................................................................................13
2.4 Module reset ......................................................................................................................................................13
2.5 Bootstrap pins...................................................................................................................................................13
2.6 Antenna integration ........................................................................................................................................14
2.6.1 External RF antenna interface.............................................................................................................14
2.6.2 Internal antenna.......................................................................................................................................15
2.7 Data interfaces..................................................................................................................................................15
2.7.1 Universal asynchronous serial interface (UART) ...........................................................................15
2.7.2 Serial peripheral interface (SPI)...........................................................................................................15
2.7.3 Dual/Quad SPI...........................................................................................................................................16
2.7.4 TWAI............................................................................................................................................................16
2.8 Analog interfaces .............................................................................................................................................16
2.8.1 Analog to digital converters .................................................................................................................16
2.9 No-connect pins (NC)......................................................................................................................................16
3Design-in..................................................................................................................................... 17
3.1 Overview ..............................................................................................................................................................17
3.2 Antenna interface ............................................................................................................................................17
3.2.1 RF transmission line design (NORA-W101)....................................................................................18
3.2.2 Antenna design (NORA-W101)...........................................................................................................20
3.2.3 On-board antenna design .....................................................................................................................23
3.3 Data communication interfaces ..................................................................................................................25
3.3.1 Asynchronous serial interface (UART) design................................................................................25
3.4 General high-speed layout guidelines ........................................................................................................25
3.4.1 Considerations for schematic design and PCB floor-planning..................................................25

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3.4.2 Component placement ..........................................................................................................................25
3.4.3 Layout and manufacturing...................................................................................................................25
3.5 Module footprint and paste mask...............................................................................................................26
3.6 Thermal guidelines...........................................................................................................................................27
3.7 ESD guidelines...................................................................................................................................................27
3.8 Design-in checklists.........................................................................................................................................28
3.8.1 Schematic checklist................................................................................................................................28
3.8.2 Layout checklist.......................................................................................................................................28
4Software ..................................................................................................................................... 29
4.1 SDK for Open CPU modules ..........................................................................................................................29
4.2 Developing and flashing NORA-W10 Open CPU software...................................................................29
4.2.1 Set up Toolchain and ESP-IDF v4.4 source files.............................................................................30
4.2.2 Setup path to ESP-IDF...........................................................................................................................30
4.2.3 Build and flash ..........................................................................................................................................30
4.2.4 ESP-IDF partition table ..........................................................................................................................31
4.2.5 Automatic bootloader on NORA-W10 EVK......................................................................................32
4.3 Output power configuration..........................................................................................................................32
4.3.1 NORA-W10 series....................................................................................................................................32
5Handling and soldering ............................................................................................................ 33
5.1 ESD handling precautions .............................................................................................................................33
5.2 Packaging, shipping, storage, and moisture preconditioning ............................................................33
5.3 Reflow soldering process ...............................................................................................................................34
5.3.1 Cleaning......................................................................................................................................................35
5.3.2 Other remarks...........................................................................................................................................35
6Regulatory compliance ............................................................................................................ 36
6.1 Country approvals............................................................................................................................................36
6.2 European Union regulatory compliance.....................................................................................................36
6.2.1 Radio Equipment Directive (RED) 2014/53/EU ..............................................................................36
6.2.2 Compliance with the RoHS directive .................................................................................................36
6.2.3 CE End-product regulatory compliance............................................................................................36
6.3 Great Britain regulatory compliance...........................................................................................................37
6.3.1 UK Conformity Assessed (UKCA) .......................................................................................................37
6.4 FCC/ISED compliance .....................................................................................................................................37
6.4.1 FCC compliance statements................................................................................................................37
6.4.2 Configuration control and software security of end-products ..................................................38
6.4.3 Operating frequencies ...........................................................................................................................39
6.4.4 RF exposure statement .........................................................................................................................39
6.4.5 End-product user manual instructions.............................................................................................40
6.4.6 End-product labeling requirements ...................................................................................................40
6.4.7 End-product compliance .......................................................................................................................41
6.5 Japan radio equipment compliance ...........................................................................................................42
6.5.1 Compliance statement ..........................................................................................................................42

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6.5.2 End product labelling requirement.....................................................................................................42
6.5.3 End product user manual requirement.............................................................................................43
6.6 NCC Taiwan compliance.................................................................................................................................43
6.6.1 Taiwan NCC Warning Statement.......................................................................................................43
6.6.2 Labeling requirements for end product ............................................................................................43
6.7 KCC South Korea compliance.......................................................................................................................44
6.8 Brazil compliance..............................................................................................................................................44
6.9 Australia and New Zealand regulatory compliance ...............................................................................45
6.10South Africa regulatory compliance...........................................................................................................45
6.11Safety compliance............................................................................................................................................45
6.12Bluetooth qualification ...................................................................................................................................46
7Pre-approved antennas list .................................................................................................... 47
7.1 Antenna accessories.......................................................................................................................................47
7.2 Single band antennas .....................................................................................................................................48
7.2.1 Dual-band antennas ...............................................................................................................................50
8Product testing ......................................................................................................................... 52
8.1 u-blox in-line production test........................................................................................................................52
8.2 OEM manufacturer production test...........................................................................................................53
8.2.1 “Go/No go” tests for integrated devices...........................................................................................53
Appendix ........................................................................................................................................... 54
AGlossary ...................................................................................................................................... 54
Related documentation.................................................................................................................. 56
Revision history ............................................................................................................................... 56
Contact.............................................................................................................................................. 56

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1Module overview
The NORA-W10 series comprises small, stand-alone, multiradio modules that integrate a powerful
microcontroller, MCU, and a radio forwireless Bluetooth and Wi-Fi communication. With the open CPU
architecture, customers can develop advanced applications running on the dual core 32-bit MCU. The
radio provides support for Wi-Fi 802.11b/g/n in the 2.4 GHz ISM band and Bluetooth Low Energy (LE)
v5.0 communications.
Supporting integrated cryptographic hardware accelerators, NORA-W10 series modules are ideal for
Internet of Things (IoT) devices, telematics, low power sensors, connected factories, connected
buildings (appliances and surveillance), point-of-sales, health devices, Artificial intelligence (AI), facial
recognition, and other design solutions that demand top-grade security.
NORA-W10 modules are compliant with the Radio Equipment Directive (RED) and are to be certified
as modular transmitters in the: Europe (RED), Great Britain (UKCA), US (FCC), Canada (IC / ISED RSS),
Japan (MIC), Taiwan (NCC), South Korea (KCC), Australia / New Zealand (ACMA), Brazil (ANATEL),
and South Africa (ICASA). For the current approval status of certification in each country, see also
Country approvals.
NORA-W10 series modules are professional grade products and support an extended temperature
range of 40 °C to +85 °C.
1.1 Module architecture
Based on the Espressif ESP32-S3 chip, NORA-W10 modules allow developers to choose either an
arbitrary external antenna with NORA-W101 or the internal antenna supported in NORA-W106 for
their application design.
These compact modules include the MCU, flash memory, crystal, and other components for
matching, filtering, antenna, decoupling, and antenna operation.
Two versions of NORA-W10 are available: NORA-W101 with antenna RF pad for the connection of an
external antenna and NORA-W106 that supports an internal PCB trace antenna.
Variant /
Ordering code
Antenna configuration
Antenna type
NORA-W101-00B
RF_ANT0: 2.4 GHz Wi-Fi and Bluetooth LE
Antenna pad
NORA-W106-00B
Switched 2.4 GHz Wi-Fi and Bluetooth LE
Single embedded PCB antenna
Table 1: Supported configurations of the NORA-W10 module series

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1.1.1 Block diagram
Figure 1: NORA-W10 series block diagram
Linear voltage regulators
RF
Wi-Fi
baseband
Bluetooth LE
Baseband
IO buffers
Xtensa Dual-core 32-bit LX7 MCU
SRAM
(512 kB)
Cryptographic
hardware
accelerators
PLL
VCC_IO
VCC (3.0- 3.6V)
40 MHz
Reset
UART
USB
I2C
SPI
QPI
Quad/Octal SPI
JTAG
GPIO
ADC
Flash
(8MB)
OPI
LPO
EFuse
ROM
(384 kB)
PCB trace antenna
(NORA-W106)
ANT PAD
(NORA-W101)
NORA-W1
ESP32-S3

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1.2 Pin definition
1.2.1 General Purpose Input and Output, GPIO pins
NORA-W101/NORA-W106 modules have82 pins. 38 pins can be used for either input or output. 4 pins
are for input only.
1.3 Pin assignment
Figure 2 shows the multiplexed pinout for NORA-W101 and NORA-W106 Open CPU modules. These,
and several additional interfaces not shown here, are described in
Although it is also possible to multiplex all interfaces through an IO MUX using any pin, the maximum
speed is limited. See also “Digital pins” in the NORA-W10 data sheet [2].
Figure 2: NORA-W101/W106 pin assignment (top view)
☞All grey pins are GND.
☞Pins A7, A8, B7, and J3 can only be used as (GPI) input signals –regardless of the selected
function/interface.
☞Several pins are used for bootstrap settings. It is important that these signals, shown in
Table 2, have the correct state during startup. See also Boot strap pins.

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1.4 Pin list
Table 2 describes the common pinout for all NORA-W10 series modules.
No.
NORA function
I/O1
Description
ESP32-S3
function
Remarks
A2
FSPIWP /
GPIO38
I/O
SPI2 Write Protect /
General Purpose I/O
FSPIWP /
GPIO38
A3
GPIO17
I/O
General Purpose I/O
GPIO17
Analog-capable pin
A4
NC
A5
FSPIDQS /
GPIO14
I/O
FSPIDQS /
GPIO14
Analog-capable pin, Touch button input
A6
FSPIIO7 /
GPIO13
I/O
SPI2 IO7 /
General Purpose I/O
FSPIIO7 /
GPIO13
Analog-capable pin, Touch button input
A7
VCCIO
I
Module I/O level voltage input
VIO voltage supply.
A8
VCC
I
Module supply voltage input
3.0-3.6 V module voltage supply.
B1
FSPICLK /
GPIO36
I/O
SPI2 clock /
General Purpose I/O
FSPICLK /
GPIO36
B3
FSPICS0 /
GPIO34
I/O
SPI2 Chip select /
General Purpose I/O
FSPICS0 /
GPIO34
B4
GPIO18
I/O
General Purpose I/O
GPIO18
Analog-capable pin
B5
NC
B6
XTAL_32K_N
/LPO_IN
GPIO16
I/O
32KHz external clock input /
Low Power Oscillator Input /
General Purpose I/O
GPIO16
Analog-capable pin
B7
VCCIO
I
Module I/O level voltage input
VIO voltage supply.
B9
NC
C1
FSPIQ /
GPIO37
I/O
SPI2 Controller Input Peripheral
Output /
General Purpose I/O
FSPIQ /
GPIO37
C2
FSPID /
GPIO35
I/O
SPI2 Controller Output
Peripheral Input /
General Purpose I/O
FSPID /
GPIO35
C4
SPICS0
I/O
SPI0 Chip select
SPICS0 /
GPIO29
Connected to internal flash. Do not
connect
C5
NC
C6
XTAL_32K_P /
GPIO15
I/O
32KHz external clock input /
General Purpose I/O
GPIO15
Analog-capable pin. If external LPO is
used at LPO_IN, put decoupling capacitor
>2F to GND on this pin only.
C8
GPIO21
I/O
General Purpose I/O
GPIO21
C9
USB_P /
GPIO20
I/O
USB differential data signal /
General Purpose I/O
USB_D+ /
GPIO20
Analog-capable pin. Default drive
capability of this pin is ~40mA
D1
SPIWP
I/O
SPI0 Write Protect
SPIWP /
GPIO28
Connected to internal flash. Connect only
for PSRAM else do not connect
D2
SPID
I/O
SPI0 Controller Output
Peripheral Input
SPID /
GPIO32
Connected to internal flash. Connect only
for PSRAM else do not connect
D3
FSPIHD /
GPIO33
I/O
SPI2 Hold /
General Purpose I/O
FSPIHD /
GPIO33
D7
NC
D8
GPIO4
I/O
General Purpose I/O
GPIO4
Analog-capable pin, Touch button input
1
I/O notations: I=Input, O=Output, I/O=Input or Output, PU=Pull Up, PD=Pull Down, D=Default, PP=Push-Pull, OD=Open Drain,
AI/AO=Analog Input/Output, NC=Not Connected

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No.
NORA function
I/O1
Description
ESP32-S3
function
Remarks
D9
USB_N /
GPIO19
I/O
USB differential data signal /
General Purpose I/O
USB_D- /
GPIO19
Analog-capable pin. Default drive
capability of this pin is ~40mA
E1
SPICS1
I/O
SPI Chip select /
General Purpose I/O
SPICS1 /
GPIO26
PSRAM chip select.
E2
SPIQ
I/O
SPI0 Controller Input Peripheral
Output
SPIQ /
GPIO31
Connected to internal flash. Connect only
for PSRAM else do not connect
E3
SPICLK_N /
GPIO48
I/O
SPI Differential clock /
General Purpose I/O
SPICLK_N /
GPIO48
E7
GPIO9
I/O
General Purpose I/O
GPIO9
Analog-capable pin, Touch button input
E8
GPIO1
I/O
General Purpose I/O
GPIO1
Analog-capable pin, Touch button input
E9
GPIO7
I/O
General Purpose I/O
GPIO7
Analog-capable pin, Touch button input
F1
SPICLK
I/O
SPI0 clock
SPICLK /
GPIO30
Connected to internal flash. Connect only
for PSRAM else do not connect
F2
SPIHD
I/O
SPI0 Hold
SPIHD /
GPIO27
Connected to internal flash. Connect only
for PSRAM else do not connect
F3
SPICLK_P /
GPIO47
I/O
SPI Differential clock /
General Purpose I/O
SPICLK_P /
GPIO47
F7
GPIO0/
Boot
I/O
General Purpose I/O
GPIO0/
Boot
F8
GPIO45
I/O
General Purpose I/O
GPIO45
F9
GPIO6
I/O
General Purpose I/O
GPIO6
Analog-capable pin, Touch button input
G1
MTDO /
GPIO40
I/O
JTAG Test Data Out /
MTDO /
GPIO40
G2
FSPIIO6 /
GPIO12
I/O
SPI2 IO6 /
General Purpose I/O
FSPIIO6 /
GPIO12
Analog-capable pin, Touch button input
G3
FSPIIO5 /
GPIO11
I/O
SPI2 IO5 /
General Purpose I/O
FSPIIO5 /
GPIO11
Analog-capable pin, Touch button input
G4
NC
G5
NC
G7
NC
G8
U0TXD /
GPIO43
I/O
UART data output /
General Purpose I/O
U0TXD /
GPIO43
G9
U0RXD /
GPIO44
I/O
UART data input /
General Purpose I/O
U0RXD /
GPIO44
H1
JTAG_TDI /
GPIO41
I/O
JTAG Test Data In (debug
interface) /
General Purpose I/O
MTDI /
GPIO41
H2
JTAG_TMS /
GPIO42
I/O
JTAG Test Mode Select /
General Purpose I/O
MTMS /
GPIO42
H3
FSPII04 /
GPIO10
I/O
SPI2 IO5 /
General Purpose I/O
FSPII04 /
GPIO10
Analog-capable pin, Touch button input
H7
GPIO46
I/O
General Purpose I/O
GPIO46
H8
GPIO2
I/O
General Purpose I/O
GPIO2
Analog-capable pin, Touch button input
H9
GPIO8
I/O
General Purpose I/O
GPIO8
Analog-capable pin, Touch button input
J1
VDD_SPI
O
SPI power supply: 3.3 V
VDD_SPI
J2
JTAG_TCK /
GPIO39
I/O
JTAG Test clock /
General Purpose I/O
MTCK /
GPIO39
J3
RESET_N
I
External system reset input.
RESET
Active low
J4
NC

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No.
NORA function
I/O1
Description
ESP32-S3
function
Remarks
J5
NC
J7
NC
J8
GPIO5
I/O
General Purpose I/O
GPIO5
Analog-capable pin, Touch button input
J9
GPIO3
I/O
General Purpose I/O
GPIO3
Analog-capable pin, Touch button input
K1
NC
K9
ANT
I/O
Antenna Tx/Rx interface
LNA_IN
50 Ωnominal characteristic impedance,
only used with NORA-W101 modules.
NC for NORA-W106
EGP
-
Exposed Ground Pins
Exposed scattered grey pins on the
module should be connected to GND
L1-M9
EAGP
-
Exposed Antenna Ground Pins
Exposed pins underneath the antenna
area should be connected to GND
Table 2: NORA-W10 pinout

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2Module integration
2.1 CPU
NORA-W10 series modules includes a Harvard Architecture Xtensa LX7 dual core CPU operating at
an internal clock frequency of up to 240 MHz. The Open CPU architecture allows custom advanced
applications running on the CPU.
The NORA-W10 architecture includes the following memories:
•384 KByte ROM for booting and core functions
•512 KByte SRAM for data and instruction
•8 Mbyte FLASH for code storage, including hardware encryption to protect programs.
•4 kbit EFUSE (non-erasable memory) for MAC addresses, module configuration, flash encryption,
and chip ID
2.2 Power modes
NORA-W10 series modules are power efficient devices capable of operating in different power saving
modes and configurations. Different sections of the module can be powered off when they are not
needed, and complex wake up events can be generated from different external and internal inputs.
For more information about power modes, see the Espressif ESP32-S3 Datasheet [2].
2.2.1 Low Power mode with Low Frequency Clock
NORA-W10 series modules do not have an internal low power oscillator (LPO) or low frequency crystal
(LFXTAL), which is required for low power modes. If low power mode is required, an external high
precision, +/- 20 ppm, 32.768 kHz crystal must be connected between pins XTAL_32K_N (Pin B6) and
XTAL_32K_P (Pin C6).
On EVK-NORA-W10, the crystal is connected to XTAL_32K_N (Pin B6) and XTAL_32K_P (Pin C6)
using a jumper configuration in order to use these as GPIOs when Low Power Mode is not in use, as
shown in Figure 3.
Figure 3: Low Frequency Clock
2.3 Power supply
The power for NORA-W10 series modules is supplied through VCC and VCC_IO pins by DC voltage.
⚠The power supply circuit must be able to source the peak current of the power modes consuming
highest power. Note that the current drawn from VCC and VCC_IO can vary significantly based
on Wi-Fi power consumption profiles.

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2.3.1 Module supply input (VCC)
NORA-W10 series modules use an integrated Linear Voltage converter to transform and stabilize the
supply voltage applied to the VCC pin. Typical Input voltage at VCC and VCC_IO pins is 3.3 V with an
operating voltage range between 3.3 V and 3.6 V.
⚠NORA-W10 must be supplied with a Class-1 PS1 (reg. IEC 62368-1) power supply.
2.3.2 Digital I/O interfaces reference voltage (VCC_IO)
NORA-W10 modules currently support 3.0–3.6 V IO voltage level only.
2.3.3 VCC application circuits
The power for NORA-W10 series modules is applied through the VCC pins. These supplies are taken
from either of the following sources:
•Switching Mode Power Supply (SMPS)
•Low Drop Out (LDO) regulator
An SMPS is the ideal design choice when the available primary supply source is significantly higher
than the operating supply voltage of the module. This offers the best power efficiency for the
application design and minimizes the amount of current drawn from the main supply source.
⚠When taking VCC supplies from an SMPS make sure that the AC ripple voltage is kept as low as
possible at the switching frequency. Design layouts should focus on minimizing the impact of any
high-frequency ringing.
Use an LDO linear regulator for primary VCC supplies that have a relatively low voltage. As LDO
regulators dissipate power linearly related to the step-down voltage, LDOs are not recommended for
step down of high voltages.
DC/DC efficiency should be regarded as a trade-off between the active and idle duty cycles of an
application. Although some DC/DC devices achieve high efficiency at light loads, these efficiencies
typically degrade as soon as the idle current drops below a few milliamps. This can have a negative
impact on the life of the battery.
If decoupling capacitors are needed on the supply rails, it is best practice to position these as close as
possible to the NORA-W10 series module. The power routing of some host system designs makes
decoupling capacitance unnecessary.
For electrical specifications, see also the appropriate NORA-W10 series data sheet [2].
2.4 Module reset
NORA-W10 is reset (rebooted) by setting the RESET_N pin to low. RESET_N has an internal pull-up
resistor setting its default state to high. The low-level input triggers a “hardware reset” of the module.
The RESET_N signal should be driven by an open drain, open collector, or contact switch. The chip
works at the minimum power when RESET_N is low (off).
2.5 Bootstrap pins
Several module pins related to the boot configuration must be strapped correctly using either pull-up
or pull-down resistors, as shown in Table 3.
⚠Boot strap pins should be avoided if other GPIO pins can be used instead. Note that all module pins
shown in bold are configured to their default state internally in the ESP32-S3 chip and must NOT
be configured externally.

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Pin
ESP32-S3
GPIO
State during
boot
Default
Behavior
Description
F7,
H7
GPIO0,
GPIO46
00
Download Boot
Booting mode
01
Invalid, do not use
10
Pull-up*, Pull-down*
Normal Boot from internal Flash
11
Normal Boot from internal Flash
J9
GPIO3
0
N/A
EFUSE_DIS_USB_JTAG = 0,
EFUSE_DIS_PAD_JTAG = 0,
EFUSE_STRAP_JTAG_SEL=1 JTAG signal
from on-chip JTAG pins
JTAG signal
selection
1
EFUSE_DIS_USB_JTAG = 0,
EFUSE_DIS_PAD_JTAG = 0,
EFUSE_STRAP_JTAG_SEL=1
JTAG signal from USB Serial/JTAG controller
D/C
EFUSE_DIS_USB_JTAG = 0,
EFUSE_DIS_PAD_JTAG = 0,
EFUSE_STRAP_JTAG_SEL=0
JTAG signal from USB Serial/JTAG controller
*About 45 kΩ.
Table 3: NORA-W10 series boot strapping pins
Pin F7 is used to enter the ESP bootloader. Consequently, this pin must be exposed on a pin header
(or similar) to flash the module. To enter bootloader mode, hold down theBoot pin F7 during the power
on. To enter the programming mode, assert a reset in bootloader mode. See Figure 4.
Figure 4: Button on Boot pin
2.6 Antenna integration
Antenna interfaces are different for each module variant in the NORA-W10 series. The modules
support either an internal antenna (NORA-W106) or external antennas connected through a
dedicated antenna pin (NORA-W101).
2.6.1 External RF antenna interface
NORA-W101 is equipped with an antenna signal (ANT) pin. The pin has a nominal characteristic
impedance of 50 and must be connected to the antenna through a 50 transmission line.
Choose an antenna with optimal radiating characteristics for the best electrical performance and
overall module functionality. An internal antenna, integrated on the application board or an external
antenna connected to the application board through a proper 50 connector, can be used.
When using an external antenna, the PCB-to-RF-cable transition must be implemented using either
a suitable 50 connector, or an RF-signal solder pad (including GND) that is optimized for 50 
characteristic impedance.

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2.6.1.1 Antenna matching
The antenna return loss should be as low as possible across the entire band to provide optimal
performance. The enclosure, shields, other components, and surrounding environment might impact
the return loss that is seen at the antenna port. Matching components are often required to retune
the antenna to 50 characteristic impedance.
It is difficult to predict the actual matching values for the antenna in the final form factor. Therefore,
it is good practice to have a placeholder in the circuit with a “pi” network, with two shunt components
and a series component in the middle. This allows maximum flexibility while tuning the matching to
the antenna feed.
2.6.1.2 Approved antenna designs
NORA-W10 modules come with a pre-certified design that can be used to save costs and time during
the certification process. To take full advantage of this service, you must implement the antenna
layout in accordance with u-blox reference designs. Reference designs are available on request from
u-blox.
The designer integrating a u-blox reference design into an end-product is solely responsible for any
unintentional RF emission generated by the end product.
The module may be integrated with other antennas. In which case, the OEM installer must certify the
design with respective regulatory agencies.
2.6.2 Internal antenna
NORA-W106 module have an internal antenna that are specifically designed and optimized for u-blox
Wi-Fi, Bluetooth Basic Rate/Enhanced Data Rate (BR/EDR), and Bluetooth LE modules. With
NORA-W106, designers only need to consider the module placement and GND clearance in antenna
area.
2.7 Data interfaces
2.7.1 Universal asynchronous serial interface (UART)
NORA-W10 modules have three UART interfaces, UART0 to UART2, for data communication and
firmware upgrade. Each interface provides asynchronous communication support for RS232, RS485,
and IrDA standards (with external drivers). Each UART supports the following signals:
•Data lines (RXD as input, TXD as output)
•Hardware flow control lines (CTS as input, RTS as output)
You can use the UARTs in 4-wire mode with hardware flow control, or in 2-wire mode with TXD and
RXD only.
☞2-wire mode is not recommended, because it is prone to buffer overruns.
The UART0 interface is used for firmware upgrade. See also Software.
It is recommended that the UART0 is either connected to a header for firmware upgrade or made
available for test points.
The IO level of the UART follows VCC_IO.
2.7.2 Serial peripheral interface (SPI)
Four SPI interfaces are available for the application. SPI0 is configured to internal flash storage, can
be controlled with chip select CS0. Additional flash cannot be connected to SPI0 interface, but an
external PSRAM can be connected. CS1 will become chip select for PSRAM.

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It is possible to connect the remaining SPI interfaces to other pins via the IO MUX but the maximum
speed will be reduced. It is also possible to configure the SPI interface as a dual or quad SPI (2 or 4-bit
bidirectional data signals). See also Dual/Quad SPI. The module can be configured as both SPI master
and slave.
⚠External flash cannot be used for code execution.
2.7.3 Dual/Quad SPI
The dual/quad SPI (2 or 4 bi-bidirectional data signals) can be used for connecting an additional
external PSRAM. The SPI to dual/quad SPI signal mappings is shown in Table 4.
SPI signal
Dual SPI signal
Quad SPI signal
MOSI
IO0
IO0
MISO
IO1
IO1
WP
-
IO2
HD
-
IO3
CS
CS
CS
CLK
CLK
CLK
Table 4: SPI to dual/quad SPI signal mapping
2.7.4 TWAI
NORA-W10 modules support the Two-Wire Automotive Interface TWAI) communication protocol,
with inherited with message priorities and arbitration. It provides multi-master and multi-cast
communication with error detection and signaling. The TWAI controller can operate at bit rates of
1 Kbit/s to 1 Mbit/s with 64-byte receive FIFO. It also supports CAN specification 2.0
2.8 Analog interfaces
2.8.1 Analog to digital converters
NORA-W10 modules support two 12-bit SAR Analog to Digital Converters (ADC). Any analog-capable
pin can be used for ADC application. All appropriate analog pins are shown in the Pinout.
For lower power consumption, NORA-W101, NORA-W106 modules can measure voltages in sleep
mode and threshold settings can be used to wake the CPU.
☞Analog pins cannot be re-routed to other pins through the IO MUX.
2.9 No-connect pins (NC)
Do not connect the NC pin. No-Connect pins are allocated for future interfaces and functionality.

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3Design-in
Follow the design guidelines stated in this chapter to optimize the integration of NORA-W10 series
modules in the final application board.
3.1 Overview
Although all application circuits must be properly designed, there are several points that require
special attention during application design. A list of these points, in order of importance, follows:
•Module antenna connection: ANT Pad
Antenna circuits affect the RF compliance of all applications that include the certification
schemes related to the module. To maintain compliance and subsequent certification of the
application design, it is important to observe the applicable parts of antenna schematic and layout
design described in Antenna interface.
•Module supply: VCC, VCC_IO, and GND pins.
Supply circuits can affect the RF performance. It is important to observe the schematic and layout
design for these supplies. See also VCC application circuits. Modules normally include several
supply pins described in the pin out of the NORA-W10 data sheet [2].
•High-speed interfaces: UART pins.
High-speed interfaces are a potential source of radiated noise that can affect the regulatory
compliance standards for radiated emissions. It is important to follow the schematic and layout
design recommendations described in the General high-speed layout guidelines.
•System functions: RESET_N, GPIO and other System input and output pins
Careful utilization of these pins in the application design is required to ensure correct boot up and
system operation. Ensure that the voltage level is correctly defined during module boot. It is
important to follow the schematic and layout design recommendations described in the General
high-speed layout guidelines.
•Other pins: ADC, CAN, and NC pins.
Careful utilization of these pins is required to guarantee proper functionality. It is important to
follow the schematic and layout design recommendations described in the General high-speed
layout guidelines.
UART_TX, UART_RXD and SYS_BOOT pins should be made accessible in order to flash regulatory
compliance testing firmware.
3.2 Antenna interface
NORA-W10 modules support the following antenna types:
•Internal antenna included on the NORA-W106 module.
•Integrated antenna on the main application PCB. Typically, a patch antenna mounted on the main
PCB or application housing, which is then connected to the NORA-W101 RF pin through a
transmission line.
•External Antenna. Typically, a monopole antenna connected to the NORA-W101 RF pin through a
coaxial cable and U.FL connector on the main PCB.

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Figure 5 summarizes each of the available antenna options.
Figure 5: Antenna options
As NORA-W10 modules cannot be mounted arbitrarily, the placement should be chosen with
consideration so that it does not interfere with radio communication. NORA-W106 modules include
an internal PCB trace antenna that cannot be mounted in a metal enclosure. No metal casing or
plastics using metal flakes should be used. Avoid metallic based paint or lacquer as well. NORA-W101
modules offer more freedom as an external antenna can be mounted further away from the module.
⚠When integrating the u-blox reference design into an end-product, the application designer is
solely responsible for any unintentional emission levels produced by the end-product.
⚠According to the FCC regulations, the transmission line from the module’s antenna pin to the
antenna or antenna connector on the host PCB is considered part of the approved antenna design.
Therefore, module integrators must either follow exactly one of the antenna reference designs
used in the module’s FCC type approval or certify their own designs.
3.2.1 RF transmission line design (NORA-W101)
RF transmission lines, such as the ones from the ANT pad up to the related antenna connector or up
to the related internal antenna pad, must be designed so that the characteristic impedance is as close
as possible to 50 .

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Figure 6 shows the design options for implementing a transmission line, namely:
•Microstrip –track separated with dielectric material and coupled to a single ground plane.
•Coplanar microstrip –track separated with dielectric material and coupled to both the ground plane
and side conductor.
•Stripline –track separated by dielectric material and sandwiched between two parallel ground
planes.
The parameters shown in the cross-sectional area of each trace design include:
•Width (W) –shows the width of the copper layer on the top layer
•Distance (S) –shows the distance between the top copper layer and the two adjacent GND planes.
•Dielectric substrate thickness (H) –shows the distance between the GND reference on the bottom
plane and the copper layer on the top layer.
•Thickness of the copper layer (T) –can also be represented by “Base Copper Weight”, which is
commonly used as the parameter for PCB stack-up.
•Dielectric constant (εr) defines the ratio between the electric permeability of the material against
the electric permeability of free space.
☞The width of a 50 Ω microstrip depends on “εr”and “H”, which must be calculated for each PCB
layer stack-up.
Figure 6: Transmission line trace design
Follow these recommendations to design a 50 transmission line correctly:
•The designer should provide enough clearance from surrounding traces and ground in the same
layer; in general, a trace to ground clearance of at least two times the trace width should be
considered. The transmission line should also be “guarded” by ground plane area on each side.
•The characteristic impedance can be calculated as first iteration using tools provided by the layout
software. It is advisable to ask the PCB manufacturer to provide the final values that are usually
calculated using dedicated software and available stack-ups from production. It could also be
possible to request an impedance coupon on panel’s side to measure the real impedance of the
traces.
•FR-4 dielectric material, although its high losses at high frequencies can be considered in RF
designs provided that:

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oRF trace length must be minimized to reduce dielectric losses.
oIf traces longer than few centimeters are needed, it is recommended to use a coaxial connector
and cable to reduce losses
oStack-up should allow for thick 50 traces and at least 200 µm trace width is recommended
to assure good impedance control over the PCB manufacturing process.
oFR-4 material exhibits poor thickness stability and thus less control of impedance over the
trace length. Contact the PCB manufacturer for specific tolerance of controlled impedance
traces.
•The width of the transmission lines and spacing to GND must be uniform and routed as smoothly
as possible: route RF lines in 45 °C angle or in arcs.
•Add GND stitching vias around transmission lines.
•Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground
layer, providing enough vias on the adjacent metal layer.
•Route RF transmission lines far from any noise source (as switching supplies and digital lines) and
from any sensitive circuit to avoid crosstalk between RF traces and Hi-impedance or analog
signals.
•Avoid stubs on the transmission lines, any component on the transmission line should be placed
with the connected pad over the trace. Also avoid any unnecessary component on RF traces.
3.2.2 Antenna design (NORA-W101)
NORA-W101 is suited for designs when an external antenna is needed due to mechanical integration
or placement of the module.
Designers must take care of the antennas from all perspective at the beginning of the design phase
when the physical dimensions of the application board are under analysis/decision, as the RF
compliance of the device integrating NORA-W101 module with all theapplicable required certification
schemes heavily depends on the radiating performance of the antennas. The designer is encouraged
to consider one of the u-blox suggested antenna part numbers and follow the layout requirements.
•External antennas such as linear monopole:
oExternal antennas basically do not imply physical restriction to the design of the PCB where
the module is mounted.
oThe radiation performance mainly depends on the antennas. It is required to select antennas
with optimal radiating performance in the operating bands.
oRF cables should carefully be selected with minimum insertion losses. Additional insertion loss
will be introduced by low quality or long cable. Large insertion loss reduces radiation
performance.
oA high quality 50 coaxial connector provides proper PCB-to-RF-cable transition.