Fujitsu MB90460 Series User manual

The following document contains information on Cypress products.

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90460/465 Series
HARDWARE MANUAL
CM44-10120-4E

FUJITSU MICROELECTRONICS LIMITED
F
2
MC-16LX
16-BIT MICROCONTROLLER
MB90460/465 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/

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PREFACE
■Objectives and intended reader
Thank you for purchasing Fujitsu Microelectronics products.
The MB90460/465 series was developed as a group of general-purpose models in the F2MC-16LX Family,
which is a family of original 16-bit single-chip microcontrollers that can be used for application specific ICs
(ASICs).
This manual is intended for engineers who design products using the MB90460/465 series of
microcontrollers. The manual describes the functions and operation of the MB90460/465 series.
Note: F2MC is a registered of Fujitsu Microelectronics Limited and stands for FUJITSU Flexible Microcontroller.
■Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■Organization of this manual
This manual consists of the following 24 chapters and 1 appendix:
Chapter 1 Overview
This chapter describes the features and basic specifications of the MB90460/465 series.
Chapter 2 Notes on Handling Devices
This chapter describes notes on Handling Devices.
Chapter 3 CPU
This chapter describes the memory space of the MB90460/465 series.
Chapter 4 Reset
This chapter describes the reset function of the MB90460/465 series.
Chapter 5 Clock
This chapter describes the clocks of the MB90460/465 series.
Chapter 6 Low Power Consumption Mode
This chapter describes the energy-saving mode of the MB90460/465 series.
Chapter 7 Interrupt
This chapter describes the interrupts and extended intelligent I/O services of the MB90460/465 series.
Chapter 8 Mode Setting
This chapter describes the operating modes and memory access mode of the MB90460/465 series.
Chapter 9 I/O Port
This chapter describes the functions and operation of the MB90460/465 series I/O ports.
Chapter 10 Time-base Timer
This chapter describes the functions and operation of the MB90460/465 series time-base timer.
Chapter 11 Watchdog Timer
This chapter describes the functions and operation of the MB90460/465 series watchdog timer.

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Chapter 12 16-bit Reload Timer
This chapter describes the functions and operation of the MB90460/465 series 16-bit reload timer.
Chapter 13 16-bit PPG Timer
This chapter describes the functions and operation of the MB90460/465 series 16-bit PPG timer.
Chapter 14 Multi-functional Timer
This chapter describes the functions and operation of the MB90460/465 series multi-functional timer.
Chapter 15 Multi-pulse Generator
This chapter describes the functions and operation of the MB90460/465 series multi-pulse generator.
Chapter 16 PWC Timer
This chapter describes the functions and operation of the MB90460/465 series PWC timer.
Chapter 17 UART
This chapter describes the functions and operation of the MB90460/465 series UART.
Chapter 18 DTP/External Interrupt Circuit
This chapter describes the functions and operation of the MB90460/465 series DTP/external interrupt
circuit.
Chapter 19 Delayed Interrupt Generator Module
This chapter describes the functions and operation of the MB90460/465 series delayed interrupt generator
module.
Chapter 20 8/10-bit A/D Converter
This chapter describes the functions and operation of the MB90460/465 series 8/10-bit A/D Converter.
Chapter 21 ROM Correction Function
This chapter describes the functions and operation of the MB90460/465 series ROM correction function.
Chapter 22 ROM Mirroring Function Selection Module
This chapter describes the functions and operation of the MB90460/465 series ROM mirroring function
selection module.
Chapter 23 512K / 1024K bit Flash Memory
This chapter describes the functions and operation of the MB90460/465 series 512K / 1024K bit flash
memory.
Chapter 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL
WRITING
This chapter describes examples of F2MC-16LX MB90F462/F462A/F463A connections for serial
writing.
Appendix
Appendix A I/O Map
The appendix A contains an I/O map and instruction overview.
Appendix B Instructions
The appendix B contains an instruction overview.

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Copyright ©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-
party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

iv

v
CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 MB90460/465 Series Features ........................................................................................................... 2
1.2 MB90460/465 Series Product line-up ................................................................................................. 5
1.3 Block Diagram of MB90460/465 Series .............................................................................................. 7
1.4 Pin Assignment ................................................................................................................................... 8
1.5 Package Dimensions ........................................................................................................................ 11
1.6 I/O Pins and Pin Functions ............................................................................................................... 14
1.7 I/O Circuit Types ............................................................................................................................... 19
CHAPTER 2 NOTES ON HANDLING DEVICES ............................................................ 23
2.1 Notes on Handling Devices .............................................................................................................. 24
CHAPTER 3 CPU ............................................................................................................ 27
3.1 CPU .................................................................................................................................................. 28
3.2 Memory Space .................................................................................................................................. 29
3.3 Memory Maps ................................................................................................................................... 31
3.4 Addressing ........................................................................................................................................ 33
3.4.1 Address Specification by Linear Addressing ............................................................................... 34
3.4.2 Address Specification by Bank Addressing ................................................................................. 35
3.5 Memory Location of Multi-byte Data ................................................................................................. 37
3.6 Registers ........................................................................................................................................... 39
3.7 Dedicated Registers ......................................................................................................................... 40
3.7.1 Accumulator (A) ........................................................................................................................... 42
3.7.2 Stack Pointers (USP, SSP) ......................................................................................................... 45
3.7.3 Processor Status (PS) ................................................................................................................. 47
3.7.4 Condition Code Register (PS: CCR) .......................................................................................... 48
3.7.5 Register Bank Pointer (PS: RP) .................................................................................................. 50
3.7.6 Interrupt Level Mask Register (PS: ILM) ..................................................................................... 51
3.7.7 Program Counter (PC) ................................................................................................................. 52
3.7.8 Direct Page Register (DPR) ........................................................................................................ 53
3.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................ 54
3.8 General-purpose Registers ............................................................................................................... 55
3.9 Prefix Codes ..................................................................................................................................... 57
3.9.1 Bank Select Prefix (PCB, DTB, ADB, SPB) ................................................................................. 58
3.9.2 Common Register Bank Prefix (CMR) ......................................................................................... 60
3.9.3 Flag Change Suppression Prefix (NCC) ...................................................................................... 61
3.9.4 Restrictions on Prefix Codes ....................................................................................................... 62
CHAPTER 4 RESET ........................................................................................................ 65
4.1 Reset ................................................................................................................................................ 66
4.2 Reset Causes and Oscillation Stabilization Wait Intervals ............................................................... 68
4.3 External Reset Pin ............................................................................................................................ 69
4.4 Reset Operation ................................................................................................................................ 71

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4.5 Reset Cause Bits .............................................................................................................................. 73
4.6 Status of Pins in a Reset .................................................................................................................. 75
CHAPTER 5 CLOCK ....................................................................................................... 77
5.1 Clock ................................................................................................................................................. 78
5.2 Block Diagram of the Clock Generation Block .................................................................................. 80
5.3 Clock Selection Register (CKSCR) ................................................................................................... 82
5.4 Clock Mode ....................................................................................................................................... 84
5.5 Oscillation Stabilization Wait Interval ................................................................................................ 86
5.6 Connection of an Oscillator or an External Clock to the Microcontroller ........................................... 87
CHAPTER 6 LOW POWER CONSUMPTION MODE ..................................................... 89
6.1 Low Power Consumption Mode ........................................................................................................ 90
6.2 Block Diagram of the Low Power Consumption Control Circuit ........................................................ 92
6.3 Low Power Consumption Mode Control Register (LPMCR) ............................................................. 94
6.4 CPU Intermittent Operation Mode .................................................................................................... 97
6.5 Standby Mode ................................................................................................................................... 98
6.5.1 Sleep Mode ................................................................................................................................. 99
6.5.2 Time-base Timer Mode ............................................................................................................. 102
6.5.3 Stop Mode ................................................................................................................................. 104
6.6 State Change Diagram ................................................................................................................... 106
6.7 State of Pins in Standby Mode and during Reset ........................................................................... 109
6.8 Usage Notes on Low Power Consumption Mode ........................................................................... 110
CHAPTER 7 INTERRUPT ............................................................................................. 113
7.1 Interrupt .......................................................................................................................................... 114
7.2 Interrupt Causes and Interrupt Vectors ........................................................................................... 116
7.3 Interrupt Control Registers and Peripheral Functions ..................................................................... 119
7.3.1 Interrupt Control Registers (ICR00 to ICR15) ........................................................................... 121
7.3.2 Interrupt Control Register Functions .......................................................................................... 123
7.4 Hardware Interrupt .......................................................................................................................... 126
7.4.1 Operation of Hardware Interrupt ................................................................................................ 129
7.4.2 Processing for Interrupt Operation ............................................................................................ 131
7.4.3 Procedure for using Hardware Interrupt .................................................................................... 132
7.4.4 Multiple Interrupts ...................................................................................................................... 133
7.4.5 Hardware Interrupt Processing Time ......................................................................................... 135
7.5 Software Interrupt ........................................................................................................................... 137
7.6 Interrupt of Extended Intelligent I/O Service (EI2OS) ..................................................................... 139
7.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ........................................................ 141
7.6.2 Registers of EI2OS Descriptor (ISD) ......................................................................................... 142
7.6.3 Operation of the Extended Intelligent I/O Service (EI2OS) ........................................................ 145
7.6.4 Procedure for using the Extended Intelligent I/O Service (EI2OS) ............................................ 146
7.6.5 Processing Time of the Extended Intelligent I/O Service (EI2OS) ............................................. 147
7.7 Exception Processing Interrupt ....................................................................................................... 149
7.8 Stack Operations for Interrupt Processing ...................................................................................... 150
7.9 Sample Programs for Interrupt Processing ..................................................................................... 152

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CHAPTER 8 MODE SETTING ....................................................................................... 157
8.1 Mode Setting ................................................................................................................................... 158
8.2 Mode Pins (MD2 to MD0) ............................................................................................................... 159
8.3 Mode Data ...................................................................................................................................... 160
CHAPTER 9 I/O PORT .................................................................................................. 163
9.1 Overview of I/O Port ....................................................................................................................... 164
9.2 Registers of I/O Port ....................................................................................................................... 166
9.3 Port 0 .............................................................................................................................................. 167
9.3.1 Port 0 Registers (PDR0, DDR0 and RDR0) .............................................................................. 169
9.3.2 Operation of Port 0 .................................................................................................................... 171
9.4 Port 1 .............................................................................................................................................. 173
9.4.1 Port 1 Registers (PDR1, DDR1 and RDR1) .............................................................................. 175
9.4.2 Operation of Port 1 .................................................................................................................... 176
9.5 Port 2 .............................................................................................................................................. 178
9.5.1 Port 2 Registers (PDR2 and DDR2) .......................................................................................... 180
9.5.2 Operation of Port 2 .................................................................................................................... 181
9.6 Port 3 .............................................................................................................................................. 183
9.6.1 Port 3 Registers (PDR3 and DDR3) .......................................................................................... 185
9.6.2 Operation of Port 3 .................................................................................................................... 186
9.7 Port 4 .............................................................................................................................................. 188
9.7.1 Port 4 Registers (PDR4 and DDR4) .......................................................................................... 190
9.7.2 Operation of Port 4 .................................................................................................................... 191
9.8 Port 5 .............................................................................................................................................. 193
9.8.1 Port 5 Registers (PDR5, DDR5 and ADER) .............................................................................. 195
9.8.2 Operation of Port 5 .................................................................................................................... 196
9.9 Port 6 .............................................................................................................................................. 198
9.9.1 Port 6 Registers (PDR6 and DDR6) .......................................................................................... 200
9.9.2 Operation of Port 6 .................................................................................................................... 201
9.10 Sample I/O Port Program ............................................................................................................... 203
CHAPTER 10 TIME-BASE TIMER .................................................................................. 205
10.1 Overview of the Time-base Timer ................................................................................................... 206
10.2 Configuration of the Time-base Timer ............................................................................................ 208
10.3 Time-base Timer Control Register (TBTC) ..................................................................................... 209
10.4 Time-base Timer Interrupts ............................................................................................................ 211
10.5 Operation of the Time-base Timer .................................................................................................. 212
10.6 Usage Notes on the Time-base Timer ............................................................................................ 214
10.7 Sample Program for the Time-base Timer Program ....................................................................... 216
CHAPTER 11 WATCHDOG TIMER ................................................................................ 219
11.1 Overview of the Watchdog Timer ................................................................................................... 220
11.2 Configuration of the Watchdog Timer ............................................................................................. 221
11.3 Watchdog Timer Control Register (WDTC) .................................................................................... 222
11.4 Operation of the Watchdog Timer ................................................................................................... 224
11.5 Usage Notes on the Watchdog Timer ............................................................................................. 226
11.6 Sample Program for the Watchdog Timer ...................................................................................... 227

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CHAPTER 12 16-BIT RELOAD TIMER ........................................................................... 229
12.1 Overview of the 16-bit Reload Timer .............................................................................................. 230
12.2 Block Diagram of the 16-bit Reload Timer ...................................................................................... 233
12.3 16-bit Reload Timer Pins ................................................................................................................ 235
12.4 16-bit Reload Timer Registers ........................................................................................................ 236
12.4.1 Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1) ........................................ 237
12.4.2 Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1) ......................................... 239
12.4.3 16-bit Timer Register (TMR0/TMR1) ......................................................................................... 241
12.4.4 16-bit Reload Register (TMRD0/TMRD1) .................................................................................. 242
12.5 16-Bit Reload Timer Interrupts ........................................................................................................ 243
12.6 Operation of the 16-bit Reload Timer ............................................................................................. 244
12.6.1 Internal Clock Mode (reload mode) ........................................................................................... 246
12.6.2 Internal Clock Mode (single-shot mode) .................................................................................... 248
12.6.3 Event Count Mode ..................................................................................................................... 250
12.7 Usage Notes on the 16-bit Reload Timer ....................................................................................... 252
12.8 Sample Programs for the 16-bit Reload Timer ............................................................................... 253
CHAPTER 13 16-BIT PPG TIMER .................................................................................. 257
13.1 Overview of 16-bit PPG Timer ........................................................................................................ 258
13.2 Block Diagram of 16-bit PPG Timer ................................................................................................ 259
13.3 16-bit PPG Timer Pins .................................................................................................................... 260
13.4 16-bit PPG Timer Registers ............................................................................................................ 262
13.4.1 PPG Down Counter Register (PDCR0 to PDCR2) .................................................................... 264
13.4.2 PPG Period Setting Buffer Register (PCSR0 to PCSR2) .......................................................... 265
13.4.3 PPG Duty Setting Buffer Register (PDUT0 to PDUT2) ............................................................. 266
13.4.4 PPG Control Status Register (PCNTL0 to PCNTL2, PCNTH0 to PCNTH2) ............................. 267
13.5 16-bit PPG Timer Interrupts ............................................................................................................ 271
13.6 Operation of 16-bit PPG Timer ....................................................................................................... 273
13.7 Usage Notes on the 16-bit PPG Timer ........................................................................................... 276
13.8 Sample Programs for the 16-bit PPG Timer ................................................................................... 277
CHAPTER 14 MULTI-FUNCTIONAL TIMER .................................................................. 279
14.1 Overview of Multi-functional Timer ................................................................................................. 280
14.2 Block Diagram of Multi-functional Timer ......................................................................................... 282
14.3 Multi-functional Timer Pins ............................................................................................................. 286
14.4 Registers of Multi-functional Timer ................................................................................................. 289
14.4.1 Compare Clear Buffer Register (CPCLRB) and Compare Clear Register (CPCLR) ................. 293
14.4.2 Timer Data Register (TCDT) ..................................................................................................... 294
14.4.3 Timer Control Status Register (TCCSH, TCCSL) ...................................................................... 295
14.4.4 Output Compare Buffer Registers (OCCPB0 to OCCPB5) /
Output Compare Registers (OCCP0 to OCCP5) ....................................................................... 299
14.4.5 Compare Control Registers (OCS0 to OCS5) ........................................................................... 301
14.4.6 Input Capture Register (IPCP0 to IPCP3) ................................................................................. 305
14.4.7 Input Capture Control Status Registers (ICS23, PICS01) ......................................................... 306
14.4.8 16-bit Timer Register (TMRR0/TMRR1/TMRR2) ....................................................................... 313
14.4.9 16-bit Timer Control Register (DTCR0/DTCR1/DTCR2) ........................................................... 314
14.4.10 Waveform Control Register (SIGCR) ........................................................................................ 318

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14.5 Multi-functional Timer Interrupts ..................................................................................................... 320
14.6 Operation of Multi-functional Timer ................................................................................................. 324
14.6.1 Operation of 16-bit free-run timer .............................................................................................. 325
14.6.2 Operation of 16-bit Output Compare ......................................................................................... 332
14.6.3 Operation of 16-bit Input Capture .............................................................................................. 337
14.6.4 Operation of Waveform Generator ............................................................................................ 339
14.7 Usage Notes on the Multi-functional Timer ..................................................................................... 349
14.8 Sample Programs for the Multi-functional Timer ............................................................................ 351
CHAPTER 15 MULTI-PULSE GENERATOR .................................................................. 355
15.1 Overview of Multi-pulse Generator ................................................................................................. 356
15.2 Block Diagram of Multi-pulse Generator ......................................................................................... 359
15.3 Multi-pulse Generator Pins ............................................................................................................. 367
15.4 Registers of Multi-pulse Generator ................................................................................................. 369
15.4.1 Output Control Register (OPCR) ............................................................................................... 372
15.4.2 Output Data Register (OPDR) ................................................................................................... 376
15.4.3 Output Data Buffer Register (OPDBR) ...................................................................................... 380
15.4.4 Input Control Register (IPCR) .................................................................................................... 384
15.4.5 Compare Clear Register (CPCR) .............................................................................................. 388
15.4.6 Timer Buffer Register (TMBR) ................................................................................................... 389
15.4.7 Timer Control Status Register (TCSR) ...................................................................................... 390
15.4.8 Noise Cancellation Control Register (NCCR) ............................................................................ 392
15.5 Multi-pulse Generator Interrupts ..................................................................................................... 394
15.6 Operation of Multi-pulse Generator ................................................................................................ 397
15.6.1 Operation of Position Detection ................................................................................................. 399
15.6.2 Operation of Data Write Control Unit ......................................................................................... 401
15.6.3 Operation of Output Data Buffer Register ................................................................................. 405
15.6.4 Operation of Data Transfer of Output Data Register ................................................................. 407
15.6.5 Operation of DTTI1 Input Control .............................................................................................. 421
15.6.6 Operation of Noise Cancellation Function ................................................................................. 424
15.6.7 Operation of 16-bit Timer ........................................................................................................... 425
15.7 Usage Notes on the Multi-pulse Generator .................................................................................... 429
15.8 Sample Programs for the Multi-pulse Generator ............................................................................ 431
CHAPTER 16 PWC Timer ............................................................................................... 433
16.1 Overview of the PWC Timer ........................................................................................................... 434
16.2 Block Diagram of the PWC Timer ................................................................................................... 435
16.3 PWC Timer Pins ............................................................................................................................. 436
16.4 PWC Timer Registers ..................................................................................................................... 438
16.4.1 PWC Control Status Register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) ................................ 439
16.4.2 PWC Data Buffer Register (PWC0/PWC1) ............................................................................... 443
16.4.3 Division Rate Control Register (DIV0/DIV1) .............................................................................. 444
16.5 PWC Timer Interrupts ..................................................................................................................... 445
16.6 Operation of the PWC Timer .......................................................................................................... 447
16.6.1 Operation Mode Selection ......................................................................................................... 450
16.6.2 Starting and Stopping the Timer and Pulse-width Measurement and Clearing the Timer ......... 451
16.6.3 Timer Mode Operation ............................................................................................................... 453

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16.6.4 Pulse Width Measurement Mode Operation .............................................................................. 456
16.7 Usage Notes on the PWC Timer .................................................................................................... 461
16.8 Sample Programs for the PWC Timer ............................................................................................ 464
CHAPTER 17 UART ........................................................................................................ 467
17.1 Overview of UART .......................................................................................................................... 468
17.2 Block Diagram of UART .................................................................................................................. 470
17.3 UART Pins ...................................................................................................................................... 473
17.4 UART Registers .............................................................................................................................. 475
17.4.1 Serial Control Register (SCR0/SCR1) ....................................................................................... 476
17.4.2 Serial Mode Register (SMR0/SMR1) ....................................................................................... 478
17.4.3 Serial Status Register (SSR0/SSR1) ........................................................................................ 480
17.4.4 Input Data Register (SIDR0/SIDR1) and Output Data Register (SOR0/SOR1) ........................ 482
17.4.5 Communication Prescaler Control Register (CDCR) ................................................................. 484
17.5 UART Interrupts .............................................................................................................................. 486
17.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................ 488
17.5.2 Transmission Interrupt Generation and Flag Set Timing ........................................................... 489
17.6 UART Baud Rates .......................................................................................................................... 490
17.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ........................................ 492
17.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) ............................... 495
17.6.3 Baud Rates Determined Using the External Clock .................................................................... 497
17.7 Operation of UART ......................................................................................................................... 498
17.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) ................................................. 500
17.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 502
17.7.3 Bidirectional Communication Function (Normal Mode) ............................................................. 504
17.7.4 Master-slave Communication Function (Multiprocessor Mode) ................................................. 506
17.8 Usage Notes on UART ................................................................................................................... 509
17.9 Sample Program for UART ............................................................................................................. 510
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ................................................. 513
18.1 Overview of the DTP/External Interrupt Circuit ............................................................................... 514
18.2 Block Diagram of the DTP/External Interrupt Circuit ...................................................................... 516
18.3 DTP/External Interrupt Circuit Pins ................................................................................................. 518
18.4 DTP/External Interrupt Circuit Registers ......................................................................................... 520
18.4.1 DTP/interrupt Cause Register (EIRR) ....................................................................................... 521
18.4.2 DTP/interrupt Enable Register (ENIR) ....................................................................................... 522
18.4.3 Request Level Setting Register (ELVR) .................................................................................. 524
18.5 Operation of the DTP/External Interrupt Circuit .............................................................................. 525
18.5.1 External Interrupt Function ........................................................................................................ 528
18.5.2 DTP Function ............................................................................................................................. 529
18.6 Usage Notes on the DTP/External Interrupt Circuit ........................................................................ 530
18.7 Sample Programs for the DTP/External Interrupt Circuit ................................................................ 532
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ................................... 535
19.1 Overview of the Delayed Interrupt Generator Module .................................................................... 536
19.2 Delayed Interrupt Generator Module Register ................................................................................ 537
19.3 Operation of the Delayed Interrupt Generator Module ................................................................... 538

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19.4 Usage Notes on the Delayed Interrupt Generator Module ............................................................. 539
CHAPTER 20 8/10-BIT A/D CONVERTER ..................................................................... 541
20.1 Overview of the 8/10-bit A/D Converter .......................................................................................... 542
20.2 Block Diagram of the 8/10-bit A/D Converter .................................................................................. 544
20.3 8/10-bit A/D Converter Pins ............................................................................................................ 546
20.4 8/10-bit A/D Converter Registers .................................................................................................... 548
20.4.1 A/D Control Status Register 1 (ADCS1) .................................................................................. 549
20.4.2 A/D Control Status Register 0 (ADCS0) .................................................................................. 551
20.4.3 A/D Data Register (ADCR0/ADCR1) ....................................................................................... 554
20.5 8/10-bit A/D Converter Interrupts .................................................................................................... 556
20.6 Operation of the 8/10-bit A/D Converter ......................................................................................... 557
20.6.1 Conversion using EI2OS .......................................................................................................... 560
20.6.2 A/D Conversion Data Protection Function ............................................................................... 561
20.7 Usage Notes on the 8/10-bit A/D Converter ................................................................................... 563
20.8 Sample Program 1 for the 8/10-bit A/D Converter (Single Conversion Mode Using EI2OS) .......... 564
20.9 Sample Program 2 for the 8/10-bit A/D Converter (Continuous Conversion Mode Using EI2OS) .. 566
20.10 Sample Program 3 for the 8/10-bit A/D Converter (Stop Conversion Mode Using EI2OS) ............ 568
CHAPTER 21 ROM CORRECTION FUNCTION ............................................................. 571
21.1 Overview of the ROM Correction Function ..................................................................................... 572
21.2 Block Diagram of ROM Correction Function ................................................................................... 573
21.3 ROM Correction Function Registers ............................................................................................... 574
21.3.1 Program Aaddress Detection Register (PADR0/PADR1) ......................................................... 575
21.3.2 Program Address Detection Control Status Register (PACSR) ................................................ 576
21.4 Operation of the ROM Correction Function .................................................................................... 578
21.5 Example of Using ROM Correction Function .................................................................................. 579
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 583
22.1 Overview of the ROM Mirroring Function Selection Module ........................................................... 584
22.2 ROM Mirroring Function Selection Register (ROMM) .................................................................... 585
CHAPTER 23 512K / 1024K BIT FLASH MEMORY ....................................................... 587
23.1 Overview of the 512K / 1024K Bit Flash Memory ........................................................................... 588
23.2 512K / 1024K Bit Flash Memory Sector Configuration ................................................................... 589
23.3 Flash Memory Control Status Register (FMCS) ............................................................................. 590
23.4 Method of Starting the Automatic Algorithm in Flash Memory ........................................................ 592
23.5 Verifying Automatic Algorithm Execution Status ............................................................................. 593
23.5.1 Data Polling Flag (DQ7) ............................................................................................................ 595
23.5.2 Toggle Bit Flag (DQ6) ................................................................................................................ 597
23.5.3 Time limit Exceeded Flag (DQ5) .............................................................................................. 598
23.5.4 Sector Deletion Timer Flag (DQ3) ............................................................................................. 599
23.6 Detailed Explanation on the Flash Memory Write/Delete ............................................................... 600
23.6.1 Setting the Read/Reset Status .................................................................................................. 601
23.6.2 Writing the Data ......................................................................................................................... 602
23.6.3 Deleting the Data (Chip Deletion) .............................................................................................. 604
23.6.4 Deleting the Data (Sector Deletion) ........................................................................................... 605

xii
23.6.5 Temporarily Stopping the Sector Deletion ................................................................................. 607
23.6.6 Restarting the Sector Deletion ................................................................................................... 608
23.7 Flash Security Feature .................................................................................................................... 609
23.8 Programming Example of 512K Bit Flash Memory ......................................................................... 610
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION
FOR SERIAL WRITING ............................................................................ 615
24.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard) ......................................... 616
24.2 Example of Connection for Serial Writing (When Power Supplied by User) ................................... 618
24.3 Example of Connection for Serial Writing (When Power Supplied from Writer) ............................. 620
24.4 Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied by User) .................................................................................................... 622
24.5 Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied from Writer) ............................................................................................... 624
APPENDIX ......................................................................................................................... 627
APPENDIX A I/O MAP ............................................................................................................................... 628
APPENDIX B Instructions ........................................................................................................................... 635
B.1 Instruction Types ............................................................................................................................ 636
B.2 Addressing ..................................................................................................................................... 637
B.3 Direct Addressing ........................................................................................................................... 639
B.4 Indirect Addressing ........................................................................................................................ 645
B.5 Execution Cycle Count ................................................................................................................... 653
B.6 Effective address field .................................................................................................................... 656
B.7 How to Read the Instruction List .................................................................................................... 657
B.8 F2MC-16LX Instruction List ............................................................................................................ 660
B.9 Instruction Map ............................................................................................................................... 674
INDEX................................................................................................................................... 697

xiii
Main changes in this edition
Page Section Change Results
- The product name is changed to "MB90460/465 series".
83 CHAPTER 5 CLOCK
5.3 Clock Selection Register (CKSCR) The function column of bit 14 in Table 5.3-1 is changed.
("·Writing has no effect on the operation." is added.)
106 CHAPTER 6 LOW POWER CONSUMPTION MODE
6.6 State Change Diagram Figure 6.6-1 is changed.
109
CHAPTER 6
LOW POWER CONSUMPTION MODE
6.7 State of Pins in Standby Mode and during
Reset
"*3" under Table 6.7-1 is changed.
123 CHAPTER 7 INTERRUPT
7.3.2 Interrupt Control Register Functions The summary is changed.
230 CHAPTER 12 16-BIT RELOAD TIMER
12.1 Overview of the 16-bit Reload Timer "●External trigger operation" is changed.
253 CHAPTER 12 16-BIT RELOAD TIMER 12.8 Sample Programs for the 16-bit Reload
Timer "●Coding example" is changed.
298
CHAPTER 14
MULTI-FUNCTIONAL TIMER
14.4.3 Timer Control Status Register
(TCCSH, TCCSL)
The function column of bit 3 in Table 14.4-2 is changed.
("·Even after "1" is written, the counter value is not initialized
if "0" is written to this bit before the next count clock." is
added.)
521 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.1 DTP/interrupt Cause Register (EIRR)
"■DTP/interrupt Cause Register (EIRR)" is changed.
("Notes:" is added.)
522 CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.2 DTP/interrupt Enable Register (ENIR)
"■DTP/interrupt Enable Register (ENIR)" is changed.
("Note:" is added.)
525
CHAPTER 18
DTP/EXTERNAL INTERRUPT CIRCUIT
18.5 Operation of the DTP/External Interrupt
Circuit
"■Setting the DTP/external Interrupt Circuit" is changed.
("1. Set as an input port the general I/O port to be used also as
a pin to input external interrupts." is added.)
530
CHAPTER 18
DTP/EXTERNAL INTERRUPT CIRCUIT
18.6 Usage Notes on the DTP/External
Interrupt Circuit
"●Input polarities of external interrupts" is changed.
("If the request input level is level setting, the pulse width
requires a longer period than the minimum pulse width stated
on the data sheet. Also, as long as the interrupt input pin
retains the active level, interrupt requests continue to be
generated to the interrupt controller, even if the DTP/external
interrupt cause register is cleared." is added.)
552 CHAPTER 20 8/10-BIT A/D CONVERTER
20.4.2 A/D Control Status Register 0 (ADCS0) The function column of bit5 to bit3 in Table 20.4-2 is changed. ("Notes:" is added.)

xiv
The vertical lines marked in the left side of the page show the changes.
607
CHAPTER 23
512K / 1024K BIT FLASH MEMORY
23.6.5 Temporarily Stopping the Sector
Deletion
"■Temporarily Stopping the Sector Deletion" is changed.
(·up to 15 µs →up to 20 µs
·The sector deletion temporary stop command must be
executed 20 µs or more after the sector deletion command or
sector deletion restart command is issued.)
616
CHAPTER 24
EXAMPLE OF F2MC-16LX MB90F462/
F462A/F463A CONNECTION FOR SERIAL
WRITING
24.1 Standard Configuration for Serial
On-board Writing (Fujitsu Standard)
Table 24.1-1 is changed.
Page Section Change Results

1
CHAPTER 1
OVERVIEW
This chapter describes the main features and basic
specifications of the MB90460/465 series.
1.1 MB90460/465 Series Features
1.2 MB90460/465 Series Product line-up
1.3 Block Diagram of MB90460/465 Series
1.4 Pin Assignment
1.5 Package Dimensions
1.6 I/O Pins and Pin Functions
1.7 I/O Circuit Types