ZiLOG ZNEO Z16F Series User manual

Copyright ©2008 by Zilog®, Inc. All rights reserved.
www.zilog.com
ZNEO®Z16F Series
Development Kit
User Manual
UM020205-0908
Z16F2800100ZCOG

ZNEO®Z16F Series Development Kit
User Manual
UM020205-0908
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN
LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN
APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant
into the body, or (b) support or sustain life and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in a significant injury to the user. A critical component is any
component in a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the
devices, applications, or technology described is intended to suggest possible uses and
may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR
PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION,
DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION,
DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The
information contained within this document has been verified according to the general
principles of electrical and mechanical engineering.
ZNEO is a registered trademark of Zilog, Inc. All other product or service names are the
property of their respective owners.
Warning:

ZNEO®Z16F Series Development Kit
User Manual
UM020205-0908 Revision History
iii
Revision History
Each instance in Revision History reflects a change to this document from
its previous revision. For more details, refer to the corresponding pages
and appropriate links in the table below.
Date Revision Level Description Page No
September
2008 05 Updated Introduction section. 1
September
2007 04 Updated Title, Schematics. Implemented Zilog Style Guide. All
June 2006 03 Added note on the ZNEO development board 16-bit
bus and programming external Flash memory. 5
May 2006 02 Updated all schematics. 12
Jan. 2006 01 Original Issue All

ZNEO®Z16F Series Development Kit
User Manual
UM020205-0908 Table of Contents
iv
Table of Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ZNEO Z16F Series Development Board . . . . . . . . . . . . . . . . . . . . . . 2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Development Kit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4
ZNEO MEMORY LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UART with IrDA ENDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switches and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External Interface Headers JP1, JP2, and JP4 . . . . . . . . . . . . . . . 11
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ZNEO®Z16F Series Development Kit
User Manual
UM020205-0908 Introduction
1
Introduction
Zilog’s ZNEO®Z16F Series MCU is part of its microcontroller products.
The ZNEO Z16F Series MCU Development Kit (Z16F2800100ZCOG)
familiarizes with the hardware and software tools available with this
product. This kit consists of the 128 KB version of the ZNEO
development board that supports and presents the features of the ZNEO
Z16F Series. This kit allows you to write application software and
contains all supporting documents.
This User Manual acquaints you with the ZNEO Z16F Series MCU
Development Kit, and provides instructions on setting up and using the
tools to start building designs and applications.
Z16F2811AL20SG is the silicon used in the board. For more details, refer
to ZNEO Z16F Series Product Specification (PS0220) available for down-
load at www.zilog.com.
Safeguards
The following precaution must be observed when working with the
devices described in this document.
Always use a grounding strap to prevent damage resulting from
electrostatic discharge (ESD).
Installation
For information on software installation and setup of the ZNEO Z16F
Series development kit, refer to ZNEO®Series of Microcontrollers
Development Kit Quick Start Guide (QS0057).
Caution:

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UM020205-0908 ZNEO Z16F Series Development Board
2
ZNEO Z16F Series Development
Board
Introduction
The ZNEO Z16F Series development board is a development and proto-
typing board for the ZNEO Z16F Series MCU. The board allows you to
evaluate the features of ZNEO Z16F Series MCU, and to develop an
application before building the hardware.
Figure 1. ZNEO Z16F Series Development Board

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UM020205-0908 ZNEO Z16F Series Development Board
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Features
The features of ZNEO Z16F Series of Microcontrollers include:
• ZNEO MCU (100-Lead LQFP package)
• 1 M x 16 External Flash memory
• 256 K x 16 External RAM
• 3 LEDs
• RS-232 interface
• On-Chip Debugger interface
• IrDA transceiver
• Electrical and mechanical compatibility with Zilog Modular Develop-
ment System (MDS) architecture
• One RESET pushbutton (S1)
• Two SPST switches (S2-STOP/RUN and S3-DIRECTION)
• 5 V DC power connector
• 20 MHz Ceramic Oscillator (Y1)
• Header for Analog-to-Digital Converter (ADC) input
• External interface connectors JP1, JP2, and JP4
• 2.7 V to 3.6 V operating voltage with 5 V tolerant inputs

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Development Kit Block Diagram
Figure 2 displays the block diagram of ZNEO Z16F Series development
kit.
Figure 2. ZNEO Z16F Series Development Kit Block Diagram
Z8F1285
(128KB FLASH,
4KB SRAM,
12 channel ADC,
3channelPWM)
FLASH
(1 M x 16, CS0)
SRAM
(256 K x 16, CS1)
IrDA
External GPIO
Bus (JP2)
External Peripheral
Bus (JP1)
20 MHz
XTAL
RS-232
External ADC
connector (JP3)
External Interface Address and Control bus
JP4
ZNEO
®
MCU
External Interface Data bus
GPIO

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User Manual
UM020205-0908 ZNEO Z16F Series Development Board
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ZNEO MEMORY LAYOUT
The ZNEO CPU has a unique memory architecture with a unified 24-bit
physical address space, which is partitioned into several distinct memory
areas. In terms of physical memory spaces, the overall address space
includes the following:
• Internal non-volatile memory
• Internal RAM
• Internal I/O memory and special function registers (SFRs)
• External memory and memory mapped peripherals
The internal memory listed above are always present in ZNEO devices,
while the external memory is optional. Every address space is defined as a
specific range of addresses located at a given place in the framework of
the unified 24-bit address space, and the address ranges of the different
spaces do not overlap. To promote code efficiency, the ZNEO CPU
supports shorter 16-bit addressing for the memory located in the address
ranges 00_0000H-00_7FFFH and FF_8000H-FF_FFFFH. Table 1 on
page 6 displays the physical layout of memory spaces available in the
ZNEO architecture.
The external Flash memory on the ZNEO development board has
a 16-bit bus. All Write operation to Flash Memory must be 16 bits
at even addresses only. Attempts to Write 1 byte will result in the
byte being replicated on both the upper and lower bytes of the
16-bit bus.
Note:

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Table 1. ZNEO Physical Memory Layout
Each internal memory space has a distinct purpose. Internal non-volatile
memory contains executable program code and constant data. ZNEO
CPU based devices have internal non-volatile memory starting at address
00_0000H. For example, a device equipped with 128 K of Flash has
internal non-volatile memory starting at address 00_0000H and ending at
address 01_FFFFH.
Internal RAM contains non-constant data and the stack. Executable
program code can also reside in internal RAM, if desired. ZNEO CPU
based devices have internal RAM ending at address FF_BFFFH, while the
beginning address (and hence the total extent of this space) is device
dependent. For example, a device equipped with 4 K of RAM has internal
RAM starting at address FF_B000H and ending at address FF_BFFFH.
Since internal RAM is accessed using 16-bit addressing, the lowest possi-
ble starting address for internal RAM on any device is FF_8000H.
ZNEO CPU based devices support 8 K of internal I/O memory located at
addresses FF_E000H–FF_FFFFH. This memory contains CPU control
registers and other SFRs, on-chip peripherals, and memory-mapped I/O
ports.
Memory Address Chip Selects
Internal I/O Memory & SFRs FF_FFFFH–FF_E000H
External Memory Mapped Peripherals
(optional) FF_DFFFH–FF_C800H CS3 – CS5
External Memory at CS2 (optional) FF_C7FFH–FF_C000H CS2
Internal RAM FF_BFFFH–FF_8000H
External Memory at CS2 (optional) F0_0000H CS2
External Memory at CS1 (optional) 80_0000H CS1
External Memory at CS0 (optional) 02_0000H CS0
Internal Non-Volatile Memory 01_FFFFH–00_0000H

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ZNEO CPU based devices also provide an external interface that allows
seamless connection to external memory and/or peripherals. External
memory can be non-volatile memory such as Flash, or RAM, or both.
External non-volatile memory is used to store program code or constant
data, while external RAM is available primarily for non-constant data.
The external interface supports multiple chip select signals (CSx), which
are asserted by the CPU when an access to external memory is requested.
These signals are used to access distinct ranges and devices in external
memory. The boundaries between memory ranges selected by the chip
select signals are at fixed addresses, and, in some cases, the ranges
covered by chip selects might overlap. For example, there might be some
addresses in the range of both the CS0 and CS1 signals. In this case, the
ZNEO CPU uses a chip select priority scheme. It asserts only a single
chip select with the highest priority among those that contain the
addresses to be accessed, with CS0 having the lowest priority and CS5 the
highest. Also, the chip selects can be individually enabled or disabled.
On-chip memory has greater priority over external memory. CS0 starts at
address 00_0000H, and CS1 starts at address 80_0000H. CS2 to CS5
start at addresses F0_0000H and beyond. For more information, refer to
ZNEO®CPU Core User Manual (UM0188) and the individual device
product specification.
MCU
The ZNEO Z16F Series Flash microcontrollers are based on Zilog’s
advanced ZNEO 16-bit CPU core. The ZNEO Z16F Series MCU family
of devices sets a new standard of performance and efficiency with a 24-bit
address bus and 16-bit data bus.
The ZNEO Z16F Series External Interface allows seamless connection to
external memory and peripherals. A 24-bit address bus and selectable
8-bit or 16-bit data bus allows parallel access up to 16 MB.

ZNEO®Z16F Series Development Kit
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8
The Development board contains circuitry to support and present all the
features of the ZNEO Z16F Series. The key features of ZNEO Z16F
Series include:
• 20 MHz ZNEO CPU Core
• Up to 128 KB internal Flash program memory with 16-bit access and
in-circuit programming capability
• Up to 4 KB internal RAM with 16-bit access
• External Interface allows seamless connection to external data
memory and peripherals with:
– 6 chip selects with Programmable Wait states
– 24-bit address bus supports up to 16 MB
– Selectable 8-bit or 16-bit data bus widths
– Programmable Chip Select signal polarity
– ISA-compatible mode
• Up to 12 channels 10-bit ADC
• Operational Amplifier
• Analog Comparator
• 4-channel DMA controller supports internal or external DMA
requests
• Two full-duplex 9-bit Universal Asynchronous Receiver/Transmitter
(UARTs) with support for Local Interconnect Network (LIN) and
Infrared Data Association (IrDA)
• Internal Precision Oscillator (IPO)
• I2C Master-Slave controller
• Enhanced Serial Peripheral Interface (ESPI) controller

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• 12-bit Pulse Width Modulator (PWM) module with three
complementary pairs or six independent PWM outputs with dead-
band generation and fault trip input
• Three standard 16-bit timers with capture, compare, and PWM capa-
bility
• Watchdog Timer (WDT) with internal RC oscillator
• Up to 76 I/O pins
• Up to 24 interrupts with programmable priority
• Single-pin on-chip debugger
• Power-on Reset (POR)
• Voltage Brownout Protection (VBO)
• 2.7 V to 3.6 V operating voltage with 5 V tolerant inputs
• 0 °C to +70 °C standard temperature, -40 °C to +105 °C extended
temperature, and -40 °C to +125 °C automotive operating ranges
For more information, refer to ZNEO®Z16F Series Product Specification
(PS0220) available for download at www.zilog.com.
UART with IrDA ENDEC
The ZNEO Z16F Series contains a fully-functional, high-performance
UART with Infrared Encoder/Decoder (ENDEC). The Infrared ENDEC is
integrated with an on-chip UART (component U13) allowing easy com-
munication between the ZNEO Z16F Series and IrDA transceivers. Infra-
red communication provides secure, reliable, low-cost, point-to-point
communication between PCs, PDAs, cell phones, printers, and other
infrared enabled devices.

ZNEO®Z16F Series Development Kit
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Switches and LEDs
The ZNEO development board contains the following LEDs and
switches:
• Green LED D1, which when illuminated indicates the presence of
3.3 V DC on the board’s VCC_3 V power bus
• Red LED D2, connected to chip port PA0_T0IN
• Yellow LED D3, connected to the chip port PA1_T0OUT
• Green LED D4, connected to the chip port PA2_DE0
• RESET switch S1, connected to the chip port RESET
• SPST switch S2, connected to the chip port PA7_SDA
• SPST switch S3, connected to the chip port PC0_T1IN
Potentiometer R10 is reserved for future use.
Jumper Settings
Table 2 provides information on the shunt status, functions, and default
settings of jumpers on the ZNEO Z16F Series development board.
Table 2. ZNEO Jumper Settings
Jumper Status Function Default
J1 OUT (not
installed) Enables ZNEO MCU access to external 16-bit memory bus on development board. X
J1 IN Disables 16-bit external memory bus and makes ZNEO MCU analog ports available through connector JP4. Refer to
schematic for JP4 pinouts.
J2* OUT RS-232 interface enabled. X
J2 IN RS-232 interface disabled.
J3* OUT IrDA interface enabled.

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External Interface Headers JP1, JP2, and JP4
External interface headers JP1, JP2, and JP4 are provided in Schematics
on page 12.
J3 IN IrDA interface
disabled. X
J6 OUT 8-bit MDS interface
disabled. X
J6 IN 8-bit MDS interface
enabled.
J7 OUT External Flash Write Protect disabled. X
J7 IN External Flash Write Protect enabled.
Note: * These jumpers must not be OUT at the same time.
Table 2. ZNEO Jumper Settings (Continued)
Jumper Status Function Default

UM020205-0908 Schematics
ZNEO®Z16F Series Development Kit
User Manual
12
Schematics
Figure 3 through Figure 6 on page 15 display the schematics for the ZNEO Z16F Series Development Kit.
Figure 3. ZNEO Z16F Series MCU Development Kit
PA0
PA1
PA2
PA7
PA3
PA4
PA5
-DIS_232
-DIS_IrDA
RXD1
nCTS1
PA6
-RESET
PA6
ANA_M[2:0]
PA3
PK[7:0]
-DIS_IrDA
ANA[11:10]
A[23:0]
-DIS_232
RXD1
TXD1
PC[7:0]
-RESET
nCTS1
PA7
ANA[7:0]
D[15:0]
PA5
PA4
PA2
TXD1
Rev C: Swapped ANA 8 and ANA 9 on MCU page and MDS interface page
POWER&COMMUNICATIONS
POWER&COMMUNICATIONS
PA4_RXD0
PA1_T0OUT
PA0_T0IN
-DIS_IRDA
PC0_T1IN
-DIS_232
PA2_DE0
PA3_CTS0
PA5_TXD0
PA7_SDA
-RESET
TXD1
RXD1
A1
FAB
A1
FAB
MCU
MCU
PK[7:0]
D[15:0]
TXD1
A[23:0]
RXD1
ANA_M[2:0]
ANA[11:10]
-WR
nCTS1
PC[7:0]
PWML1
PWML2
ANA[7:0]
PWMH1
ANA_8
DE1
PWMH2
ANA_9
-RD
-MC_EN
PA5
PA7
PA0
PA1
PA2
PA3
PA4
-XM_EN
PA6
VREF
PC0_T1IN
-RESET
MDS INTERFACE
MDS_INTERFACE
-DIS_IrDA
-DIS_232
PK[7:0]
D[15:0]
A[23:0]
-WR
PC[7:0]
-RD
ANA_M[2:0]
ANA[11:10]
ANA[7:0]
PWML1
PWMH1
PWML2
PWMH2
PA2
PA3
PA4
PA5
PA6
PA7
TXD1
RXD1
ANA8
ANA9
nCTS1
VREF
-RESET
-MC_EN
-XM_EN
DE1
Title
Size
Document Number
Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
14
Thursday, March 02, 2006
Title
Size Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
14
Thursday, March 02, 2006
Title
Size Rev
Date: Sheet of
96C0999-001 C
B
14
Thursday, March 02, 2006
TOP
Z16F2811

UM020205-0908 Schematics
ZNEO®Z16F Series Development Kit
User Manual
13
Figure 4. ZNEO Z16F Series MCU Development Kit
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PD0_PWMH1_ADR20
PJ4_DATA12
PK4_nCS2
PK1_nBLEN
GND
PJ2_DATA10
PD3_DE1_ADR16
PJ7_DATA15
PF5_ADR5
PF0_ADR0
PK7_nCS5
GND
PA2_DE0
PA0_T0IN
GND
PB1__ANA1_T0IN1
PD1_PWML1_ADR21
PJ1_DATA9
PK2_nCS0
PA5_TXD0
PC5_MISO
VCC_33v
PE3_DATA3
PB0__ANA0_T0IN0
PF1_ADR1
VCC_33v
PK3_nCS1
PE0_DATA0
PA1_T0OUT
PB4__ANA4
PC4_MOSI
PJ0_DATA8
-RESET
PA4_RXD0 PF7_ADR7
PH1_ANA9_nRD
PF6_ADR6
PE4_DATA4
PB5__ANA5
PF2_ADR2
PH2_ANA10
PE1_DATA1
VCC_33v
PH0_ANA8_nWR
PD5_TXD1_ADR19
PJ6_DATA14
PB3__ANA3_OPOUT
VCC_33V
PF3_ADR3
GND VCC_33v
PJ3_DATA11
PC2_nSS
GND
PK5_nCS3
PH3_ANA11_CPINP_nWAIT
PD4_RXD1_ADR18
PJ5_DATA13
PK0_nBHEN
GND
PE2_DATA2
PB6_ANA6_OPINP
VCC_33v
PF4_ADR4
PK6_nCS4
PB2__ANA2_T0IN2
VCC_33v
PD2_PWMH2_ADR22
PA3_nCTS0
PB7_ANA7_OPINN
PC1_TOUT PC1
PC3_SCK PC3
PC0_T1IN
PA6_SCL
PA7_SDA
PC4_MOSI PC4
PA4_RXD0
PA3_nCTS0
PA5_TXD0
PC5_MISO PC5
PA1_T0OUT
PC2_nSS PC2
PK5_nCS3 PK5
PK7_nCS5 PK7
PK0_nBHEN PK0
PK6_nCS4 PK6
PK4_nCS2 PK4
PK2_nCS0 PK2
PK1_nBLEN PK1
PH3_ANA11_CPINP_nWAIT ANA11
PH2_ANA10 ANA10
PK3_nCS1 PK3
PF4_ADR4 A4
PJ2_DATA10 D10
PF2_ADR2 A2
PJ3_DATA11 D11
PE5_DATA5 D5
PJ0_DATA8 D8
PE1_DATA1 D1
PJ5_DATA13 D13
PG0_ADR8 A8
PE7_DATA7 D7
PE4_DATA4 D4
PG7_ADR15 A15
PF3_ADR3 A3
PF7_ADR7 A7
PE2_DATA2 D2
PF5_ADR5 A5
PJ6_DATA14 D14
PJ4_DATA12 D12
PG3_ADR11 A11
PE0_DATA0 D0
PJ1_DATA9 D9
PF6_ADR6 A6
PG4_ADR12 A12
PG5_ADR13 A13
PE3_DATA3 D3
PG1_ADR9 A9
PG6_ADR14 A14
PE6_DATA6 D6
PJ7_DATA15 D15
PG2_ADR10 A10
PF1_ADR1 A1
PF0_ADR0 A0
A20
A21
A22
A16
A18
A19
A17
A23
PD0_PWMH1_ADR20
PD3_DE1_ADR16
PD4_RXD1_ADR18
PD7_PWML2_ADR23
PD2_PWMH2_ADR22
PD6_nCTS1_ADR17
PD1_PWML1_ADR21
PD5_TXD1_ADR19
PD5_TXD1_ADR19
PD3_DE1_ADR16
PD2_PWMH2_ADR22
PD1_PWML1_ADR21
PD7_PWML2_ADR23
PD6_nCTS1_ADR17
PD0_PWMH1_ADR20
PD4_RXD1_ADR18
DE1
nCTS1
PWML1
PWMH2
TXD1
PWMH1
PWML2
RXD1
PC6_T2IN_PWMH0 PC6
PC7_T2OUT_PWML0 PC7
PH1_ANA9_nRD
PH0_ANA8_nWR
ANA_9
ANA_8
OPINP_CINN
VREF
AGND
ANA_5
CINP
OPOUT
ANA_M2
ANA_M1
ANA_M0
-MC_EN
Vref
AGND
ANA6
ANA11
ANA7
ANA1
ANA0
ANA2
PA0_T0IN
ANA_M1
ANA_M2
ANA_M0
VCC_33V
PB3__ANA3_OPOUT ANA3
PB2__ANA2_T0IN2 ANA2
PB1__ANA1_T0IN1 ANA1
PB6_ANA6_OPINP ANA6
PB4__ANA4 ANA4
PB5__ANA5 ANA5
ANA3
PB0__ANA0_T0IN0 ANA0
PB7_ANA7_OPINN ANA7
PA2_DE0
AVCC
-MC_EN
VCC_33V
GND
DBG
VCC_33V
-RESET VCC_33V
VCC_33V
PC1_TOUT
PG6_ADR14
PD6_nCTS1_ADR17
PC0_T1IN
VCC_33v
PE5_DATA5
PG2_ADR10
PE7_DATA7
PG3_ADR11
DBG
GND
PC3_SCK
VCC_33v
PG0_ADR8
PE6_DATA6
PG5_ADR13
PG1_ADR9
PA6_SCL
PA7_SDA
PD7_PWML2_ADR23
PC6_T2IN_PWMH0
PG4_ADR12
PC7_T2OUT_PWML0
PG7_ADR15
GND
OPINN
PC0
ANA_5 ANA5
D[15:0]
A[23:0]
-WR
-RD
ANA[11:10]
ANA_M[2:0]
ANA_9
ANA_8
ANA[7:0]
PC[7:0]
PK[7:0]
-MC_EN
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PWMH1
PWML1
PWMH2
PWML2
DE1
TXD1
RXD1
nCTS1
-XM_EN
VREF
-RESET
PC0_T1IN
VCC_33V
VCC_33V
Title
Size Document Number Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
24
Monday, May 08, 2006
Title
Size Document Number Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
24
Monday, May 08, 2006
Title
Size Document Number Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
24
Monday, May 08, 2006
DBG
INTERFACE
XM_OUT/MC_IN
MCU
C3
0.01uF
C3
0.01uF
C6
22pF
C6
22pF
R6
10K
R6
10K
U3
SN74CBTLV3861
U3
SN74CBTLV3861
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
A9
10
A10
11
B1
22
B2
21
B3
20
B4
19
B5
18
B6
17
B7
16
B8
15
B9
14
B10
13
NC
1
VCC
24
GND
12
OE
23
C4 12pF C4 12pF
C22
0.01uF
C22
0.01uF
R5
49.9K
R5
49.9K
C9
0.01uF
C9
0.01uF
C21
0.01uF
C21
0.01uF
C20
0.01uF
C20
0.01uF
C2 0.1uF C2 0.1uF
U2
Z16F2811AL20SG
U2
PA0/T0IN/OUT/DMA0REQ
1
PD2/PWMH2/ADR22
2
PC2/SS/CS4
3
PF6/ADR6
4
RESET
5
VDD
6
PF5/ADR5
7
PF4/ADR4
8
PF3/ADR3
9
PE3/DATA3
11
PE4/DATA4
10
GND
12
PE2/DATA2
13
PE1/DATA1
14
PE0/DATA0
15
GND
16
PF2/ADR2
17
PF1/ADR1
18
PF0/ADR0
19
VDD
20
PD1/PWML1/ADR21
21
PD0/PWMH1/ADR20
22
EXTAL
23
XTAL
24
PA1/T0OUT/DMA0CK 95
PA6/SCL/CS3
75
PA7/SDA/CS4
74
GND
25
AGND
45
GND
51
AVDD
31
PH0/ANA8/WR
32
PH1/ANA9/RD
33
PB0/ANA0/T0IN0
34
PB1/ANA1/T0IN1
35
PB4/ANA4
36
PB5/ANA5
37
PB6/ANA6/OPINP/CINN
38
PB7/ANA7/OPINN
39
PB3/ANA3/OPOUT
40
PB2/ANA2/T0IN2
41
PH2/ANA10/CS0
42
PH3/ANA11/CPINP/WAIT
43
VREF
44
PC0/T1IN/OUT/DMA1REQ/CINN
52
PC1/T1OUT/DMA1ACK/COUT
53
DBG
54
PC6/T2IN/OUT/PWMH0 55
PC7/T2OUT/PWML0
56
PG7/ADR15
57
VDD
58
PG6/ADR14
59
PG5/ADR13
60
PG4/ADR12
61
PG3/ADR11
62
PE7/DATA7
64
PE6/DATA6
65
PE5/DATA5
66
PG2/ADR10
67
PG1/ADR9
68
PG0/ADR8
70
PD7/PWML2/ADR23
71
PC3/SCK/DMA2REQ
72
PD6/CTS1/ADR17
73
PA5/TXD0/CS2 76
PA4/RXD0/CS1 77
PC4/MOSI/DMA2ACK 85
PD5/TXD1/ADR19 86
PD4/RXD1/ADR18 87
PD3/DE1/ADR1688
PC5/MISO/CS589
PF7/ADR7 90
PA3/CTS0/FAULT0 93
PA2/DE0/FAULTY 94
GND 92
VDD 91
GND 78
VDD 79
GND
69
VDD
63
PK3/CS1
26
PK2/CS0
27
PK1/BLEN
28
PK0/BHEN
29
VDD
30
PK4/CS2
46
PK5/CS3
47
PK6/CS4
48
PK7/CS5
49
VDD
50
PJ7/DATA15 80 PJ6/DATA14 81 PJ5/DATA13 82 PJ4/DATA12 83
GND 84
PJ3/DATA11 97
VDD 96
PJ2/DATA10 98
PJ1/DATA9 99 PJ0/DATA8 100
R11
1K
R11
1K
R4
10K
R4
10K
P3
HDR/PIN 2x3
P3
HDR/PIN 2x3
1 2
3 4
5 6
C18
0.01uF
C18
0.01uF
C19
0.01uF
C19
0.01uF
J1
HDR/PIN 1x2
J1
HDR/PIN 1x2
1
2
R35
10K
R35
10K
C8
0.01uF
C8
0.01uF
+
C11 10uF
+
C11 10uF
C23
1000pF
C23
1000pF
C16
0.01uF
C16
0.01uF
U4A
SN74LVC04
U4A
SN74LVC04
1 2
14
7
C17
0.01uF
C17
0.01uF
C15
0.01uF
C15
0.01uF
R9
10K
R9
10K
R8
0 OHm
R8
0 OHm
C14
0.01uF
C14
0.01uF
C5
22pF
C5
22pF
U5
SN74CBTLV3861
U5
SN74CBTLV3861
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
A9
10
A10
11
B1
22
B2
21
B3
20
B4
19
B5
18
B6
17
B7
16
B8
15
B9
14
B10
13
NC
1
VCC
24
GND
12
OE
23
C12
0.01uF
C12
0.01uF
C1 100pF C1 100pF
C13
0.01uF
C13
0.01uF
U1
SN74CBTLV3861
U1
SN74CBTLV3861
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
A9
10
A10
11
B1
22
B2
21
B3
20
B4
19
B5
18
B6
17
B7
16
B8
15
B9
14
B10
13
NC
1
VCC
24
GND
12
OE
23
R1
10K
R1
10K
R7
0 OHm
R7
0 OHm
Y1
20 MHz
Y1
20 MHz
1 3
2
R3 12.4K R3 12.4K
R2 7.8K R2 7.8K
C7
0.01uF
C7
0.01uF
C10
0.01uF
C10
0.01uF
R10
5K
R10
5K
13
2
Z16F2811

UM020205-0908 Schematics
ZNEO®Z16F Series Development Kit
User Manual
14
Figure 5. ZNEO Z16F Series MCU Development Kit
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ANA7
GND
PD5_TXD1
GND
A21
-MREQ -BHEN
PC1_TOUT
A3
VREF
-F91_WE
A20
GND
ANA3
D1
A18
PC3_SCK
-CS0
A1
GND
PC4_MOSI
A8
A5
D0
-BUSACK -CS4
GND
ANA5
A16
PA7_SDA
-DIS_FLASH
PD3
PC6_T2IN_PWMH0
A23
A13
GND
VCC_33V
A4
A19
A22
D6
PC7_T2OUT_PWML0
ANA4
D4
GND
PWML2
A0
PA2
-CS1
A9
PC2_nSS
A15
GND
D7
-INSTRD -CS3
VCC_33V
D3
ANA_M0
PA6_SCL
PD6_nCTS1
PA4_RXD0
PC0_T1IN
ANA_M1
A14
A10
D2
PC5_MISO
PA3_CTS0
-IOREQ -BLEN
VCC_33V
ANA_M2
A11
A17
PD4_RXD1
D5
-RESET
A7
VCC_33V
VCC_33V
GND
GND
ANA6
VCC_33V
A2
PA5_TXD0
-BUSREQ -CS5
GND
A12
-CS2
D8
D10
-TRSTN D12
A6
D9
D11
D13
D14
D15
D13
D9
D2
D4
D3
D6
D0
D12
D5
D11
D7
D14
D10
D15
D1
D8
-BHEN
-BLEN
-RD
-WR
-CS1
-RESET
ANA_M1
ANA_M0
ANA_M2
PC6_T2IN_PWMH0 PC6
PC5
PC4
PC3
PC2
PC7_T2OUT_PWML0 PC7
PC0_T1INPC0
PC1_TOUT PC1
-WR
-RD
ANA10
ANA2
ANA3
ANA7
ANA6
ANA5
ANA4
ANA1
ANA0
ANA8
PB5_ANA5 ANA5
PB7_ANA7 ANA7
PB3_ANA3 ANA3
PB0_ANA0 ANA0
PB6_ANA6 ANA6
PB2_ANA2 ANA2
PH0_ANA8 ANA8
PB1_ANA1 ANA1
PB4_ANA4 ANA4
PG3_ADR11 A11
PF0_ADR0 A0
PF7_ADR7 A7
A23
PF2_ADR2 A2
PG6_ADR14 A14
D5
PG1_ADR9 A9
D15
D6
-RD
PG5_ADR13 A13
A18
PF1_ADR1 A1
-FLASH_EN
-WR
D14
PG4_ADR12 A12
PG2_ADR10 A10
PF6_ADR6 A6
D10
D3
D1
A16
PF5_ADR5 A5
D12
D7
D0
A17
A20
-RESET
D4
PG0_ADR8 A8
A19
A21
PF3_ADR3 A3
D8
PG7_ADR15 A15
D13
D9
D11
PF4_ADR4 A4
A22
D2
-DIS_FLASH
-CS0 PK2
-CS5 PK7
-CS4 PK6
-BHEN PK0
-CS3 PK5
-CS0
-CS1 PK3
-CS2 PK4
-BLEN PK1
-FLASH_EN
PC2_nSS
PC5_MISO
PC4_MOSI
PC3_SCK
PH1_ANA9 ANA9
PJ6_DATA14 D14
PE7_DATA7 D7
PE6_DATA6 D6
PE2_DATA2 D2
PE0_DATA0 D0
PJ3_DATA11 D11
PJ0_DATA8 D8
PE4_DATA4 D4
PJ5_DATA13 D13
PE1_DATA1 D1
PJ4_DATA12 D12
PJ1_DATA9 D9
PE5_DATA5 D5
PJ7_DATA15 D15
PJ2_DATA10 D10
PE3_DATA3 D3
PJ0
PJ1 PJ2
PJ3
PH3_ANA11 WAIT
-FLASH_PR
-FLASH_PR
-CS3
PH2_ANA10 ANA10
VCC_33V
PC4_MOSI
PC5_MISO
ANA9
PC2_nSS
ANA8
ANA11
ANA9
PC3_SCK
PH3_ANA11 ANA11
ANA11
VREF
PJ0_DATA8
PJ1_DATA9
PJ2_DATA10
PJ3_DATA11
PJ0
PJ1
PJ2
PJ3
-F91_WE
GNDGND
A11
A3
A14
A1
A15
A18
A6
A5
A17
A4
A9
A10
A13
A16
A2
A8
A12
A19
A7
A20
A9
A11
A10
A2
A16
A8
A5
A17
A13
A15
A14
A6
A3
A7
A1
A12
A4
A18
-F91_WE
-DIS_232
-DIS_IrDA
ANA[7:0]
ANA_M[2:0]
PK[7:0]
PC[7:0]
D[15:0]
-WR
A[23:0]
-RD
PA7
PA3
PA2
PA4 PA5
PA6
PWMH2
ANA8
ANA9
ANA[11:10]
VREF
PWML2
PWMH1
PWML1
TXD1
RXD1
nCTS1
-RESET
-MC_EN
-XM_EN
DE1
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
Title
Size
Document Number
Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
34
Monday, May 08, 2006
Title
Size Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
34
Monday, May 08, 2006
Title
Size Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
34
Monday, May 08, 2006
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
8BIT_MDS_ENABLE
FLASH_WRITE
PROTECT
MEMORY AND MDS INTERFACE
FIX for REV C
C33
0.1uF
C33
0.1uF
C40
0.1uF
C40
0.1uF
JP4
HDR/PIN 2x13
JP4
HDR/PIN 2x13
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
C25
0.01uF
C25
0.01uF
C35
0.1uF
C35
0.1uF
R28
10K
R28
10K
U8
SN74CBTLV3384
U8
SN74CBTLV3384
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
1OE
1
2OE
13
VCC
24
GND
12
C38
0.1uF
C38
0.1uF
C31
0.1uF
C31
0.1uF
C26
0.01uF
C26
0.01uF
U7B
SN74LVC00
U7B
SN74LVC00
4
5
6
U7A
SN74LVC00
U7A
SN74LVC00
1
2
3
147
C27
0.01uF
C27
0.01uF
C34
0.1uF
C34
0.1uF
C41
0.1uF
C41
0.1uF
U9
SN74CBTLV3384
U9
SN74CBTLV3384
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
1OE
1
2OE
13
VCC
24
GND
12
R29
0 OHm
R29
0 OHm
R30
10K
R30
10K
J7
HDR/PIN 1x2
J7
HDR/PIN 1x2
1
2
R31
0 OHm
R31
0 OHm
JP1
HDR/PIN 2x30
JP1
HDR/PIN 2x30
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
C36
0.1uF
C36
0.1uF
C29
0.01uF
C29
0.01uF
C32
0.1uF
C32
0.1uF
C39
0.1uF
C39
0.1uF
C28
0.01uF
C28
0.01uF
R34
10K
R34
10K
C24
0.01uF
C24
0.01uF
R32
0 OHm
R32
0 OHm
R33
10K
R33
10K
U6
AT49BV162AT
U6
AT49BV162AT
A0
25
A1
24
A2
23
A3
22
A4
21
A5
20
A6
19
A7
18
A8
8
A9
7
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
48
A17
17
A18
16
A19
9
CE
26
OE
28
WE
11
D0
29
D1
31
D2
33
D3
35
D4
38
D5
40
D6
42
D7
44
D8
30
D9
32
D10
34
D11
36
D12
39
D13
41
D14
43
D15/A-1
45
RESET
12
RY_BY
15
BYTE
47
GND
27
GND
46
VCC
37
NC
10
VPP
14
NC
13
U10
TC55VCM216
U10
TC55VCM216
GND
27
VCC
37
A0
25
A1
24
A2
23
A3
22
A4
21
A5
20
A6
19
A7
18
A8
8
A9
7
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
48
I/O0
29
I/O1
31
I/O2
33
I/O3
35
I/O4
38
I/O5
40
I/O6
42
I/O7
44
CE1
26
CE2
12
OE
28
WE
11
NC
16
A17
17
UBEN
14
LBEN
15
NC
47
NC
10
GND
46
I/O11
36
I/O12
39
I/O13
41
I/O14
43
I/O15
45
NC
9
OP
13
I/O8
30
I/O9
32
I/O10
34
J6
HDR/PIN 1x2
J6
HDR/PIN 1x2
1 2
JP2
HDR/PIN 2x30
JP2
HDR/PIN 2x30
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
C30
0.1uF
C30
0.1uF
C37
0.1uF
C37
0.1uF
Z16F2811

UM020205-0908 Schematics
ZNEO®Z16F Series Development Kit
User Manual
15
Figure 6. ZNEO Z16F Series MCU Development Kit
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5V VCC_5V
GND
IRDA_SD
PA3_CTS0
PA4_RXD0
GND
PA5_TXD0
GND
GND
GND
RXD0
CTS0
TXD0
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
VCC_33V
-DIS_232
PA5_TXD0
PA3_CTS0
PA4_RXD0
-DIS_IRDA
PA2_DE0
PA1_T0OUT
PA0_T0IN
-RESET
PA7_SDA
PC0_T1IN
RXD1
TXD1
VCC_33V
VCC_33V
VCC_5V
VCC_33V
Title
Size
Document Number
Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
44
Thursday, March 02, 2006
Title
Size Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
44
Thursday, March 02, 2006
Title
Size Rev
Date: Sheet of
96C0999-001 C
Z8F1285 Evaluation Module. Schematic.
B
44
Thursday, March 02, 2006
DIS RS232
USER
DIS IRDA
-RESET
CONSOLE
3.3 OK
VCC 3.3V
STOP/RUN
DIRECTION
POWER & LOCAL INTERFACES
GND
R21 2R2R21 2R2
D4
GREEN
D4
GREEN
21
C42
0.1uF
C42
0.1uF
R26
10K
R26
10K
C50
0.1uF
C50
0.1uF
U4B
SN74LVC04
U4B
SN74LVC04
3 4
147
P1
CON DC
P1
CON DC
2
3
1
R15
10K
R15
10K
U4E
SN74LVC04
U4E
SN74LVC04
11 10
147
TP1TP1
1 2 3
S3
EG1218
S3
EG1218
D1
GREEN
D1
GREEN
21
P2
DB9 Female
P2
DB9 Female
5
9
4
8
3
7
2
6
1
+
C49
10uF
+
C49
10uF
C48
0.1uF
C48
0.1uF
U7C
SN74LVC00
U7C
SN74LVC00
9
10
8
U4D
SN74LVC04
U4D
SN74LVC04
9 8
147
U7D
SN74LVC00
U7D
SN74LVC00
12
13
11
R17
100
R17
100
C46
0.1uF
C46
0.1uF
U4C
SN74LVC04
U4C
SN74LVC04
5 6
147
D3
YELL
D3
YELL
21
R22
10K
R22
10K
C45
0.1uF
C45
0.1uF
U4F
SN74LVC04
U4F
SN74LVC04
13 12
147
R27
100
R27
100
R13
10K
R13
10K
TP2TP2
1 2 3
C51
0.33uF
C51
0.33uF
R24
10K
R24
10K
R23
100
R23
100
R19 68R R19 68R
R14
10K
R14
10K
C44
0.1uF
C44
0.1uF
R16
10K
R16
10K
J3
HDR/PIN 1x2
J3
HDR/PIN 1x2
1
2
S2
EG1218
S2
EG1218
+
C43
10uF
+
C43
10uF
R12
100 OHm
R12
100 OHm
R25
100
R25
100
C47
0.1uF
C47
0.1uF
R18
10K
R18
10K
D2
RED
D2
RED
21
U12
SPX2815AU-3.3
U12
SPX2815AU-3.3
VI
3
GND
1
VO
2
U13
ZHX1810
U13
ZHX1810
TXD
2
SD
4
RXD
3
LEDA
1
VCC
5
GND
6
T
0
J2
HDR/PIN 1x2
J2
HDR/PIN 1x2
1
2
U11
SP3222EBCA
U11
SP3222EBCA
EN
1
C1+
2
C1-
4
C2+
5
C2-
6
T1IN
13
T2IN
12
R1OUT
15
R2OUT
10
V+
3
V-
7
T1OUT
17
T2OUT
8
R1IN
16
R2IN
9
SHDN
20
VCC 19
GND
18
NC
11
NC
14
R20
100
R20
100
S1
SW PB NO
S1
SW PB NO
1 2
Z16F2811

ZNEO®Z16F Series Development Kit
User Manual
UM020205-0908 Customer Support
16
Customer Support
For answers to technical questions about the product, documentation, or
any other issues with Zilog’s offerings, please visit Zilog’s Knowledge
Base at http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems,
please visit Zilog’s Technical Support at http://support.zilog.com.