ADLINK Technology cExpress-AL User manual

Leading EDGE COMPUTING
cExpress-AL
User’s Manual
COM Express Compact Size Type 6 Module with
Intel® Atom™, Pentium®, Celeron® SoC
Manual Rev.: 1.0
Revision Date: December 4, 2017
Part Number: 50-1J068-1000

ii Preface
Preface
Copyright
Copyright 2017 ADLINK Technology, Inc. This document contains proprietary information protected by copyright.
All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in
any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and
function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer
be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use
the product or documentation, even if advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with
the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to
ensure that our products, manufacturing processes, components, and raw materials have as little impact on the
environment as possible. When products are at their end of life, our customers are encouraged to dispose of them
in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or
registered trademarks of their respective companies.
Revision History
Revision Description Date By
1.0 Initial 2017-12-04 JC

cExpress-AL
Preface iii
Table of Contents
Preface................................................................................................................................ii
List of Figures ....................................................................................................................v
List of Tables.....................................................................................................................vi
1. Introduction................................................................................................................1
2. Specifications............................................................................................................3
2.1. Core System ...............................................................................................................3
2.2. Expansion Busses ......................................................................................................3
2.3. Video...........................................................................................................................4
2.4. Audio...........................................................................................................................4
2.5. LAN.............................................................................................................................4
2.6. Multi I/O and Storage..................................................................................................4
2.7. Serial I/O.....................................................................................................................5
2.8. SEMA Board Controller ..............................................................................................5
2.9. Debug .........................................................................................................................5
2.10. Trusted Platform Module (TPM) ..............................................................................5
2.11. Power Specifications ...............................................................................................6
2.12. Operating Temperatures .........................................................................................6
2.13. Environmental .........................................................................................................6
2.14. Specification Compliance ........................................................................................6
2.15. Operating Systems..................................................................................................6
2.16. Functional Diagram .................................................................................................7
2.17. Mechanical Drawing ................................................................................................8
3. Pinouts and Signal Descriptions..............................................................................9
3.1. AB/CD Pin Definitions.................................................................................................9
3.2. Signal Description Terminology ................................................................................12
3.3. AB Signal Descriptions .............................................................................................13
3.4. CD Signal Descriptions.............................................................................................23
4. Module Interfaces....................................................................................................31
4.1. Connector, Switch and LED Locations .....................................................................31
4.2. 40-pin Debug Connector...........................................................................................32
4.3. Status LEDs..............................................................................................................33
4.4. MIPI60 Debug Header ..............................................................................................34
4.5. Fan Connector ..........................................................................................................35
4.6. BIOS Setup Defaults Reset Button...........................................................................36

iv Preface
4.7. Switch Settings .........................................................................................................37
5. Smart Embedded Management Agent (SEMA) .....................................................39
5.1. Board Specific SEMA Functions...............................................................................40
6. System Resources ..................................................................................................43
6.1. System Memory Map................................................................................................43
6.2. I/O Map .....................................................................................................................43
6.3. Interrupt Request (IRQ) Lines...................................................................................45
6.4. PCI Configuration Space Map ..................................................................................47
6.5. PCI Interrupt Routing Map ........................................................................................49
6.6. SMBus Address Table ..............................................................................................50
7. BIOS Setup...............................................................................................................51
7.1. Menu Structure .........................................................................................................51
7.2. Main ..........................................................................................................................52
7.3. Advanced..................................................................................................................54
7.4. Chipset......................................................................................................................69
7.5. Security Menu...........................................................................................................80
7.6. Boot Menu ................................................................................................................80
7.7. Save & Exit Menu .....................................................................................................81
8. BIOS Checkpoints, Beep Codes.............................................................................83
8.1. Status Code Ranges.................................................................................................84
8.2. Standard Status Codes.............................................................................................84
8.3. OEM-Reserved Checkpoint Ranges......................................................................... 91
9. Mechanical Information...........................................................................................93
9.1. Board-to-Board Connectors......................................................................................93
9.2. Thermal Solution.......................................................................................................94
9.3. Mounting Methods ....................................................................................................97
9.4. Standoff Types..........................................................................................................98
Safety Instructions...........................................................................................................99
Getting Service...............................................................................................................100

cExpress-AL
Preface v
List of Figures
Figure 1: cExpress-AL Functional Block Diagram....................................................................................7
Figure 2: cExpress-AL Mechanical Drawing ............................................................................................8
Figure 3: cExpress-AL Connector, Switch and LED Locations ............................................................. 31
Figure 4: cExpress-AL and the DB40 Debug Module ........................................................................... 31
Figure 5: cExpress-AL Switch Locations............................................................................................... 37
Figure 6: COM Express Mounting Methods ..........................................................................................97
Figure 7: COM Express Standoff Types................................................................................................ 98

vi Preface
List of Tables
Table 1: cExpress-AL AB/CD Pin Definitions ...........................................................................................9
Table 2: 40-pin Debug Connector Pin Definition ................................................................................... 32
Table 3: cExpress-AL LED Descriptions ............................................................................................... 33
Table 4: MIPI60 Debug Header Pin Definition ...................................................................................... 34
Table 5: Fan Connector Pin Definition .................................................................................................. 35
Table 6: BIOS Select and Mode Configuration Switch Settings............................................................ 37
Table 7: SEMA Onboard Voltage Monitor ............................................................................................. 40
Table 8: SEMA BMC Status .................................................................................................................. 40
Table 9: SEMA Exception Codes .......................................................................................................... 41
Table 10: SEMA BMC Flags.................................................................................................................. 41

cExpress-AL
Introduction 1
1. Introduction
The cExpress-AL is a COM Express COM.0 R3.0 Type 6 module supporting the Intel® Atom™ processor, Intel®
Pentium® processor and Intel® Celeron® processor system-on-chip (SoC). The cExpress-AL is specifically
designed for customers who need optimized processing and graphics performance with low power consumption in
a long product life solution.
The Intel® Atom™ processor, Intel® Pentium® processor and Intel® Celeron® processor and support non-ECC
type DDR3L dual-channel memory at 1600/1867 MHz to provide excellent overall performance. Integrated Intel®
Gen9 LP Graphics includes features such as OpenGL 4.3, DirectX 12, OpenCL 2.0; and support for H.265/HEVC,
H.264, MPEG2, VC1, VP9, MVC, JPEG/MJPEG hardware decode. Up to three independent displays are available
from DDI ports supporting HDMI/DVI/DisplayPort, optional VGA, single/dual-channel 18/24-bit LVDS and optional
eDP. The cExpress-AL is specifically designed for customers with balanced performance/power consumption
requirements who want to outsource the custom core logic of their systems for reduced development time.
The cExpress-AL has dual stacked SODIMM sockets for up to 8 GB non-ECC type DDR3L memory. Featured IO
include a single Gigabit Ethernet port (IEEE 1588 support), USB 3.0 ports and USB 2.0 ports, SATA 6 Gb/s ports,
and up to 5 PCIe x1 lanes. In addition, SD signals are muxed with GPIO. Support is provided for SMBus and I2C.
The module is equipped with SPI AMI EFI BIOS, supporting embedded features such as remote console, CMOS
backup, hardware monitor, and watchdog timer. An optional eMMC 5.0 (8/16/32 GB) is supported.

2 Introduction
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cExpress-AL
Specifications 3
2. Specifications
2.1. Core System
CPU Dual or quad-core Intel® Atom™, Pentium® or Celeron® Processor SoC
•AtomTM E3950 1.6/2.0GHz (Turbo), 400-650MHz (graphics), 12W (4C/1866)
•AtomTM E3940 1.6/1.8GHz (Turbo), 400-600MHz (graphics), 9W (4C/1866)
•AtomTM E3930 1.3/1.8GHz (Turbo), 400-550MHz (graphics), 6W (2C/1866)
•Pentium® N4200 1.1/2.5GHz (Turbo), 200-750MHz (graphics), 6W (4C/1866)
•Celeron® N3350 1.1/2.4GHz (Turbo), 200-650MHz (graphics), 6W (2C/1866)
Supports: Dual or quad Out-of-Order Execution (OOE) processor cores, Intel® VT-x,
Intel® VT-d, Intel® SSE4.1 and SSE4.2, Intel® 64 architecture, Intel® Turbo Boost
Technology 2.0, Intel AES-NI, Intel® TXT, PCLMULQDQ instruction DRNG
Notes: Availability of features may vary between processor SKUs and operating systems.
Only Atom™ SKUs can support extreme temperature operating range
Cache 2MB for all SKUs
Memory Dual channel non-ECC 1600/1867 MHz DDR3L memory up to 8GB in dual stacked
SODIMM sockets (lower slot must be populated)
BIOS AMI EFI with CMOS backup in 16MB SPI BIOS
2.2. Expansion Busses
PCI Express •4 PCIe x1 (AB): ports 0/1/2/3 (direct from SoC) configurable to x1, x2, x4
•A 5th PCIe x1 (port 4) is supported by build option with a PCIe bridge IC (ports 2/3/4
from PCIe bridge IC support x1 only, see 2.16 Functional Diagram below).
Other •LPC bus
•SMBus (system)
•I2C (user)

4 Specifications
2.3. Video
Integrated on Processor Intel® 9th generation LP graphics core architecture with up to 18 execution units
supporting three independent displays
GPU Feature Support •3D graphics hardware acceleration
•Support for DirectX12/11.3/10/9.3, OCL 2.0, OGL ES 3.0, OGL 4.3
•Video decode hardware acceleration including support for H.265 (HEVC), H.264, MVC,
MPEG-2, VC-1, WMV9, VP8/VP9, JPEG/MJPEG formats
•Video encode hardware acceleration including support for H.265 (HEVC), H.264,
VP8/VP9, JPEG/MJPEG formats
•Supports content protection using PAVP 2.0 and HDCP 1.4/2.0
Note: Availability of features may vary between operating systems.
Display Types •Dual/single channel 18/24-bit LVDS, supports DE mode and H/V-Sync mode display
•eDP x4 lanes (eDP 1.3, by build option in place of LVDS)
•DDI1/2 support DisplayPort (DP 1.2), HDMI (1.4b), DVI
•VGA (via DP-to-VGA IC, by build option in place of DDI2)
Note: Only two simultaneous HDMI/DVI outputs supported.
2.4. Audio
Integrated Intel® HD Audio integrated on SoC
Codec Located on carrier Express-BASE6 (ALC886 standard support)
2.5. LAN
MAC/PHY Intel® i210 Ethernet controller (Intel® i211 is supported by project basis)
Interface 10/100/1000 Mbit/s connection, IEEE 1588 support
Notes: PCIe port 5 is supported by build option, in place of GbE. Supports GBE0_SDP on A49 pin.
2.6. Multi I/O and Storage
USB •3x USB 3.0/2.0/1.1 (USB 0/1/2)
•5x USB 2.0/1.1 (USB 3/4/5/6/7)
Note: USB port 0 supports USB 2.0 OTG on Yocto Linux OS
SATA 2x SATA 6Gb/s (SATA0, SATA1)
GPIO 4 GPO and 4 GPI
Note: GPI with interruput supported on Linux.
eMMC 5.0 (build option) 8/16/32 GB (boot device support may vary between operating systems)*
SD SD 3.0 signal is muxed with GPIO, switching controlled by BIOS setting (boot device
support may vary between operating systems)*
Note: Supports 3.3V SD cards only.
*Note: See table below for detailed boot device support information.

cExpress-AL
Specifications 5
Boot Device Support
Windows 10
Enterprise Linux (Yocto) Windows IOT Core
eMMC 5.0 Yes Yes TBD Storage only
SD Yes Yes TBD
eMMC 5.0 Yes Yes TBD OS Installation
SD No No TBD
Note: eMMC and SD functionality as an OS installation device may change dependent on Intel updates. Please
contact your local sales representative for more information.
2.7. Serial I/O
zPorts: 2x UART ports COM 1/2 (COM 1/2 supports console redirection), baud rate up to 115.2 kbps
Port Description IRQ Address Console Redirection
Support
COM 1 Supported by module (SER0, A98/A99), via NCT5104D 10 0x240 Yes
COM 2 Supported by module (SER1, A101/A102), via NCT5104D 11 0x248 Yes
COM 3 Supported by Super I/O (W83627DHG) on carrier board 4 0x3F8 Yes
COM 4 Supported by Super I/O (W83627DHG) on carrier board 3 0x2F8 Yes
2.8. SEMA Board Controller
zType: ADLINK Smart Embedded Management Agent (SEMA)
zFunctions:
•Voltage/Current monitoring
•Power sequence debug support
•AT/ATX mode control
•Logistics and forensic information
•Flat panel control
•General purpose I2C
•Failsafe BIOS (dual BIOS )
•Watchdog timer and fan control
2.9. Debug
z40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
zMIPI60 60-pin header for debug of SoC (build option)
2.10. Trusted Platform Module (TPM)
zChipset: Infineon (build option)
zType: TPM 2.0

6 Specifications
2.11. Power Specifications
Power Modes AT and ATX mode (AT mode startup controlled by SEMA Board Controller)
Standard Voltage Input ATX: 12V±5% / 5Vsb ±5% or AT = 12V±5%
Wide Voltage Input ATX: 4.75-20 V / 5Vsb ±5% or AT = 4.75-20 V
Power Management ACPI 5.0 compliant, Smart Battery support
Power States Supports C0, C1, C1E, C6L, C6, C7, S0, S3, S4, S5, S5 ECO mode (Wake-on-USB
S3/S4, WoL S3/S4/S5)
ECO Mode Supports deep S5 for 5Vsb power saving
Please contact your ADLINK representative for the document “COM Express Module Power Consumption”.
2.12. Operating Temperatures
Standard Operating
Temperature 0°C to +60°C (Wide Voltage Input)
Storage: -20°C to +70°C
Extreme Rugged Operating
Temperature (optional) -40°C to +85°C (Standard Voltage Input only, build option supported by Atom™ SKUs
only)
Storage: -40°C to +85°C
2.13. Environmental
Humidity Operating: 5-90% RH, non-condensing
Storage: 5-95% RH (and operating with conformal coating)
Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,
Condition D
HALT Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.14. Specification Compliance
zPICMG COM.0: Rev. 3.0 Type 6, Compact size 95 x 95 mm
2.15. Operating Systems
Standard Support •Windows 10 Enterprise 64-bit
•Linux 64-bit
•VxWorks 64-bit (under verification)
Extended Support (BSP) •Linux (64-bit)
•VxWorks 64-bit (under verification)

cExpress-AL
Specifications 7
2.16. Functional Diagram
AB
Intel® Atom®
Intel® Pentium®
Intel® Celeron®
“Apollo Lake”
CD
SODIMM
1867/1600 MHz
2‐8 GB DDR3L
non‐ECC
DDI1 (4 lanes)
DP/HDMI
HD Audio
2x SATA 6Gb/s (port 0/1)
8x USB 2.0/1.0 (ports 0‐7)
(OTG on port 0, OS dependent)
MIPI60
60‐pin
(build option)
DDI2 (4 lanes)
DP/HDMI
3x USB 3.0 upgrade
(ports 0/1/2)
Single/dual channel
18/24‐bit LVDS
eDP
LM73
SEMA
BMC
SMBus
GP I2C
SPI 0
BIOS
LPC bus
SPI
SPI 1
BIOS
DDC I2C
SPI_CS#
SODIMM
1867/1600 MHz
2‐8 GB DDR3L
non‐ECC
eDP x4 lanes (build option)
LVDS
eDP to LVDS
4x GPI, 4x GPO (SD)
GPIO
SD
PCIe x1 (port0)
PCIe x1 (port1)
PCIe x1 (port2)
PCIe Bridge
(build option)
PCIe x1 (port3)
PCIe x1 (port4)
GbE
TPM 2.0
(build option)
I2C
MUX
VGA
DP to VGA
(build option) Note: max. capacity is 8GB
(2x 4GB or 1x 8GB)
UART0
UART1
LPC to
UART
GBE0_SDP
eMMC 5.0
8/16/32GB
(build option)
Figure 1: cExpress-AL Functional Block Diagram

8 Specifications
2.17. Mechanical Drawing
Top View
Side View
2.7
6
0
0
4
88.9
91
6
18
4 16.5 74.2 80
4
91
0 4
91
42
95
95
95
88.34 74.54
82.93
connector on bottom side
3.25 2
5.2 9.2
All are dimensions shown in millimeters.
Tolerances should be ± 0.25mm, unless otherwise noted. The tolerances of the module
connector locating peg holes (16.50, 6.00] and [16.50, 18.00]) should be ±0.10mm.
Figure 2: cExpress-AL Mechanical Drawing

cExpress-AL
Pinouts and Signal Descriptions 9
3. Pinouts and Signal Descriptions
3.1. AB/CD Pin Definitions
The cExpress-AL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector
All pins in the COM Express specification are described, including those not supported on the cExpress-AL. Those
not supported on the cExpress-AL module are crossed out.
Table 1: cExpress-AL AB/CD Pin Definitions
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 GND D2 GND
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 USB_SSRX0- D3 USB_SSTX0-
A4 GBE0_LINK100# B4 LPC_AD0 C4 USB_SSRX0+ D4 USB_SSTX0+
A5 GBE0_LINK1000# B5 LPC_AD1 C5 GND D5 GND
A6 GBE0_MDI2- B6 LPC_AD2 C6 USB_SSRX1- D6 USB_SSTX1-
A7 GBE0_MDI2+ B7 LPC_AD3 C7 USB_SSRX1+ D7 USB_SSTX1+
A8 GBE0_LINK# B8 LPC_DRQ0# C8 GND D8 GND
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 USB_SSRX2- D9 USB_SSTX2-
A10 GBE0_MDI1+ B10 LPC_CLK C10 USB_SSRX2+ D10 USB_SSTX2+
A11 GND (fixed) B11 GND (fixed) C11 GND (fixed) D11 GND (fixed)
A12 GBE0_MDI0- B12 PWRBTN# C12 USB_SSRX3- D12 USB_SSTX3-
A13 GBE0_MDI0+ B13 SMB_CK C13 USB_SSRX3+ D13 USB_SSTX3+
A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND
A15 SUS_S3# B15 SMB_ALERT# C15 DDI1_PAIR6+ D15 DDI1_CTRLCLK_AUX+
A16 SATA0_TX+ B16 SATA1_TX+ C16 DDI1_PAIR6‐D16 DDI1_CTRLDATA_AUX
A17 SATA0_TX- B17 SATA1_TX- C17 RSVD D17 RSVD
A18 SUS_S4# B18 SUS_STAT# C18 RSVD D18 RSVD
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCIE_RX6+ D19 PCIE_TX6+
A20 SATA0_RX- B20 SATA1_RX- C20 PCIE_RX6- D20 PCIE_TX6-
A21 GND (fixed) B21 GND (fixed) C21 GND (fixed) D21 GND (fixed)
A22 SATA2_TX+ B22 SATA3_TX+ C22 PCIE_RX7+ D22 PCIE_TX7+
A23 SATA2_TX- B23 SATA3_TX- C23 PCIE_RX7- D23 PCIE_TX7-
A24 SUS_S5# B24 PWR_OK C24 DDI1_HPD D24 RSVD
A25 SATA2_RX+ B25 SATA3_RX+ C25 DDI1_PAIR4+ D25 RSVD
A26 SATA2_RX- B26 SATA3_RX- C26 DDI1_PAIR4- D26 DDI1_PAIR0+
A27 BATLOW# B27 WDT C27 RSVD D27 DDI1_PAIR0-
A28 (S)ATA_ACT# B28 HDA_SDIN2 C28 RSVD D28 RSVD
A29 HDA_SYNC B29 HDA_SDIN1 C29 DDI1_PAIR5+ D29 DDI1_PAIR1+
A30 HDA_RST# B30 HDA_SDIN0 C30 DDI1_PAIR5- D30 DDI1_PAIR1-
A31 GND (fixed) B31 GND (fixed) C31 GND (fixed) D31 GND (fixed)
A32 HDA_BITCLK B32 SPKR C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+
A33 HDA_SDOUT B33 I2C_CK C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2-
A34 BIOS_DIS0# B34 I2C_DAT C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL
A35 THRMTRIP# B35 THRM# C35 RSVD D35 RSVD

10 Pinouts and Signal Descriptions
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A36 USB6‐B36 USB7‐C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+
A37 USB6+ B37 USB7+ C37 DDI3_CTRLDATA_AUX D37 DDI1_PAIR3‐
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 DDI3_DDC_AUX_SEL D38 RSVD
A39 USB4‐B39 USB5‐C39 DDI3_PAIR0+ D39 DDI2_PAIR0+
A40 USB4+ B40 USB5+ C40 DDI3_PAIR0-D40 DDI2_PAIR0‐
A41 GND (fixed) B41 GND (fixed) C41 GND (fixed) D41 GND (fixed)
A42 USB2‐B42 USB3‐C42 DDI3_PAIR1+ D42 DDI2_PAIR1+
A43 USB2+ B43 USB3+ C43 DDI3_PAIR1-D43 DDI2_PAIR1‐
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 DDI3_HPD D44 DDI2_HPD
A45 USB0‐B45 USB1‐C45 RSVD D45 RSVD
A46 USB0+ B46 USB1+ C46 DDI3_PAIR2+ D46 DDI2_PAIR2+
A47 VCC_RTC B47 ESPI_EN# C47 DDI3_PAIR2-D47 DDI2_PAIR2‐
A48 RSVD B48 USB0_HOST_PRSNT C48 RSVD D48 RSVD
A49 GBE0_SDP B49 SYS_RESET# C49 DDI3_PAIR3+ D49 DDI2_PAIR3+
A50 LPC_SERIRQ B50 CB_RESET# C50 DDI3_PAIR3-D50 DDI2_PAIR3‐
A51 GND (fixed) B51 GND (fixed) C51 GND (fixed) D51 GND (fixed)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+
A53 PCIE_TX5‐B53 PCIE_RX5‐C53 PEG_RX0‐D53 PEG_TX0‐
A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCIE_TX4+ * B55 PCIE_RX4+ * C55 PEG_RX1+ D55 PEG_TX1+
A56 PCIE_TX4‐* B56 PCIE_RX4‐* C56 PEG_RX1‐D56 PEG_TX1‐
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+
A59 PCIE_TX3‐B59 PCIE_RX3‐C59 PEG_RX2‐D59 PEG_TX2‐
A60 GND (fixed) B60 GND (fixed) C60 GND (fixed) D60 GND (fixed)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+
A62 PCIE_TX2‐B62 PCIE_RX2‐C62 PEG_RX3‐D62 PEG_TX3‐
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1‐B65 PCIE_RX1‐C65 PEG_RX4+ D65 PEG_TX4+
A66 GND B66 WAKE0# C66 PEG_RX4‐D66 PEG_TX4‐
A67 GPI2 B67 WAKE1# C67 RAPID_SHUTDOWN D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+
A69 PCIE_TX0‐B69 PCIE_RX0‐C69 PEG_RX5‐D69 PEG_TX5‐
A70 GND (fixed) B70 GND (fixed) C70 GND (fixed) D70 GND (fixed)
A71 LVDS_A0+ B71 LVDS_B0+ C71 PEG_RX6+ D71 PEG_TX6+
A72 LVDS_A0‐B72 LVDS_B0‐C72 PEG_RX6‐D72 PEG_TX6‐
A73 LVDS_A1+ B73 LVDS_B1+ C73 GND D73 GND
A74 LVDS_A1‐B74 LVDS_B1‐C74 PEG_RX7+ D74 PEG_TX7+
A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7‐D75 PEG_TX7‐
A76 LVDS_A2‐B76 LVDS_B2‐C76 GND D76 GND
A77 LVDS_VDD_EN B77 LVDS_B3+ C77 RSVD D77 RSVD
A78 LVDS_A3+ B78 LVDS_B3‐C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3‐B79 LVDS_BKLT_EN C79 PEG_RX8‐D79 PEG_TX8‐

cExpress-AL
Pinouts and Signal Descriptions 11
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED)
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK‐B82 LVDS_B_CK‐C82 PEG_RX9‐D82 PEG_TX9‐
A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10‐D86 PEG_TX10‐
A87 eDP_HPD B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
A89 PCIE0_CK_REF‐B89 VGA_RED* C89 PEG_RX11‐D89 PEG_TX11‐
A90 GND (fixed) B90 GND (fixed) C90 GND (fixed) D90 GND (fixed)
A91 SPI_POWER B91 VGA_GRN* C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU* C92 PEG_RX12‐D92 PEG_TX12‐
A93 GPO0 B93 VGA_HSYNC* C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC* C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK* C95 PEG_RX13‐D95 PEG_TX13‐
A96 TPM_PP B96 VGA_I2C_DAT* C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 RSVD
A98 SER0_TX B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 SER0_RX B99 RSVD C99 PEG_RX14‐D99 PEG_TX14‐
A100 GND (fixed) B100 GND (fixed) C100 GND (fixed) D100 GND (fixed)
A101 SER1_TX B101 FAN_PWMOUT C101 PEG_RX15+ D101 PEG_TX15+
A102 SER1_RX B102 FAN_TACHIN C102 PEG_RX15‐D102 PEG_TX15‐
A103 LID# B103 SLEEP# C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
Notes:
•LID# and SLEEP# signals are not natively supported on the SoC. They instead connect to GPIO pins
simulating their behaviour.
•*VGA is by build option, in place of DDI2
•eDP x4 lanes is by build option, in place of LVDS
•SD signal is muxed with GPIO, switching controlled by BIOS setting (see section 3.3.14)
•PCIe bridge IC is by build option to support more than 4 PCIe x1 (e.g. PCIe lane 4)

12 Pinouts and Signal Descriptions
3.2. Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input/output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module

cExpress-AL
Pinouts and Signal Descriptions 13
3.3. AB Signal Descriptions
3.3.1. Audio Signals
Signal Pin Description I/O PU/PD Comment
HDA_RST# A30 Reset output to CODEC, active low. O 3.3V
HDA_SYNC A29
Sample-synchronization signal to the
CODEC(s).
O 3.3V
HDA_BITCLK A32 Serial data clock generated by the
external CODEC(s).
I/O 3.3V
HDA_SDOUT A33 Serial TDM data output to the CODEC. O 3.3V
HDA_SDIN[2:0] B28
B30
Serial TDM data inputs from up to 3
CODECs.
I/O 3.3V PD 680
ohm
Only supports HDA_SDIN0.
PD 680 ohm, based on SoC
vendor guidance.
3.3.2. Analog VGA (build option)
Signal Pin Description I/O PU/PD Comment
VGA_RED B89
Red for monitor.
Analog DAC output, designed to
drive a 37.5-Ohm equivalent load.
O Analog PD 150R
VGA_GRN B91
Green for monitor
Analog DAC output, designed to
drive a 37.5-Ohm equivalent load.
O Analog PD 150R
VGA_BLU B92
Blue for monitor.
Analog DAC output, designed to
drive a 37.5-Ohm equivalent load.
O Analog PD 150R
VGA_HSYNC B93 Horizontal sync output to VGA
monitor
O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated
to identify VGA monitor capabilities)
I/O OD 3.3V PU 2k2
3.3V
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V PU 2k2
3.3V
VGA is by build option, in
place of DDI 2

14 Pinouts and Signal Descriptions
3.3.3. LVDS/eDP
LVDS
Signal Pin Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential pairs O LVDS
LVDS_A_CK+
LVDS_A_CK-
A81
A82
LVDS Channel A differential clock O LVDS
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
B71
B72
B73
B74
B75
B76
B77
B78
LVDS Channel B differential pairs O LVDS
LVDS_B_CK+
LVDS_B_CK-
B81
B82
LVDS Channel B differential clock O LVDS
LVDS is default.
(through eDP to LVDS
bridge)
Note: eDP support
available by build
option
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 10k
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V PD 100k ePD to LVDS
requirement
LVDS_I2C_CK A83
DDC lines used for flat panel detection and
control.
O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84
DDC lines used for flat panel detection and
control.
I/O 3.3V PU 2k2 3.3V
eDP (build option)
Signal Pin Description I/O PU/PD Comment
eDP_TX2+
eDP_TX2-
eDP_TX1+
eDP_TX1-
eDP_TX0+
eDP_TX0--
A71
A72
A73
A74
A75
A76
eDP differential pairs O PCIE AC coupled off module
eDP_TX3+
eDP_TX3--
A81
A82
eDP differential pairs O PCIE AC coupled off module
eDP_VDD_EN A77 eDP power enable O 3.3V PD 10k
eDP_BKLT_EN B79 eDP backlight enable O 3.3V
eDP_BKLT_CTRL B83 eDP backlight brightness control O 3.3V PD 100k
eDP_AUX+ A83 eDP AUX+ I/O PCIE AC coupled off module
eDP_AUX- A84 eDP AUX- I/O PCIE AC coupled off module
eDP_HPD A87
Detection of Hot Plug / Unplug and
notification of the link layer
I 3.3V PD 100k