AMD -K6-2/450 - MHz Processor Installation and operating instructions

®
Embedded
AMD-K6™
Processors
BIOS Design Guide
Publication # 23913 Rev: AAmendment/0
Issue Date: November 2000
Application Note

Trademarks
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Other product names used in this publication are for identification purposes only and may be trademarks of their
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© 2000 Advanced Micro Devices, Inc. All rights reserved.
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products at any time without notice.

Contents iii
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Processor Models and Steppings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
AMD-K6™E Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . 3
AMD-K6™-2 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
AMD-K6™-2E Embedded Processor. . . . . . . . . . . . . . . . . . . . . . 4
AMD-K6™-2E+ Embedded Processor. . . . . . . . . . . . . . . . . . . . . 4
AMD-K6™-III Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AMD-K6™-IIIE+ Embedded Processor . . . . . . . . . . . . . . . . . . . 5
BIOS Consideration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPU Speed Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . . 6
Cache Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SMM Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
States after RESET and INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register States after RESET and INIT . . . . . . . . . . . . . . . . . . . 8
Processor State after INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPUID Identification Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
State-Save Map Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Trap Dword Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Model-Specific Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standard Model-Specific Registers (All Models) . . . . . . . . . . 16
Model 7 and Model 8/[7:0] Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 18
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 19
SYSCALL/SYSRET Target Address Register (STAR) . . . . . . 22

iv Contents
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Model 8/[F:8] Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 24
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 27
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . 30
Processor State Observability Register (PSOR) . . . . . . . . . . . 34
Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 36
Model 9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 39
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . . 40
Model D Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Processor State Observability Register (PSOR)
(Low-Power Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . . 48
Enhanced Power Management Register (EPMR)
(Low-Power Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
EPM 16-Byte I/O Block (Low-Power Versions Only). . . . . . . . 55
Embedded AMD Processor Recognition. . . . . . . . . . . . . . . . . . . . . . . 57
CPUID Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Testing for the CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . 58
Using CPUID Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Identifying the Processor’s Vendor . . . . . . . . . . . . . . . . . . . . . 60
Testing For Extended Functions . . . . . . . . . . . . . . . . . . . . . . . 61
Determining the Processor Signature . . . . . . . . . . . . . . . . . . . 61
Identifying Supported Features . . . . . . . . . . . . . . . . . . . . . . . . 63
Determining Instruction Set Support. . . . . . . . . . . . . . . . . . . . 64
Detection Algorithm for Determining Instruction Set
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AMD Processor Signature (Extended Function). . . . . . . . . . . 66
Displaying the Processor’s Name . . . . . . . . . . . . . . . . . . . . . . . 66
Displaying Cache Information . . . . . . . . . . . . . . . . . . . . . . . . . 67
Determining AMD PowerNow!™ Technology Information . . 67
Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
New AMD-K6™ Processor Instructions. . . . . . . . . . . . . . . . . . . . . . . . 68
Additional Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Contents v
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Software Timing Dependencies Relative to Memory
Controller Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Pipelining Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Standard Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Extended Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Cache Associativity Field Definitions . . . . . . . . . . . . . . . . . . . 80
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Values Returned by the CPUID Instruction . . . . . . . . . . . . . . 81
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

vi Contents
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information

List of Figures vii
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
List of Figures
Figure 1. CPUID Instruction Flow Chart . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Extended Feature Enable Register (EFER)
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Write Handling Control Register (WHCR)
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. SYSCALL/SYSRET Target Address Register (STAR)
(Models 8, 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Extended Feature Enable Register (EFER)
(Model 8/[F:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Write Handling Control Register (WHCR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7. UC/WC Cacheability Control Register (UWCCR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. Processor State Observability Register (PSOR)
(Models 8/[F:8], 9, and Standard-Power D) . . . . . . . . . . . 34
Figure 9. Page Flush/Invalidate Register (PFIR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Extended Feature Enable Register (EFER)
(Models 9 and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. L2 Cache Organization (AMD-K6™-III Processor) . . . . . 40
Figure 12. L2 Cache Sector and Line Organization . . . . . . . . . . . . . 41
Figure 13. L2 Tag or Data Location (AMD-K6™-III
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. L2 Data—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. L2 Tag Information (AMD-K6™-III Processor)—EAX . . 43
Figure 16. LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17. Processor State Observability Register (PSOR)
(Model D Low-Power Versions) . . . . . . . . . . . . . . . . . . . . 46
Figure 18. L2 Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19. L2 Cache Sector and Line Organization
(same as Figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

viii List of Figures
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Figure 20. L2 Tag or Data Location (AMD-K6™-2E+
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21. L2 Tag or Data Location (AMD-K6™-IIIE+
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. L2 Data—EAX (same as Figure 14) . . . . . . . . . . . . . . . . . 51
Figure 23. L2 Tag Information (AMD-K6™-2E+
Processor)—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24. L2 Tag Information (AMD-K6™-IIIE+
Processor)—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25. LRU Byte (same as Figure 16) . . . . . . . . . . . . . . . . . . . . . 53
Figure 26. Enhanced Power Management Register (EPMR)
(Low-Power Model D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 27. EPM 16-Byte I/O Block (Low-Power Model D) . . . . . . . . 55
Figure 28. Bus Divisor and Voltage ID Control (BVC) Field
(Low-Power Model D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 29. Contents of EAX Register Returned by Function 1 . . . . 62
Figure 30. Contents of EAX Register Returned by
Extended Function 8000_0001h . . . . . . . . . . . . . . . . . . . . 66

List of Tables ix
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
List of Tables
Table 1. Features of the AMD-K6™ Processor Family . . . . . . . . . . 2
Table 2. AMD-K6™E Processor (Model 7) and AMD-K6™ Processor
(Model 8/[7:0]) State after RESET . . . . . . . . . . . . . . . . . . . 8
Table 3. AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E
Processor (Model 8/[F:8]) State after RESET . . . . . . . . . . 8
Table 4. AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and
AMD-K6™-IIIE+ Processors (Model D)
State after RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Recommended Boot Strings for AMD-K6™ Processors . 11
Table 6. AMD-K6™ Processor I/O Trap Dword Configuration
at Offset FFA4h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Summary by Register of MSR Differences within the
AMD-K6™ Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Summary by Model of MSR Differences within the
AMD-K6™ Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Model-Specific Registers Supported by Models 7 and
8/[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Extended Feature Enable Register (EFER) Definition
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. SYSCALL/SYSRET Target Address Register (STAR)
Definition (Models 8, 9, and D). . . . . . . . . . . . . . . . . . . . . 22
Table 12. Model-Specific Registers Supported by Model 8/[F:8]. . 23
Table 13. Extended Feature Enable Register (EFER)
Definition (Model 8/[F:8]) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Write Ordering and Performance Settings for EFER
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. WC/UC Memory Type for UWCCR Register . . . . . . . . . . 31
Table 16. Valid Masks and Range Sizes for UWCCR Register. . . . 32
Table 17. Processor-to-Bus Clock Ratios (Models 8/[F:8] and 9) . . 35

xList of Tables
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Table 18. Processor-to-Bus Clock Ratios
(Model Standard-Power D) . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Model-Specific Registers Supported by Model 9 . . . . . . 38
Table 20. Extended Feature Enable Register (EFER) Definition
(Models 9 and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. Tag versus Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Model-Specific Registers Supported by Model D . . . . . . 45
Table 23. Processor-to-Bus Clock Ratios (Low-Power Model D) . . . 47
Table 24. Tag versus Data Selector (same as Table 21). . . . . . . . . . 51
Table 25. Enhanced Power Management Register (EPMR)
Definition (Low-Power Model D) . . . . . . . . . . . . . . . . . . . 54
Table 26. EPM 16-Byte I/O Block Definition (Low-Power Model D) 55
Table 27. Bus Divisor and Voltage ID Control (BVC) Definition
(Low-Power Model D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 28. CPUID Functions in AMD-K6™ Processors. . . . . . . . . . . 60
Table 29. Processor Signatures for AMD-K6™ Processors . . . . . . . 62
Table 30. Standard and Extended Feature Bits . . . . . . . . . . . . . . . . 63
Table 31. Standard Feature Flag Descriptions. . . . . . . . . . . . . . . . . 74
Table 32. Extended Feature Flag Descriptions . . . . . . . . . . . . . . . . 76
Table 33. EBX Format Returned by Function 8000_0005h. . . . . . . 78
Table 34. ECX Format Returned by Function 8000_0005h. . . . . . . 78
Table 35. EDX Format Returned by Function 8000_0005h . . . . . . 78
Table 36. ECX Format Returned by Function 8000_0006h. . . . . . . 79
Table 37. EDX Format Returned by Function 8000_0007h . . . . . . 79
Table 38. Associativity Values for L2 Cache . . . . . . . . . . . . . . . . . . 80
Table 39. CPUID Values Returned by AMD-K6™ Processors . . . . 81

Revision History xi
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Revision History
Date Rev Description
November 2000 A Initial public release.

xii Revision History
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information

23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Introduction 1
Application Note
Embedded AMD-K6™
Processors BIOS Design Guide
Introduction
This document highlights the BIOS modifications required to
fully support the AMD-K6™ processors used by AMD’s
embedded customers. The information in this application note
pertains to the following processors in the AMD-K6 family:
■AMD-K6E embedded processor
■AMD-K6-2 processor
■AMD-K6-2E embedded processor
■AMD-K6-2E+ embedded processor
■AMD-K6-III processor
■AMD-K6-IIIE+ embedded processor
There can be more than one way to implement the functionality
detailed in this document, and the information provided is for
demonstration purposes.
All referenced AMD-K6 processor documents can be found on
the AMD website at http://www.amd.com/.
Audience
It is assumed that the reader has a solid understanding of the
x86 processors, the x86 architecture, and programming
requirements.

2Processor Models and Steppings
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Processor Models and Steppings
Four models within the AMD-K6 family of processors—models
7, 8, 9, and D—are discussed in this document.
For most models, feature and function detection can be
determined by reading the standard and extended feature bits
by executing the CPUID instruction. However, for certain
models, it is necessary to check the stepping—by executing the
CPUID instruction—to determine specific function support.
Table 1 shows the features of each model and stepping of the
AMD-K6 processor family.
The descriptions in the remainder of this section provide more
detailed information on the AMD-K6 processor family
members, and the models and steppings that comprise each
member.
Table 7 on page 14 and Table 8 on page 15 summarize the MSR
differences between the models and steppings of the AMD-K6
family of processors.
Table 1. Features of the AMD-K6™ Processor Family
Processor Model/
Stepping Process(in microns)
Number
of MSRs1
Notes:
1. Refer to “Model-Specific Registers Overview” on page 14 for more information.
3DNow!™
Instructions 3DNow! Extensions AMD PowerNow!™ Technology L2 Cache
AMD-K6E 7 0.25 6
AMD-K6-2 8/[7:0] 0.25 7 Yes
AMD-K6-2 and
AMD-K6-2E 8/[F:8] 0.25 102
2. Model 8/[F:8] defines the bits and fields in the Write Handling Control Register (WHCR) and Extended Feature Enable Register (EFER)
differently from the models 7 and 8/[7:0].
Yes
AMD-K6-2E+ D/[7:4] 0.18 113,4
3. This model implements the same ten MSRs as the Model 8/[F:8]. With the exception of bit 4 (L2D) in the EFER register, the bits and
fields within these ten MSRs are defined identically.
4. Low-power versions implement one additional register to support AMD PowerNow!™ technology.
Yes Yes Yes5
5. AMD PowerNow! technology is supported on low-power versions of these processors only.
128 Kbytes
AMD-K6-III 9/[3:0] 0.25 113Yes 256 Kbytes
AMD-K6-IIIE+ D/[3:0] 0.18 113,4 Yes Yes Yes5

Processor Models and Steppings 3
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
AMD-K6™E Embedded Processor
Model 7 Model 7 is the first processor manufactured in the 0.25-micron
process.
■Model 7 supports six model-specific registers (MSRs).
AMD-K6™-2 Processor
Some important features supported by the AMD-K6-2 processor
include the 3DNow!™ instruction set and a 100-MHz processor
bus.
Model 8/[7:0] Model 8/[7:0] is any of eight possible model/steppings—models
8/0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, or 8/7. Model 8/[7:0] is
manufactured in the 0.25-micron process and was the original
version of the AMD-K6-2 available as a desktop product.
■Model 8/[7:0] implements the same six MSRs as the Model 7,
and the bits and fields within these six MSRs are defined
identically.
■Model 8/[7:0] also implements the SYSCALL/SYSRET
Target Address Register (STAR) MSR for a total of seven
MSRs.
Model 8/[F:8] Model 8/[F:8] is any of eight possible model/steppings—models
8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, or 8/F. Model 8/[F:8] is
manufactured in the 0.25-micron process.
■Model 8/[F:8] implements the same six MSRs as the models
7 and 8/[7:0], but the bits and fields within two of these
MSRs—WHCR and EFER—are not defined identically.
■Also, Model 8/[F:8] supports the STAR MSR and three
additional MSRs, for a total of ten MSRs.

4Processor Models and Steppings
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
AMD-K6™-2E Embedded Processor
The AMD-K6-2E processor also supports the 3DNow!
instruction set and a 100-MHz processor bus.
Model 8/[F:8] Model 8/[F:8] is any of eight possible model/steppings—models
8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, or 8/F. Model 8/[F:8] is
manufactured in the 0.25-micron process.
■Model 8/[F:8] implements the same six MSRs as the models
7 and 8/[7:0], but the bits and fields within two of these
MSRs—WHCR and EFER—are not defined identically.
■Also, Model 8/[F:8] supports the STAR MSR and three
additional MSRs, for a total of ten MSRs.
AMD-K6™-2E+ Embedded Processor
In addition to supporting the 3DNow! instruction set and a 100-
MHz processor bus, the AMD-K6-2E+ processor contains a 128-
Kbyte backside L2 cache. It also supports the 3DNow! DSP
instructions extensions. Low-power versions of the processor
support AMD PowerNow!™ technology.
Model D/[7:4] Model D/[7:4] is any of four possible model/steppings—models
D/4, D/5, D/6, or D/7. Model D/[7:4] is manufactured in the 0.18-
micron process.
■Model D/[7:4] implements the same ten MSRs as the Model
8/[F:8]. With the exception of bit 4 (L2D) in the EFER
register, the bits and fields within these ten MSRs are
defined identically for standard-power versions. The PSOR
register is defined differently for low-power versions.
■Model D/[7:4] supports an additional MSR, the Level-2
Cache Array Access Register (L2AAR), for a total of eleven
MSRs.
■Low-power versions of Model D/[7:4] support an additional
MSR, the Enhanced Power Management Register (EPMR),
for a total of twelve MSRs.

Processor Models and Steppings 5
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
AMD-K6™-III Processor
In addition to supporting the 3DNow! instruction set and a 100-
MHz processor bus, the AMD-K6-III processor contains a 256-
Kbyte backside L2 cache.
Model 9/[3:0] Model 9/[3:0] is any of four possible model/steppings—models
9/0, 9/1, 9/2, or 9/3. Model 9/[3:0] is manufactured in the 0.25-
micron process.
■Model 9/[3:0] implements the same ten MSRs as the Model
8/[F:8]. With the exception of bit 4 (L2D) in the EFER
register, the bits and fields within these ten MSRs are
defined identically.
■Model 9/[3:0] supports one additional MSR for a total of
eleven MSRs.
AMD-K6™-IIIE+ Embedded Processor
In addition to supporting the 3DNow! instruction set and a 100-
MHz processor bus, the AMD-K6-IIIE+ processor contains a 256-
Kbyte backside L2 cache. It also supports the 3DNow! DSP
instruction extensions. Low-power versions of the processor
support AMD PowerNow! technology.
Model D/[3:0] Model D/[3:0] is any of four possible model/steppings—models
D/0, D/1, D/2, or D/3. Model D/[3:0] is manufactured in the 0.18-
micron process.
■Model D/[3:0] implements the same ten MSRs as the Model
8/[F:8]. With the exception of bit 4 (L2D) in the EFER
register, the bits and fields within these ten MSRs are
defined identically for standard-power versions. The PSOR
register is defined differently for low-power versions.
■Model D/[7:4] supports an additional MSR, the Level-2
Cache Array Access Register (L2AAR), for a total of eleven
MSRs.
■Low-power versions of Model D/[7:4] support an additional
MSR, the Enhanced Power Management Register (EPMR),
for a total of twelve MSRs.

6BIOS Consideration Checklist
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
BIOS Consideration Checklist
CPUID
■Use the CPUID instruction to properly identify the
processor. For information on the CPUID instruction, see
“CPUID Instruction Overview” on page 57.
■Determine the processor model, stepping, and features
using functions 0000_0001h and 8000_0001h of the CPUID
instruction.
■Display the processor name (BIOS boot strings) as described
in “CPUID Identification Algorithms” on page 11.
CPU Speed Detection
■Use speed detection algorithms that do not rely on
repetitive instruction sequences.
■Use the Time Stamp Counter (TSC) to ‘clock’ a timed
operation and compare the result to the real-time clock
(RTC) to determine the operating frequency. See the CPU
Speed Determination Program available on the AMD website
at http://www.amd.com/products/cpg/bin/.
■Display the recommended BIOS boot string as shown in
Table 5 on page 11.
Model-Specific Registers (MSRs)
■Only access MSRs implemented in the processor.
■Enable write allocation by programming the Write Handling
Control Register (WHCR). See “Write Handling Control
Register (WHCR)” on page 19 and page 27, and the
Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326 for more information.
Note: The WHCR register as defined in models 7 and 8/[7:0] is
implemented differently in models 8/[F:8], 9, and D.
■For the AMD-K6-2E, AMD-K6-2E+, AMD-K6-III, and
AMD-K6-IIIE+ processors, utilize the information provided
in the Processor State Observability Register (PSOR) to
display the correct processor bus frequency.

BIOS Consideration Checklist 7
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Cache Testing
■The AMD-K6 family of processors does not contain MSRs to
allow for testing of the L1 cache. However, the AMD-K6-2E+,
AMD-K6-III, and AMD-K6-IIIE+ processors do contain an
MSR that allows for testing of their L2 caches. This MSR is
called L2AAR, and it is described in “Level-2 Cache Array
Access Register (L2AAR)” on page 40.
SMM Issues
■The System Management Mode (SMM) functionality of the
processor is the same as the Pentium® processor.
■Implement the processor SMM state-save area in a similar
manner as Pentium processors except for the IDT Base and
possibly Pentium processor-reserved areas. See “System
Management Mode (SMM)” on page 13 for more
information.

8States after RESET and INIT
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
States after RESET and INIT
Register States after RESET and INIT
After the processor has completed its initialization following
the recognition of an asserted RESET or INIT signal, the states
of all architecture registers and MSRs are compatible with
those of Pentium processors. Differences are listed in Table 2
through Table 4.
Table 2. AMD-K6™E Processor (Model 7) and AMD-K6™ Processor (Model
8/[7:0]) State after RESET
Register RESET State
EDX 0000_05MSh1
Notes:
1. “M” represents the Model and “S” represents the Stepping.
EFER 0000_0000_0000_0000h
STAR2
2. Processor Model 7 does not support the STAR register.
0000_0000_0000_0000h
WHCR 0000_0000_0000_0000h
Table 3. AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E Processor
(Model 8/[F:8]) State after RESET
Register RESET State
EDX 0000_05MSh1
Notes:
1. “M” represents the Model and “S” represents the Stepping.
EFER 0000_0000_0000_0002h
PFIR 0000_0000_0000_0000h
PSOR 0000_0000_0000_01SBh1,2
2. “B” represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the
BF[2:0] signals sampled during the falling transition of RESET.
STAR 0000_0000_0000_0000h
UWCCR 0000_0000_0000_0000h
WHCR 0000_0000_0000_0000h