AMD -K6-2/450 - MHz Processor Installation and operating instructions

®
Embedded
AMD-K6™
Processors
BIOS Design Guide
Publication # 23913 Rev: AAmendment/0
Issue Date: November 2000
Application Note

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Contents iii
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Processor Models and Steppings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
AMD-K6™E Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . 3
AMD-K6™-2 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
AMD-K6™-2E Embedded Processor. . . . . . . . . . . . . . . . . . . . . . 4
AMD-K6™-2E+ Embedded Processor. . . . . . . . . . . . . . . . . . . . . 4
AMD-K6™-III Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AMD-K6™-IIIE+ Embedded Processor . . . . . . . . . . . . . . . . . . . 5
BIOS Consideration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CPU Speed Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . . 6
Cache Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SMM Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
States after RESET and INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register States after RESET and INIT . . . . . . . . . . . . . . . . . . . 8
Processor State after INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPUID Identification Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
State-Save Map Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Trap Dword Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Model-Specific Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standard Model-Specific Registers (All Models) . . . . . . . . . . 16
Model 7 and Model 8/[7:0] Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 18
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 19
SYSCALL/SYSRET Target Address Register (STAR) . . . . . . 22

iv Contents
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Model 8/[F:8] Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 24
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 27
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . 30
Processor State Observability Register (PSOR) . . . . . . . . . . . 34
Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 36
Model 9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 39
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . . 40
Model D Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Processor State Observability Register (PSOR)
(Low-Power Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . . 48
Enhanced Power Management Register (EPMR)
(Low-Power Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
EPM 16-Byte I/O Block (Low-Power Versions Only). . . . . . . . 55
Embedded AMD Processor Recognition. . . . . . . . . . . . . . . . . . . . . . . 57
CPUID Instruction Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Testing for the CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . 58
Using CPUID Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Identifying the Processor’s Vendor . . . . . . . . . . . . . . . . . . . . . 60
Testing For Extended Functions . . . . . . . . . . . . . . . . . . . . . . . 61
Determining the Processor Signature . . . . . . . . . . . . . . . . . . . 61
Identifying Supported Features . . . . . . . . . . . . . . . . . . . . . . . . 63
Determining Instruction Set Support. . . . . . . . . . . . . . . . . . . . 64
Detection Algorithm for Determining Instruction Set
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
AMD Processor Signature (Extended Function). . . . . . . . . . . 66
Displaying the Processor’s Name . . . . . . . . . . . . . . . . . . . . . . . 66
Displaying Cache Information . . . . . . . . . . . . . . . . . . . . . . . . . 67
Determining AMD PowerNow!™ Technology Information . . 67
Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
New AMD-K6™ Processor Instructions. . . . . . . . . . . . . . . . . . . . . . . . 68
Additional Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Contents v
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Software Timing Dependencies Relative to Memory
Controller Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Pipelining Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Standard Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Extended Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Cache Associativity Field Definitions . . . . . . . . . . . . . . . . . . . 80
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Values Returned by the CPUID Instruction . . . . . . . . . . . . . . 81
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

vi Contents
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information

List of Figures vii
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
List of Figures
Figure 1. CPUID Instruction Flow Chart . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Extended Feature Enable Register (EFER)
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Write Handling Control Register (WHCR)
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. SYSCALL/SYSRET Target Address Register (STAR)
(Models 8, 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Extended Feature Enable Register (EFER)
(Model 8/[F:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Write Handling Control Register (WHCR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7. UC/WC Cacheability Control Register (UWCCR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. Processor State Observability Register (PSOR)
(Models 8/[F:8], 9, and Standard-Power D) . . . . . . . . . . . 34
Figure 9. Page Flush/Invalidate Register (PFIR)
(Models 8/[F:8], 9, and D) . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. Extended Feature Enable Register (EFER)
(Models 9 and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. L2 Cache Organization (AMD-K6™-III Processor) . . . . . 40
Figure 12. L2 Cache Sector and Line Organization . . . . . . . . . . . . . 41
Figure 13. L2 Tag or Data Location (AMD-K6™-III
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. L2 Data—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. L2 Tag Information (AMD-K6™-III Processor)—EAX . . 43
Figure 16. LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 17. Processor State Observability Register (PSOR)
(Model D Low-Power Versions) . . . . . . . . . . . . . . . . . . . . 46
Figure 18. L2 Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19. L2 Cache Sector and Line Organization
(same as Figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

viii List of Figures
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Figure 20. L2 Tag or Data Location (AMD-K6™-2E+
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21. L2 Tag or Data Location (AMD-K6™-IIIE+
Processor)—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. L2 Data—EAX (same as Figure 14) . . . . . . . . . . . . . . . . . 51
Figure 23. L2 Tag Information (AMD-K6™-2E+
Processor)—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24. L2 Tag Information (AMD-K6™-IIIE+
Processor)—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25. LRU Byte (same as Figure 16) . . . . . . . . . . . . . . . . . . . . . 53
Figure 26. Enhanced Power Management Register (EPMR)
(Low-Power Model D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 27. EPM 16-Byte I/O Block (Low-Power Model D) . . . . . . . . 55
Figure 28. Bus Divisor and Voltage ID Control (BVC) Field
(Low-Power Model D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 29. Contents of EAX Register Returned by Function 1 . . . . 62
Figure 30. Contents of EAX Register Returned by
Extended Function 8000_0001h . . . . . . . . . . . . . . . . . . . . 66

List of Tables ix
23913A/0—November 2000 Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
List of Tables
Table 1. Features of the AMD-K6™ Processor Family . . . . . . . . . . 2
Table 2. AMD-K6™E Processor (Model 7) and AMD-K6™ Processor
(Model 8/[7:0]) State after RESET . . . . . . . . . . . . . . . . . . . 8
Table 3. AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E
Processor (Model 8/[F:8]) State after RESET . . . . . . . . . . 8
Table 4. AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and
AMD-K6™-IIIE+ Processors (Model D)
State after RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Recommended Boot Strings for AMD-K6™ Processors . 11
Table 6. AMD-K6™ Processor I/O Trap Dword Configuration
at Offset FFA4h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Summary by Register of MSR Differences within the
AMD-K6™ Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Summary by Model of MSR Differences within the
AMD-K6™ Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Model-Specific Registers Supported by Models 7 and
8/[7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Extended Feature Enable Register (EFER) Definition
(Models 7 and 8/[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. SYSCALL/SYSRET Target Address Register (STAR)
Definition (Models 8, 9, and D). . . . . . . . . . . . . . . . . . . . . 22
Table 12. Model-Specific Registers Supported by Model 8/[F:8]. . 23
Table 13. Extended Feature Enable Register (EFER)
Definition (Model 8/[F:8]) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Write Ordering and Performance Settings for EFER
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. WC/UC Memory Type for UWCCR Register . . . . . . . . . . 31
Table 16. Valid Masks and Range Sizes for UWCCR Register. . . . 32
Table 17. Processor-to-Bus Clock Ratios (Models 8/[F:8] and 9) . . 35

xList of Tables
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0—November 2000
Preliminary Information
Table 18. Processor-to-Bus Clock Ratios
(Model Standard-Power D) . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Model-Specific Registers Supported by Model 9 . . . . . . 38
Table 20. Extended Feature Enable Register (EFER) Definition
(Models 9 and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 21. Tag versus Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Model-Specific Registers Supported by Model D . . . . . . 45
Table 23. Processor-to-Bus Clock Ratios (Low-Power Model D) . . . 47
Table 24. Tag versus Data Selector (same as Table 21). . . . . . . . . . 51
Table 25. Enhanced Power Management Register (EPMR)
Definition (Low-Power Model D) . . . . . . . . . . . . . . . . . . . 54
Table 26. EPM 16-Byte I/O Block Definition (Low-Power Model D) 55
Table 27. Bus Divisor and Voltage ID Control (BVC) Definition
(Low-Power Model D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 28. CPUID Functions in AMD-K6™ Processors. . . . . . . . . . . 60
Table 29. Processor Signatures for AMD-K6™ Processors . . . . . . . 62
Table 30. Standard and Extended Feature Bits . . . . . . . . . . . . . . . . 63
Table 31. Standard Feature Flag Descriptions. . . . . . . . . . . . . . . . . 74
Table 32. Extended Feature Flag Descriptions . . . . . . . . . . . . . . . . 76
Table 33. EBX Format Returned by Function 8000_0005h. . . . . . . 78
Table 34. ECX Format Returned by Function 8000_0005h. . . . . . . 78
Table 35. EDX Format Returned by Function 8000_0005h . . . . . . 78
Table 36. ECX Format Returned by Function 8000_0006h. . . . . . . 79
Table 37. EDX Format Returned by Function 8000_0007h . . . . . . 79
Table 38. Associativity Values for L2 Cache . . . . . . . . . . . . . . . . . . 80
Table 39. CPUID Values Returned by AMD-K6™ Processors . . . . 81