AMD AX1800DMT3C - Athlon XP 1.53 GHz Processor User manual

Preliminary Information
AMD Athlon XP
Processor Model 6
Data Sheet
Publication # 24309 Rev: E
Issue Date: March 2002
TM

Preliminary Information
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, 3DNow!, and QuantiSpeed
are trademarks of Advanced Micro Devices, Inc.
HyperTransport is a trademark of the HyperTransport Technology Consortium.
MMX is a trademark of Intel Corporation.
Windows is a trademark of Microsoft Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
© 2000–2002 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
tion in which the failure of AMD’s product could create a situation where per-
sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.

Table of Contents iii
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 QuantiSpeed™ Architecture Summary . . . . . . . . . . . . . . . . . . 2
2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6
3 Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 13
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 26
7.4 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 27
7.5 VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 27
7.6 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7 VCC_CORE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.8 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.9 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 31
7.10 SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 32
7.11 AMD Athlon System Bus AC and DC Characteristics . . . . . 34
7.12 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 36
7.13 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.14 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
7.15 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 41

iv Table of Contents
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information
8 Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 43
8.1 Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Signal Sequence and Timing Description . . . . . . . . . . . . . 43
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 46
8.2 Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 46
Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3 OPGA Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 51
10.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . 68
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . 68
CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 68
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . 69
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 69
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . 71
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . 72
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . 73

Table of Contents v
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
11 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Standard AMD Athlon XP Processor Model 6 Products . . . . . . . . . . 75
Appendix A Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 77
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

vi Table of Contents
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information

List of Figures vii
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
List of Figures
Figure 1. Typical AMD Athlon™ XP Processor Model 6 System
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. AMD Athlon XP Processor Model 6 Power Management
States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. AMD Athlon System Bus Disconnect Sequence in the
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence . . . . 16
Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. VCC_CORE Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 32
Figure 10. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. General ATE Open Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 38
Figure 12. Signal Relationship Requirements During Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 13. AMD Athlon XP Processor Model 6 OPGA Package . . . . . . . . 49
Figure 14. AMD Athlon XP Processor Model 6 Pin Diagram—
Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 15. AMD Athlon XP Processor Model 6 Pin Diagram—
Bottomside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 16. OPN Example for the AMD Athlon XP Processor
Model 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

viii List of Figures
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information

List of Tables ix
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
List of Tables
Table 1. Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . . . 28
Table 7. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 32
Table 10. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 33
Table 11. AMD Athlon™ System Bus DC Characteristics . . . . . . . . . . . . 34
Table 12. AMD Athlon System Bus AC Characteristics . . . . . . . . . . . . . . 35
Table 13. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 39
Table 15. Guidelines for Platform Thermal Protection of the
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 41
Table 17. Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 18. Dimensions for the AMD Athlon XP Processor
Model 6 OPGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 20. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 21. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 70
Table 22. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 74
Table 23. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 24. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

xList of Tables
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information

Revision History xi
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
Revision History
Date Rev Description
March 2002 E
Revisions to the AMD Athlon™ XP Processor Model 6 Data Sheet since January 2002 include
the following:
■ In Chapter 6, revised Table 1, “Thermal Design Power,” on page 23
■ In Chapter 7, revised Table 8, “VCC_CORE Voltage and Current,” on page 31
■ In Chapter 10, revised Table , “FID[3:0] Pins,” on page 70
■ In Chapter 11, revised Figure 16, “OPN Example for the AMD Athlon™ XP Processor Model 6’
on page 75
January 2002 D
Revisions to the AMD Athlon™ XP Processor Model 6 Data Sheet since November 2001 include
the following:
■ In Chapter 6, revised Table 1, “Thermal Design Power,” on page 23
■ In Chapter 7, revised Table 8, “VCC_CORE Voltage and Current,” on page 31
■ In Chapter 11, revised Figure 16, “OPN Example for the AMD Athlon™ XP Processor Model 6’
on page 75
November 2001 C
Revisions to the AMD Athlon™ XP Processor Model 6 Data Sheet since October 2001 include
the following:
■ In Chapter 6, revised Table 1, “Thermal Design Power,” on page 23
■ In Chapter 7, revised Table 6, “VCC_CORE AC and DC Characteristics,” on page 28, Table 8,
“VCC_CORE Voltage and Current,” on page 31, revised Table 13, “General AC and DC
Characteristics,” on page 36, added new section, “Open Drain Test Circuit” on page 38, added
Figure 11, “General ATE Open Drain Test Circuit’ on page 38, added new section, “Thermal
Protection Characterization” on page 40 , and added Table 15, “Guidelines for Platform
Thermal Protection of the Processor,” on page 41
■ In Chapter 11, revised Figure 16, “OPN Example for the AMD Athlon™ XP Processor Model 6’
on page 75
October 2001 B Initial release of the AMD Athlon™ XP Processor Model 6 Data Sheet

xii Revision History
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information

Chapter 1 Overview 1
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
1 Overview
The AMD Athlon™ XP processor model 6 with QuantiSpeed™
architecture powers the next generation in computing platforms,
delivering extreme performance for Windows™ XP.
The AMD Athlon™ XP processor model 6 is the latest member
of the AMD Athlon family of processors designed to meet the
computation-intensive requirements of cutting-edge software
applications running on high-performance desktop systems.
Delivered in an OPGA package, the AMD Athlon XP processor
model 6 delivers the integer, floating-point, and 3D multimedia
performance needed for highly demanding applications running
on x86 system platforms. The AMD Athlon XP processor model 6
delivers compelling performance for cutting-edge software
applications that include high-speed Internet capability, digital
content creation, digital photo editing, digital video, image
compression, video encoding for streaming over the Internet,
soft DVD, commercial 3D modeling, workstation-class
Computer-Aided Design (CAD), commercial desktop publishing,
and speech recognition. The AMD Athlon XP processor model 6
also offers the scalability and reliability that IT managers and
business users require for enterprise computing.
The AMD Athlon XP processor model 6 features a
seventh-generation microarchitecture with an integrated,
exclusive L2 cache, which supports the growing processor and
system bandwidth requirements of emerging software, graphics,
I/O, and memory technologies. The high-speed execution core of
the AMD Athlon XP processor model 6 includes multiple x86
instruction decoders, a dual-ported 128-Kbyte split level-one
(L1) cache, an exclusive 256-Kbyte L2 cache, three independent
integer pipelines, three address calculation pipelines, and a
superscalar, fully pipelined, out-of-order, three-way
floating-point engine. The floating-point engine is capable of
delivering outstanding performance on numerically complex
applications.
The features of the AMD Athlon XP processor model 6 are
QuantiSpeed™ architecture, a high-performance full-speed
cache, a 266-MHz, 2.1-Gigabyte per second system bus, and
3DNow!™ Professional technology. The AMD Athlon system
bus combines the latest technological advances, such as
point-to-point topology, source-synchronous packet-based
transfers, and low-voltage signaling to provide an extremely
powerful, scalable bus for an x86 processor.

2Overview Chapter 1
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information
The AMD Athlon XP processor model 6 is binary-compatible
with existing x86 software and backwards compatible with
applications optimized for MMX™, SSE, and 3DNow!
technology. Using a data format and Single-Instruction
Multiple-Data (SIMD) operations based on the MMX
instruction model, the AMD Athlon XP processor model 6 can
produce as many as four, 32-bit, single-precision floating-point
results per clock cycle. The 3DNow! Professional technology
implemented in the AMD Athlon XP processor model 6
includes new integer multimedia instructions and
software-directed data movement instructions for optimizing
such applications as digital content creation and streaming
video for the internet, as well as new instructions for Digital
Signal Processing (DSP)/communications applications.
1.1 QuantiSpeed™ Architecture Summary
The following features summarize the AMD Athlon XP
processor model 6 QuantiSpeed architecture:
■An advanced nine-issue, superpipelined, superscalar x86
processor microarchitecture designed for increased
Instructions Per Cycle (IPC) and high clock frequencies
■Fully pipelined floating-point unit that executes all x87
(floating-point), MMX,SSE and 3DNow! instructions
■Hardware data pre-fetch that increases and optimizes
performance on high-end software applications utilizing
high-bandwidth system capabilities
■Advanced two-level Translation Look-aside Buffer (TLB)
structures for both enhanced data and instruction address
translation. The AMD Athlon XP processor model 6 with
QuantiSpeed architecture incorporates three TLB
optimizations: the L1 DTLB increases from 32 to 40 entries,
the L2 ITLB and L2 DTLB both use exclusive architecture,
and the TLB entries can be speculatively loaded.
The AMD Athlon XP processor model 6 delivers excellent
system performance in a cost-effective, industry-standard form
factor. The AMD Athlon processor model 6 is compatible with
motherboards based on Socket A.
Figure 1 on page 3 shows a typical AMD Athlon processor
system block diagram.

Chapter 1 Overview 3
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
Figure 1. Typical AMD Athlon™ XP Processor Model 6 System Block Diagram
SDRAM or DDR
AGP Bus
Memory Bus
AGP
PCI Bus
LAN SCSI
LPC Bus
USB
Dual EIDE
AMD Athlon™ XP
Processor Model 6
System Controller
(Northbridge)
Peripheral Bus
Controller
(Southbridge)
Modem / Audio
Thermal Monitor
BIOS
AMD Athlon System Bus

4Overview Chapter 1
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information

Chapter 2 Interface Signals 5
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
2 Interface Signals
2.1 Overview
The AMD Athlon™ system bus architecture is designed to
deliver excellent data movement bandwidth for next-
generation x86 platforms as well as the high-performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 64-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Athlon™ System Bus Signals”
on page 6, Chapter 10, “Pin Descriptions” on page 51, and the
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
2.2 Signaling Technology
The AMD Athlon system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (VREF). The reference signal is used by the receivers to
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
“Pin Descriptions” on page 51.

6Interface Signals Chapter 2
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information
2.3 Push-Pull (PP) Drivers
The AMD Athlon XP processor model 6 supports Push-Pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
See “ZN and ZP Pins” on page 74 for more information.
2.4 AMD Athlon™ System Bus Signals
The AMD Athlon system bus is a clock-forwarded, point-to-
point interface with the following three point-to-point channels:
■A 13-bit unidirectional output address/command channel
■A 13-bit unidirectional input address/command channel
■A 72-bit bidirectional data channel
For more information, see Chapter 7, “Electrical Data” on page
25 and the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902.

Chapter 3 Logic Symbol Diagram 7
24309E—March 2002 AMD Athlon™ XP Processor Model 6 Data Sheet
Preliminary Information
3 Logic Symbol Diagram
Figure 2 is the logic symbol diagram of the processor. This
diagram shows the logical grouping of the input and output
signals.
Figure 2. Logic Symbol Diagram
SDATA[63:0]#
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]#
Data
SADDIN[14:2]#
SADDINCLK#
Probe/SysCMD
SADDOUT[14:2]#
SADDOUTCLK#
VID[4:0]
FID[3:0]
A20M#
CLKFWDRST
CONNECT
COREFB
COREFB#
FERR
IGNNE#
INIT#
INTR
NMI
PROCRDY
PWROK
RESET#
SFILLVALID#
SMI#
STPCLK#
SYSCLK#SYSCLK
Clock
Voltage
Control
Frequency
Control
Legacy
Request
AMD Athlon™ XP
Processor Model 6
SDATAINVALID#
SDATAOUTVALID#
Power
and Initialization
Management Thermal
Diode
THERMDA
THERMDC
FLUSH#
PICCLK
PICD[1:0] APIC

8Logic Symbol Diagram Chapter 3
AMD Athlon™ XP Processor Model 6 Data Sheet 24309E—March 2002
Preliminary Information