AMD Athlon Processor x86 User manual

AMD Athlon Processor
x86 Code Optimization
Guide
TM

Trademarks
AMD, the AMD logo, AMD Athlon, K6, 3DNow!, and combinations thereof, K86, and Super7 are trademarks,
and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc.
Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
MMX is a trademark and Pentium is a registered trademark of Intel Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
© 1999 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
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is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
tion in which the failure of AMD’s product could create a situation where per-
sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.

Contents iii
22007E/0—November 1999 AMD Athlon™ Processor x86 Code Optimization
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
1 Introduction 1
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
AMD Athlon™Processor Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
AMD Athlon Processor Microarchitecture Summary . . . . . . . . . . . . . 4
2 Top Optimizations 7
Optimization Star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Group I Optimizations —Essential Optimizations . . . . . . . . . . . . . . . 8
Memory Size and Alignment Issues . . . . . . . . . . . . . . . . . . . . . . 8
Use the 3DNow!™PREFETCH and PREFETCHW
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Select DirectPath Over VectorPath Instructions . . . . . . . . . . . 9
Group II Optimizations—Secondary Optimizations . . . . . . . . . . . . . . 9
Load-Execute Instruction Usage. . . . . . . . . . . . . . . . . . . . . . . . . 9
Take Advantage of Write Combining. . . . . . . . . . . . . . . . . . . . 10
Use 3DNow! Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Avoid Branches Dependent on Random Data . . . . . . . . . . . . . 10
Avoid Placing Code and Data in the Same
64-Byte Cache Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 C Source Level Optimizations 13
Ensure Floating-Point Variables and Expressions
are of Type Float. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Use 32-Bit Data Types for Integer Code . . . . . . . . . . . . . . . . . . . . . . . 13
Consider the Sign of Integer Operands . . . . . . . . . . . . . . . . . . . . . . . 14
Use Array Style Instead of Pointer Style Code . . . . . . . . . . . . . . . . . 15
Completely Unroll Small Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Avoid Unnecessary Store-to-Load Dependencies . . . . . . . . . . . . . . . 18
Consider Expression Order in Compound Branch Conditions . . . . . 20

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AMD Athlon™Processor x86 Code Optimization 22007E/0—November 1999
Switch Statement Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Optimize Switch Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Use Prototypes for All Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Use Const Type Qualifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Generic Loop Hoisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Generalization for Multiple Constant Control Code. . . . . . . . 23
Declare Local Functions as Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Dynamic Memory Allocation Consideration . . . . . . . . . . . . . . . . . . . 25
Introduce Explicit Parallelism into Code . . . . . . . . . . . . . . . . . . . . . . 25
Explicitly Extract Common Subexpressions . . . . . . . . . . . . . . . . . . . 26
C Language Structure Component Considerations . . . . . . . . . . . . . . 27
Sort Local Variables According to Base Type Size . . . . . . . . . . . . . . 28
Accelerating Floating-Point Divides and Square Roots . . . . . . . . . . 29
Avoid Unnecessary Integer Division. . . . . . . . . . . . . . . . . . . . . . . . . . 31
Copy Frequently De-referenced Pointer Arguments to
Local Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Instruction Decoding Optimizations 33
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Select DirectPath Over VectorPath Instructions. . . . . . . . . . . . . . . . 34
Load-Execute Instruction Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Use Load-Execute Integer Instructions . . . . . . . . . . . . . . . . . . 34
Use Load-Execute Floating-Point Instructions with
Floating-Point Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Avoid Load-Execute Floating-Point Instructions with
Integer Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Align Branch Targets in Program Hot Spots . . . . . . . . . . . . . . . . . . . 36
Use Short Instruction Lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Avoid Partial Register Reads and Writes. . . . . . . . . . . . . . . . . . . . . . 37
Replace Certain SHLD Instructions with Alternative Code. . . . . . . 38
Use 8-Bit Sign-Extended Immediates . . . . . . . . . . . . . . . . . . . . . . . . . 38

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22007E/0—November 1999 AMD Athlon™Processor x86 Code Optimization
Use 8-Bit Sign-Extended Displacements. . . . . . . . . . . . . . . . . . . . . . . 39
Code Padding Using Neutral Code Fillers . . . . . . . . . . . . . . . . . . . . . 39
Recommendations for the AMD Athlon Processor . . . . . . . . . 40
Recommendations for AMD-K6®Family and
AMD Athlon Processor Blended Code . . . . . . . . . . . . . . . . . . . 41
5 Cache and Memory Optimizations 45
Memory Size and Alignment Issues . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Avoid Memory Size Mismatches. . . . . . . . . . . . . . . . . . . . . . . . 45
Align Data Where Possible . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Use the 3DNow! PREFETCH and PREFETCHW Instructions. . . . . 46
Take Advantage of Write Combining . . . . . . . . . . . . . . . . . . . . . . . . . 50
Avoid Placing Code and Data in the Same 64-Byte Cache Line. . . . 50
Store-to-Load Forwarding Restrictions. . . . . . . . . . . . . . . . . . . . . . . . 51
Store-to-Load Forwarding Pitfalls—True Dependencies. . . . 51
Summary of Store-to-Load Forwarding Pitfalls to Avoid. . . . 54
Stack Alignment Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Align TBYTE Variables on Quadword Aligned Addresses. . . . . . . . 55
C Language Structure Component Considerations . . . . . . . . . . . . . . 55
Sort Variables According to Base Type Size . . . . . . . . . . . . . . . . . . . 56
6 Branch Optimizations 57
Avoid Branches Dependent on Random Data . . . . . . . . . . . . . . . . . . 57
AMD Athlon Processor Specific Code . . . . . . . . . . . . . . . . . . . 58
Blended AMD-K6 and AMD Athlon Processor Code . . . . . . . 58
Always Pair CALL and RETURN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Replace Branches with Computation in 3DNow! Code . . . . . . . . . . . 60
Muxing Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Sample Code Translated into 3DNow! Code . . . . . . . . . . . . . . 61
Avoid the Loop Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Avoid Far Control Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . 65
Avoid Recursive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

vi Contents
AMD Athlon™Processor x86 Code Optimization 22007E/0—November 1999
7 Scheduling Optimizations 67
Schedule Instructions According to their Latency . . . . . . . . . . . . . . 67
Unrolling Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Complete Loop Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Partial Loop Unrolling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Use Function Inlining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Always Inline Functions if Called from One Site . . . . . . . . . . 72
Always Inline Functions with Fewer than 25 Machine
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Avoid Address Generation Interlocks. . . . . . . . . . . . . . . . . . . . . . . . . 72
Use MOVZX and MOVSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Minimize Pointer Arithmetic in Loops . . . . . . . . . . . . . . . . . . . . . . . . 73
Push Memory Data Carefully. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8 Integer Optimizations 77
Replace Divides with Multiplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Multiplication by Reciprocal (Division) Utility . . . . . . . . . . . 77
Unsigned Division by Multiplication of Constant. . . . . . . . . . 78
Signed Division by Multiplication of Constant . . . . . . . . . . . . 79
Use Alternative Code When Multiplying by a Constant. . . . . . . . . . 81
Use MMX™Instructions for Integer-Only Work . . . . . . . . . . . . . . . . 83
Repeated String Instruction Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Latency of Repeated String Instructions. . . . . . . . . . . . . . . . . 84
Guidelines for Repeated String Instructions . . . . . . . . . . . . . 84
Use XOR Instruction to Clear Integer Registers . . . . . . . . . . . . . . . . 86
Efficient 64-Bit Integer Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Efficient Implementation of Population Count Function. . . . . . . . . 91
Derivation of Multiplier Used for Integer Division
by Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Unsigned Derivation for Algorithm, Multiplier, and
Shift Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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22007E/0—November 1999 AMD Athlon™Processor x86 Code Optimization
Signed Derivation for Algorithm, Multiplier, and
Shift Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9 Floating-Point Optimizations 97
Ensure All FPU Data is Aligned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Use Multiplies Rather than Divides . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Use FFREEP Macro to Pop One Register from the FPU Stack . . . . 98
Floating-Point Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 98
Use the FXCH Instruction Rather than FST/FLD Pairs . . . . . . . . . . 99
Avoid Using Extended-Precision Data . . . . . . . . . . . . . . . . . . . . . . . . 99
Minimize Floating-Point-to-Integer Conversions . . . . . . . . . . . . . . . 100
Floating-Point Subexpression Elimination. . . . . . . . . . . . . . . . . . . . 103
Check Argument Range of Trigonometric Instructions
Efficiently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Take Advantage of the FSINCOS Instruction . . . . . . . . . . . . . . . . . 105
10 3DNow!™ and MMX™ Optimizations 107
Use 3DNow! Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Use FEMMS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Use 3DNow! Instructions for Fast Division . . . . . . . . . . . . . . . . . . . 108
Optimized 14-Bit Precision Divide . . . . . . . . . . . . . . . . . . . . . 108
Optimized Full 24-Bit Precision Divide . . . . . . . . . . . . . . . . . 108
Pipelined Pair of 24-Bit Precision Divides. . . . . . . . . . . . . . . 109
Newton-Raphson Reciprocal. . . . . . . . . . . . . . . . . . . . . . . . . . 109
Use 3DNow! Instructions for Fast Square Root and
Reciprocal Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Optimized 15-Bit Precision Square Root . . . . . . . . . . . . . . . . 110
Optimized 24-Bit Precision Square Root . . . . . . . . . . . . . . . . 110
Newton-Raphson Reciprocal Square Root. . . . . . . . . . . . . . . 111
Use MMX PMADDWD Instruction to Perform
Two 32-Bit Multiplies in Parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3DNow! and MMX Intra-Operand Swapping . . . . . . . . . . . . . . . . . . 112

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AMD Athlon™Processor x86 Code Optimization 22007E/0—November 1999
Fast Conversion of Signed Words to Floating-Point . . . . . . . . . . . . 113
Use MMX PXOR to Negate 3DNow! Data . . . . . . . . . . . . . . . . . . . . 113
Use MMX PCMP Instead of 3DNow! PFCMP. . . . . . . . . . . . . . . . . . 114
Use MMX Instructions for Block Copies and Block Fills . . . . . . . . 115
Use MMX PXOR to Clear All Bits in an MMX Register . . . . . . . . . 118
Use MMX PCMPEQD to Set All Bits in an MMX Register. . . . . . . 119
Use MMX PAND to Find Absolute Value in 3DNow! Code . . . . . . 119
Optimized Matrix Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Efficient 3D-Clipping Code Computation Using
3DNow! Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Use 3DNow! PAVGUSB for MPEG-2 Motion Compensation . . . . . 123
Stream of Packed Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Complex Number Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11 General x86 Optimization Guidelines 127
Short Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Register Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Stack Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Appendix A AMD Athlon™Processor Microarchitecture 129
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
AMD Athlon Processor Microarchitecture . . . . . . . . . . . . . . . . . . . . 130
Superscalar Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Branch Prediction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Early Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Instruction Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Integer Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Contents ix
22007E/0—November 1999 AMD Athlon™Processor x86 Code Optimization
Integer Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Floating-Point Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . 137
Load-Store Unit (LSU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
L2 Cache Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Write Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
AMD Athlon System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Appendix B Pipeline and Execution Unit Resources Overview 141
Fetch and Decode Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Integer Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Floating-Point Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Execution Unit Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Integer Pipeline Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Floating-Point Pipeline Operations . . . . . . . . . . . . . . . . . . . . 150
Load/Store Pipeline Operations . . . . . . . . . . . . . . . . . . . . . . . 151
Code Sample Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Appendix C Implementation of Write Combining 155
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Write-Combining Definitions and Abbreviations . . . . . . . . . . . . . . 156
What is Write Combining? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Write-Combining Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Sending Write-Buffer Data to the System . . . . . . . . . . . . . . . 159
Appendix D Performance-Monitoring Counters 161
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Performance Counter Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
PerfEvtSel[3:0] MSRs
(MSR Addresses C001_0000h–C001_0003h) . . . . . . . . . . . . . 162

xContents
AMD Athlon™Processor x86 Code Optimization 22007E/0—November 1999
PerfCtr[3:0] MSRs
(MSR Addresses C001_0004h–C001_0007h) . . . . . . . . . . . . . 167
Starting and Stopping the Performance-Monitoring
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Event and Time-Stamp Monitoring Software. . . . . . . . . . . . . . . . . . 168
Monitoring Counter Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Appendix E Programming the MTRR and PAT 171
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Memory Type Range Register (MTRR) Mechanism . . . . . . . . . . . . 171
Page Attribute Table (PAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Appendix F Instruction Dispatch and Execution Resources 187
Appendix G DirectPath versus VectorPath Instructions 219
Select DirectPath Over VectorPath Instructions. . . . . . . . . . . . . . . 219
DirectPath Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
VectorPath Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237