AMD Xilinx ZCU670 User manual

ZCU670 Evaluaon Board
User Guide
UG1532 (v1.0) March 30, 2022
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Overview.......................................................................................................................................4
Additional Resources.................................................................................................................. 4
Block Diagram..............................................................................................................................5
Board Features............................................................................................................................ 5
Board Specifications....................................................................................................................8
Chapter 2: Board Setup and Configuration....................................................10
Standard ESD Measures........................................................................................................... 10
Board Component Location.....................................................................................................10
Default Jumper and Switch Settings....................................................................................... 14
Zynq UltraScale+ RFSoC XCZU67DR........................................................................................ 18
Chapter 3: Board Component Descriptions................................................... 20
Overview.....................................................................................................................................20
Component Descriptions......................................................................................................... 20
Appendix A: VITA57.4 FMCP Connector Pinout............................................ 63
Appendix B: Xilinx Design Constraints............................................................. 64
Overview.....................................................................................................................................64
Appendix C: Regulatory and Compliance Information........................... 65
CE Information...........................................................................................................................65
Compliance Markings............................................................................................................... 66
Appendix D: HW-XM650/755 Balun Daughter Cards for RFSoC
EVM...................................................................................................................................67
Overview.....................................................................................................................................67
Block Diagram........................................................................................................................... 68
Connector...................................................................................................................................69
XM650/755 Connector Pinouts................................................................................................ 71
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CoreHC2 Connector Pin Out (XM755 Only)............................................................................76
Features......................................................................................................................................77
Board Specifications................................................................................................................. 79
Functional Description..............................................................................................................82
Appendix E: Additional Resources and Legal Notices..............................92
Xilinx Resources.........................................................................................................................92
Documentation Navigator and Design Hubs.........................................................................92
References..................................................................................................................................92
Revision History.........................................................................................................................94
Please Read: Important Legal Notices................................................................................... 94
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Chapter 1
Introduction
Overview
The ZCU670 is an evaluaon board featuring the ZU67DR Zynq® UltraScale+™ RFSoC DFE
device. This board enables the evaluaon of applicaons requiring mul-band (sub-7 GHz,
mmWave), mul-std (5G, LTE, etc.), and mul-mode (TDD, FDD) radios, including Milcom and
Satcom applicaons. The ZCU670 board is equipped with all the common board-level features
needed for design development, such as DDR4 memory, networking interfaces, an FMC+
expansion port, as well as access to the RFMC 2.0 interface.
Additional Resources
See Appendix E: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the ZCU670 evaluaon board.
Chapter 1: Introduction
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Block Diagram
A block diagram of the ZCU670 evaluaon board is shown in the following gure.
Figure 1: Evaluation Board Block Diagram
PS DDR4 SODIMM
64-bit
USB3.0
FMCP_HSPC_DP[4:6]
SFP[0:3]
FMCP_HSPC_DP[0:3]
SD3.0
PS_PMU_GPO[0:5]
PMU_INPUT
PS_GPIO1
SFP TX_DISABLE
USB3.0
ETHERNET RGMII
CONFIG.IF
JTAG IF
UART2
MSP430_UCA1
PL DDR4 Component
32-bit (4x8-bit)
SI538_PL_CLK
300MHz CLK
ADCIO x8
DACIO x8
8A34001 CLK in x1
Si5381 CLKO x1
Si5381 CLKinx1
ADCIO x8
DACIO x8
CLK104_SPI_MUX_SEL
TDD SMA x1
CPU_RESET
MPS430_GPIO
8A34001 CLKO x1
8A34001 CLKinx1
Si5381 CLKO x1
CLK104_PL_CLK
TDD SMA x1
PB/LEDs/CLK MUX SEL
SYSMON_I2C
PS PB/LED
UART0
PS_I2C0
PS_I2C1
QSPI_UPR
QSPI_LWR
PS_GPIO2
RFMC2.0 CON1
ADC_T1_CH0~CH3
ADC_T2_CH01/CH23
ADC_T0_CH0~CH3
RFMC2.0 CON2
DAC_T1_CH0~CH3
DAC_T0_CH0~CH3
X25678-111521
Board Features
The ZCU670 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• ZU67DR-2, FSVE1156 package
• Form factor: see Board Specicaons
•Conguraon from:
○Dual QSPI
Chapter 1: Introduction
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○Micro-SD card
○USB-to-JTAG bridge
○PC4 2x7 2 mm JTAG pod at cable header
• Clocks
○SI5381 (various frequencies)
For addional details on this clock, see Table 17, Table 18, and SI5381A 10 Independent
Output Any-Frequency Clock Generator U43.
○CLK104 (various frequencies):
Oponal for DFE. Contact factory for availability.
- CLK104_PL_CLK
- CLK104_PL_SYSREF
- CLK104_AMS_SYSREF
- CLK104_DAC_REFCLK (direct connect SSMP)
○8A34001 IEEE 1588, Synchronous Ethernet (SyncE), and eCPRI clock (various frequencies)
For addional details on this clock, see Table 17, Table 18, and SI5381A 10 Independent
Output Any-Frequency Clock Generator U43.
○PS_REF_CLK 33.333333...(33 + 1/3 MHz)
○ADC_CLK_226 (direct connect SSMP)
For addional details on this clock, see Table 17, Table 18, and Programmable User SI570
Clocks.
○DAC_CLK_228 (direct connect SSMP)
○USER_MGT_SI570 (default 156.25 MHz)
For addional details on this clock, see Table 17, Table 18, and Programmable User SI570
Clocks.
○USER_SI570_C0 (default 300 MHz)
For addional details on this clock, see Table 17, Table 18, and Programmable User SI570
Clocks.
○User SMA clocks
For more informaon, see User SMA Clocks.
• PS DDR4 4 GB 64-bit SODIMM
• PL DDR4 C0 I/F 2 GB 32-bit component (4x8-bit)
Chapter 1: Introduction
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• PS GTR (bank 505) assignment
○USB3 (1 GTR)
○FMCP HSPC DP (3 GTR)
• PL GTY assignment (2 quads, 8 total GTY)
○2x2 zSFP+ (4 GTY on bank GTY127)
○FMCP HSPC DP (4 GTY, bank GTY128)
• PS MIO connecvity
○PS MIO[0:5, 7:12]: dual QSPI
○PS MIO[13]: PS_GPIO2
○PS MIO[14:17]: 2 channels of I2C
○PS MIO[18:19]: UART0 (1 of 3 FT4232 UART channels)
○PS MIO[22:23]: PS_PB, PS_LED I/F
○PS MIO[26]: PMU_INPUT
○PS MIO[27:30]: SFP[0:3] TX_DISABLE
○PS MIO[32:37]: PMU_GPO[0:5]
○PS MIO[38]: PS_GPIO1
○PS MIO[39:43, 45:51]: SD I/F
○PS MIO[52:63]: USB3.0
○PS MIO[64:77]: Ethernet RGMII
• PL I/O connecons
○PL user GPIO pushbuon
○PL CPU reset pushbuon
○PL user GPIO LEDs (4)
• Security—PSBATT buon baery backup
• SYSMON header
•Operaonal switches (power on/o, PS_PROG_B, boot mode DIP switch)
•Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System controller (MSP430)
Chapter 1: Introduction
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The ZCU670 provides a rapid prototyping plaorm that uses the XCZU67DR-2FSVE1156I
device. The ZU67DR contains many useful processor system (PS) hard block peripherals exposed
through the mul-use I/O (MIO) interface and a variety of FPGA programmable logic. The
following table lists a brief summary of the resources available within the ZU67DR.
Feature set overview, descripon, and ordering informaon is provided in the Zynq UltraScale+
RFSoC DFE Data Sheet: Overview (DS883).
Table 1: Zynq UltraScale+ RFSoC ZU67DR Features and Resources
Feature Resource Count
Digital front end Included
14-bit 2.95 GSPS RF-ADC with DDC 8
14-bit 5.9 GSPS ADC RF-DAC with DDC 2
14-bit 10 GSPS RF-DAC with DUC 8
APU: Quad-core Arm® Cortex®-A53 MPCore with CoreSight™ 1
RTPU: Dual-core Arm Cortex-R5F MPCore with CoreSight 1
HD I/O 96
HP I/O 312
MIO banks 3 banks, total of 78 pins
PS GTR 6 Gb/s transceivers 4 PS-GTRs
PL GTY 28 Gb/s transceivers 8 GTYs
System logic cells 489,300
CLB flip-flops 447,360
CLB LUTs 223,680
Maximum distributed RAM (Mb) 6.9
Block RAM blocks 648
UltraRAM blocks 160
DSP slices 1,872
100G Ethernet with RS-FEC 1
Board Specifications
Dimensions
Height: 12.225 inches (31.05 cm)
Width: 10.675 inches (27.11 cm)
Thickness: 0.122 inches (0.310 cm)
Note: A 3D model of this board is not available.
Chapter 1: Introduction
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See the ZCU670 Evaluaon Board website for the XDC lisng and board schemacs.
Environmental
Note: The operang temperature range is not fully tested across the specied temperature range. It is for
general guidelines only. Customers should use the ZCU670 evaluaon board for evaluaon purposes only
in a normal lab environment and should not operate beyond room temperature.
•Temperature:
Operang: 0°C to +45°C
Storage: –25°C to +60°C
•Humidity: 5% to 95% non-condensing
Operating Voltage
+12 VDC
Chapter 1: Introduction
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Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in
total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
•Aach a wrist strap to an unpainted metal surface of your hardware to prevent electrostac
discharge from damaging your hardware.
• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for
stac control. It does not increase or decrease your risk of receiving electric shock when you
are using or working on electrical equipment.
• If you do not have a wrist strap, before you remove the product from ESD packaging and
installing or replacing hardware, touch an unpainted metal surface of the system for a
minimum of ve seconds.
• Do not remove the device from the anstac bag unl you are ready to install the device in
the system.
• With the device sll in its anstac bag, touch it to the metal frame of the system.
• Grasp cards and boards by the edges. Avoid touching the components and gold connectors on
the adapter.
• If you need to lay the device down while it is out of the anstac bag, lay it on the anstac
bag. Before you pick it up again, touch the anstac bag and the metal frame of the system at
the same me.
• Handle the devices carefully to prevent permanent damage.
Board Component Location
The following gure shows the ZCU670 board component locaons. Each numbered component
shown in the gure is keyed to Table 2.
Chapter 2: Board Setup and Configuration
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IMPORTANT! The following gure is for visual reference only and might not reect the current revision of
the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be a
reference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic ZCU670 version of interest for such details.
Figure 2: ZCU670 Component Locations
1
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
35
27
42
45
13
15
43 28
12
16
33
7
25
36
30
5
8
47
26
3
37
38
39
40
9
10
41
29
44
2
14
17
34
18
19
21
20
22
23
24
26
46
48
6
4
11
31
X25693-100421
Chapter 2: Board Setup and Configuration
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Board Component Descriptions
The following table idenes the components and references the respecve schemac
(038-05023-01) page numbers.
Table 2: ZCU670 Board Component Locations
Callout Ref.
Des.
Feature
[B]=Bottom Notes Schematic
Page
1 U1 Zynq® UltraScale+™ RFSoC fansink XCZU67DR-FFVE115 Ironwood P/N:
C19450
2 J48 DDR4 SODIMM socket with 64-bit DDR4
SODIMM
LOTES ADDR0067-P001A with MICRON
MTA4ATF51264HZ-2G6E1
Note: J48 is bottomside.
40
3 U96-U99 DDR4 C0 4x8-bit clamshell component
memory (4 GB)
Micron MT40A1G8SA-075
Note: U96 and U97 are bottomside.
65-68
4 U130 (C1) User PS ref. clock, 33.333333...(33 + 1/3
MHz)
Skyworks (SiLabs) SI570JAC000900DGR 38
5 U11, U12 Dual Quad SPI flash memory (4 Gb
total)
Micron MT25QU02GCBB8E12-0SIT 21
6 U6, J18 USB 3 ULPI transceiver [B], USB Micro-
AB connector
SMSC USB3320-EZK, WURTH
692122030100
20
7 J23 SD card interface connector MOLEX 5025700893 24
8 U29, J24 Quad USB_UART, USB micro-B
connector
FTDI FT4232Hx-REEL, Hirose ZX62D-
AB-5P8(30)
25
9 J25 JTAG 2 mm 2x7 flat-cable connector Molex 87832-1420 25
10 U43 Fixed frequency clock gen. [B] Skyworks (SiLabs) SI5381A-E13960-GMR 37
11 U47 (C0) User Clock, 300 MHz, 3.3V LVDS [B] Skyworks (SiLabs) 570BAB001614DG 38
12 U48 User MGT Clock, 156.250 MHz, 3.3V LVDS Skyworks (SiLabs) 570BAB000544DG 38
U409 Various eCPRI clocks Renesas 8A34001E-000AJG8 34
13 External SFP jitter attenuated clock CLK104 module function (J101) 64
14 J101 CLK104 module connector Samtec LPAF-20-03.0-L-06-2-K-TR 64
15 J29 Quad zSFP/zSFP+ connector TE connectivity/AMP 2198325-5 33
16 U33, P1 10/100/1000 MHz Ethernet PHY, RJ45
with magnetics
TI DP83867IRPAP, Wurth 7499111221A 26
17 U17, U15 I2C0 bus switch, expander [B] TI PCA9544ARGYR, TI TCA6416APWR 22
18 U20, U22 I2C1 bus switches [B] 2 ea. TI TCA9548APWR 23
19 U38 System controller (SC) TI MSP430F5342 27
20 J24 MSP430 SC emulation cable connector TYCO 5103308-2 25
21 SW6, SW7 System controller 5-pole DIP switch and
reset PB switch
Wurth Electronics, Inc. 416131160805, E-
Switch TL3301EP100QG
27
22 SW2 FPGA MODE 4-pole DIP switch 4-pole C&K SDA04H1SBD 10
Chapter 2: Board Setup and Configuration
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Table 2: ZCU670 Board Component Locations (cont'd)
Callout Ref.
Des.
Feature
[B]=Bottom Notes Schematic
Page
23
SW8 User pushbutton switches, active-High E-switch TL3301EP100QG 42
SW13 CPU_RESET pushbutton, active-High E-switch TL3301EP100QG 42
DS54-
DS57
Four single color LEDs, active-High PL GPIO LEDs, LUMEX SML-LX0603GW-
TR
42
SW1 PS (MIO22) pushbutton E-switch TL3301EP100QG 9
SW3 PS_PROG pushbutton E-switch TL3301EP100QG 10
SW4, SW5 PS_POR_B, PS_SRST_B pushbuttons E-switch TL3301EP100QG 10
J15 2-PIN HDR PS_POR_B SULLINS PBC02SAAN 10
J16 2-PIN HDR PS_SRST_B SULLINS PBC02SAAN 10
J17 2-PIN HDR MR_B (U5 RST) SULLINS PBC02SAAN 10
24 SW15 Power ON/OFF slide switch C&K 1101M2S3AQE2 43
J50 Power connector MOLEX 39-30-1060 43
25 J28 FMCP HSPC connector Samtec ASP_184329_01 28-32
26 - Power management system (top, [B]) Infineon voltage regulators 47-58
27 J21 PMBUS connector SULLINS PBC03SAAN 22
28 J5 SYSMON 2X6 vertical male pin header SULLINS PBC06DAAN 3
29 J82 RFMC 2.0 connector 1 Samtec LPAF-50-03.0-L-08-2-K-TR 61
30 J87 RFMC 2.0 connector 2 Samtec LPAF-50-03.0-L-08-2-K-TR 62
31 J148 2-pin HDR RFSoC selection SULLINS PBC02SAAN 53
33 U50 Fan controller Maxim MAX6643LBBAEE++ 43
J57 Fan header (keyed 3-pin) Molex 22-11-2032 43
34 J6, J7 SMA 8A34001_Q5_OUT_SMA AMPHENOL 132134-15 35
35 J8, J98 ADC clock connectors CARLISLE TM14-0084-00 7
36 J99, J100 DAC clock connectors CARLISLE TM14-0084-00 8
37 U5 PWR-ON reset IC [B] Maxim MAX16025TE+ 10
38
U7 USB3 power switch Micrel MIC2544A-1YM 20
J20 USB 3.0 J18 shield header SULLINS PBC03SAAN 20
J19 VBUS_SEL option header SULLINS PBC0S2AAN 20
39 U104 INFINEON PMIC1 Infineon IR35215MTRPBF 44
40 U53 INFINEON PMIC2 Infineon IRPS5401MXI04TRP 47
41 U55 INFINEON PMIC3 Infineon IRPS5401MXI04TRP 49
42 U127 VCCINT PS/block RAM 18A regulator Infineon IR38164MTRP 50
43 U112 MGTAVCC 4A regulator Infineon IR38164MTRP 51
44 U123 VCC1V8 8A regulator Infineon IR38164MTRP 52
45 U115,
U116
ADC/DAC AVCC regulators [B] MPS MPM3683-7 53
46 U114 ADC AVCCAUX 2A regulator [B] MPS MPM3833C 54
47 U125 DAC AVCCAUX regulator [B] MPS MPM3833C 55
Chapter 2: Board Setup and Configuration
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Table 2: ZCU670 Board Component Locations (cont'd)
Callout Ref.
Des.
Feature
[B]=Bottom Notes Schematic
Page
48 U118 DAC AVTT regulator [B] MPS MPM3833C 55
Default Jumper and Switch Settings
The following gure shows the ZCU670 board jumper header and switch locaons. Each
numbered component shown in the gure is keyed to the applicable table in this secon. Both
tables reference the respecve schemac page numbers.
Chapter 2: Board Setup and Configuration
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Figure 3: Board Jumper Header and Switch Locations
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
12
5
12
3
11
7
14
4
8
X25710-091021
Chapter 2: Board Setup and Configuration
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Jumpers
The following table lists the default jumper sengs.
Table 3: Default Jumper Settings
Callout Reference
Design Function Default Schematic Page
1 J1
POR_OVERRIDE
2-3 3
1-2: Enable
2-3: Disable
2
J2
SYSMON I2C Address
ON 3
OFF: SYSMON_VP_R floating
ON: SYSMON_VP_P pulled down
J3
SYSMON I2C Address
ON 3
OFF: SYSMON_VN_R floating
ON: SYSMON_VP_N pulled down
J4
SYSMON VREFP
1-2 31-2: 1.25V VREFP connected to fpga
2-3: VREFP connected to GND
3
J15
Reset Sequencer PS_POR_B
ON 10
OFF: Sequencer does not control PS_POR_B
ON: Sequencer can control PS_POR_B
J16
Reset Sequencer PS_SRST_B
ON 10OFF: Sequencer does not control PS_SRST_B
ON: Sequencer can control PS_SRST_B
J17
Reset Sequencer inhibit
OFF 10
OFF: Sequencer normal operation
ON: Sequencer inhibit (resets will stay asserted)
4
ULPI USB3320 U6 ULPIO_VBUS_SEL option jumper
OFF 20J19 ON: Selects U17 MIC2544A switch 5V for VBUS
OFF: Normal operation, VBUS from J18 USB3.0 conn.
J20
USB 3.0 Connector J18 Shield connection options
2-3 201-2: J20 shield capacitor C171 to GND
2-3: J20 shield directly to GND
5 J22
SD3.0 U107 IP4856CX25 level-trans. ref. voltage select
1-2 24
1-2: Track SD3.0 J12 socket UTIL_3V3 3.3V
2-3: GND = revert to internal voltage reference
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Table 3: Default Jumper Settings (cont'd)
Callout Reference
Design Function Default Schematic Page
7
J39
zSFP0 J29 LT enable jumper
OFF 33
ON: zSFP0 TX_DISABLE = GND = enabled
OFF: zSFP0 TX_DISABLE = high = disabled
J44
zSFP1 J29 LL enable jumper
OFF 33
ON: zSFP1 TX_DISABLE = GND = enabled
OFF: zSFP1 TX_DISABLE = high = disabled
8
J32
zSFP2 J29 RT enable jumper
OFF 33
ON: zSFP2 TX_DISABLE = GND = enabled
OFF: zSFP2 TX_DISABLE = high = disabled
J35
zSFP3 J29 RL enable jumper
OFF 33ON: zSFP3 TX_DISABLE = GND = enabled
OFF: zSFP3 TX_DISABLE = high = disabled
31 J148
Voltage selection jumper for Zynq UltraScale+ RFSoC
ON 53
ON: ADC_AVCC=1.01V for ZU67DR device (DFE)
OFF: ADC_AVCC=0.925V for ZU47DR device (Gen3)
Switches
The following table lists the default switch sengs.
Table 4: Default Switch Settings
Callout Reference
Design Function Default Schematic Page
11 SW2
RFSoC U1 mode 4-pole DIP switch
0000 10
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW1[4:1] = Mode[3:0]
JTAG = ON,ON,ON,ON = 0000
QSPI32 = ON,ON,OFF,ON = 0010
SD = OFF,OFF,OFF,ON = 1110
12 SW6 MSP430 U38 5-pole GPIO DIP switch 11111 27
Switch OFF = 1 = High; ON = 0 = Low
14 SW15 Main power slide switch OFF 43
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the ZCU670 board power
connector J50. The ATX 6-pin connector has a dierent pinout than J50. Connecng an ATX 6-pin
connector into J50 damages the ZCU670 board and voids the board warranty.
See Power On/O Slide Switch for more informaon.
Chapter 2: Board Setup and Configuration
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Zynq UltraScale+ RFSoC XCZU67DR
Zynq UltraScale+ RFSoC ZU67DR uses a mul-stage boot process documented in the Boot and
Conguraon chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
Switch SW2 conguraon opon sengs are idened in the following table.
Table 5: Mode Switch SW2 Configuration Option Settings
Mode Mode Pins [3:0] Mode SW2 [4:1]2
JTAG 0000 ON,ON,ON,ON
QSPI32 00101ON,ON,OFF,ON
SD 1110 OFF,OFF,OFF,ON
Notes:
1. Default switch setting.
2. Switch OFF = 1 = High; ON = 0 = Low. See callout 11 in Table 4.
JTAG
Vivado® Design Suite or third-party tools can establish a JTAG connecon to the Zynq UltraScale
+ RFSoC through the FTDI FT4232 USB-to-JTAG/USB UART device (U29) connected to micro-
USB connector (J24).
QSPI
Use the following steps to boot from the dual QSPI non-volale conguraon memory.
1. Store a valid Zynq UltraScale+ RFSoC boot image into the QSPI ash devices (U11, U12,
MIO[0:12] QSPI interface).
2. Set the boot mode pins SW2 [4:1] as indicated in the table above for QSPI32.
3. Either power-cycle or press the power-on reset (POR) pushbuon. SW2 is callout 11 in
Figure 3.
SD
Use the following steps to boot from an SD card.
1. Store a valid Zynq UltraScale+ RFSoC boot image le onto an SD card (plugged into SD
socket J23) connected to the MIO[39:51] SD interface.
2. Set the boot mode pins SW3 [4:1] as indicated in the table above for SD.
3. Either power-cycle or press the power-on reset (POR) pushbuon. SW2 is callout 11 in
Figure 3.
Chapter 2: Board Setup and Configuration
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ZCU670 Board User Guide 18
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See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more informaon about
Zynq UltraScale+ RFSoC conguraon opons.
Chapter 2: Board Setup and Configuration
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 19
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a descripon of the board’s components and features. Table 2 idenes
the components and references the respecve schemac page numbers. Component locaons
are shown in Figure 2.
Component Descriptions
Zynq UltraScale+ RFSoC XCZU67DR
[Figure 2, callout 1]
The ZCU670 board is populated with the Zynq® UltraScale+™ RFSoC DFE
XCZU67DR-2FSVE1156I, which combines a powerful processing system (PS) and user-
programmable logic (PL) in the same device. The processing system in the Zynq UltraScale+
RFSoC features the Arm® agship Cortex®- A53 64-bit quad-core processor and Cortex-R5F
dual-core real-me processor.
The VCCINT supplies are user adjustable through the PMBus with the voltage ranges to support
whichever Zynq UltraScale+ RFSoC speed grade is on the evaluaon board. See the Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteriscs (DS926) for more informaon.
Top-level Block Diagram
The following gure shows the top-level block diagram for the Zynq UltraScale+ RFSoC.
Chapter 3: Board Component Descriptions
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