Analog Devices AD9739 User manual

14-Bit, 2500 MSPS,
RF Digital-to-Analog Converter
AD9739
Rev. A
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FEATURES
Dynamic performance
DOCSIS 3.0 performance
8 QAM carriers @ 400 MHz IF: −71 dBc
16 QAM carriers @ 400 MHz IF: −68 dBc
32 QAM carriers @ 400 MHz IF: −65 dBc
72 QAM carriers @ 600 MHz IF: −61 dBc
Single-carrier WCDMA ACLR performance @ 2457.6 MSPS
fOUT = 350 MHz (normal mode)
1st adjacent channel: −80 dBc
5th adjacent channel: −80.5 dBc
fOUT = 2100 MHz (mix mode)
1st adjacent channel: −69 dBc
5th adjacent channel: −75 dBc
Single-tone NSD performance @ 2.4 GSPS
−166 dBm/Hz @ 100 MHz IF
−162 dBm/Hz @ 1 GHz IF
RF synthesis support
FS mix, RZ modes
Dual-port LVDS data interface with on-chip 100 Ω
terminations
Low power: 1.1 W @ 2.5 GSPS
APPLICATIONS
Broadband communications systems
CMTS/VOD
Cellular infrastructure
Point-to-point wireless
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9739 is a high performance, high frequency 14-bit DAC
that provides sample rates up to 2500 MSPS, permitting
multicarrier generation up to the Nyquist frequency in
baseband mode and second and third Nyquist zones in mix
mode. It includes a serial peripheral interface (SPI) for
configuration and readback of status registers. A dual-port
LVDS interface is used to enable the high sample rate with
existing FGPA/ASIC technology. The output current can be
programmed over a range of 8.66 mA to 31.66 mA. The
AD9739 is manufactured on a 0.18 µm CMOS process and
operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-
ball chip scale ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
LVDS
RECEIVER
SYNCHRONIZER
BAND GAP
DCI_P
DCI_N
SYNC_IN_N
SYNC_IN_P
SPI
14-, 12-,
10-BIT DAC
CORE
IOUTP
IOUTN
SDO
SDIO
SCLK
CS
LVDS
DRIVER
REFERENCE
CURRENT
DACCLK_N DACCLK_P
I120VREF
RESET
DCO_P
DCO_N
SPI
S2
LVDS
RECEIVER
DB0[13:0] P
DB0[13:0]N
DB1[13:0]N
DB1[13:0] P
LVDS
DRIVER
SYNC_OUT_P
SYNC_OUT_N
CLOCK
DISTRIBUTION
07851-001
Figure 1.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD)
performance enable high quality synthesis of wideband
signals up to 1 GHz.
2. A dual-port interface with double data rate (DDR) LVDS
data receivers supports the maximum conversion rate of
2500 MSPS.
3. Manufactured on a CMOS process, the AD9739 uses a
proprietary switching technique that enhances dynamic
performance.
4. The current output(s) of the AD9739 are easily configured
for single-ended or differential circuit topologies.

AD9739
Rev. A | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 11
Static Linearity ............................................................................ 11
Dynamic Performance Normal Mode, 20 mA Full Scale
(Unless Otherwise Noted)......................................................... 13
Dynamic Performance Mix Mode, 20 mA Full Scale............ 17
DOCSIS Performance................................................................ 19
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
Serial Peripheral Interface ......................................................... 25
General Operation of the Serial Interface ............................... 25
Instruction Mode (8-Bit Instruction) ...................................... 25
Serial Interface Port Pin Descriptions ..................................... 25
SCLK—Serial Clock............................................................... 25
CS—Chip Select...................................................................... 25
SDIO—Serial Data I/O.......................................................... 25
SDO—Serial Data Out........................................................... 25
MSB/LSB Transfers..................................................................... 26
Serial Port Configuration .......................................................... 26
SPI Register Map ............................................................................ 27
SPI Registers................................................................................ 28
Applications Information .............................................................. 37
Analog Modes of Operation ..................................................... 37
LVDS Data Port Interface.......................................................... 37
Clocking the AD9739 ................................................................ 39
Applying Data to the AD9739 .................................................. 40
Mu Delay Controller.................................................................. 41
Mu Control Operation............................................................... 41
Search Mode ........................................................................... 41
Track Mode ............................................................................. 42
Mu Delay and Phase Readback ............................................ 42
Operating the Mu Controller Manually.............................. 42
Calculating Mu Delay Line Step Size................................... 42
Synchronization Controller ...................................................... 43
Operation in Master Mode ................................................... 44
Operation in Slave Mode ...................................................... 45
Data Receiver Operation in Auto Mode ................................. 45
Data Receiver Operation in Manual Mode............................. 46
Calculating the DCI Delay Line Step Size .......................... 46
Maximum Allowable Data Timing Skew/Jitter ...................... 46
Optimizing the Clock Common-Mode Voltage .................... 47
Analog Control Registers .......................................................... 47
Mirror Roll-Off Frequency Control......................................... 47
Voltage Reference ....................................................................... 47
Analog Outputs .......................................................................... 48
Interrupt Requests...................................................................... 49
Recommended Start-Up Sequence .......................................... 50
Outline Dimensions....................................................................... 53
Ordering Guide .......................................................................... 53
REVISION HISTORY
7/11—Rev 0 to Rev A
Changes to Table 2, DAC CLOCK INPUT (DACCLK_P,
DACCLK_N), Added DAC Clock Rate......................................... 4
Changes to Table 3, Added Dynamic Performance
Parameters ......................................................................................... 5
Change to Ordering Guide............................................................ 53
1/09—Revision 0: Initial Version

AD9739
Rev. A | Page 3 of 56
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IFS = 20 mA.
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY
Integral Nonlinearity (INL) ±1.3 LSB
Differential Nonlinearity (DNL) ±0.8 LSB
ANALOG OUTPUTS
Gain Error (with Internal Reference) 5.5 %
Full-Scale Output Current 8.66 20.2 31.66 mA
Output Compliance Range −1.0 +1.0 V
Output Resistance 10 MΩ
Output Capacitance 1 pF
TEMPERATURE DRIFT
Gain 60 ppm/°C
Reference Voltage 20 ppm/°C
REFERENCE
Internal Reference Voltage 1.2 V
Output Resistance15 kΩ
ANALOG SUPPLY VOLTAGES
VDDA 3.1 3.3 3.5 V
VDDC 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
VDD33 3.10 3.3 3.5 V
VDD 1.70 1.8 1.90 V
SUPPLY CURRENTS AND POWER DISSIPATION 2.0 GSPS
IVDDA 37 38 mA
IVDDC 159 166 mA
IVDD33 34 37 mA
IVDD 233 238 mA
Power Dissipation 0.940 0.975 W
Sleep Mode
IVDDA 2.5 2.75 mA
Power-Down Mode2
IVDDA 0.02 0.135 mA
IVDDC 3.8 mA
IVDD33 0.5 1.3 mA
IVDD 0.1 2.75 mA
SUPPLY CURRENTS AND POWER DISSIPATION 2.5 GSPS
IVDDA 37 mA
IVDDC 223 mA
IVDD33 34 mA
IVDD 290 mA
Power Dissipation 1.16 W
1Use an external amplifier to drive any external load.
2All power-down bits set (Register 0x01, Bit 0, Bit 1, Bit 4, Bit 5; Register 0x02, Bit 3).

AD9739
Rev. A | Page 4 of 56
DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range
link, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
LVDS DATA INPUTS
(DB0[13:0]P, DB0[13:0]N, DB1[13:0]P, DB1[13:0]N) DB+ = VIA, DB−= VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH – VIDTHL 20 mV
Receiver Differential Input Impedance, RIN 80 120 Ω
LVDS Input Rate 1250 MSPS
LVDS Minimum Data Valid Period (tMDE) 344 ps
Input Capacitance 1.2 pF
LVDS CLOCK INPUT
(DCI_P, DCI_N) DCI_P = VIA, DCI_N = VIB
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN 80 120 Ω
Maximum Clock Rate 625 MHz
LVDS CLOCK OUTPUT
(DCO_P, DCO_N) DCO_P = VOA, DCO_N = VOB 100 Ω Termination
Output Voltage High, VOA or VOB 1375 mV
Output Voltage Low, VOA or VOB 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, Single-Ended, RO40 100 140 Ω
ROMismatch Between A and B, ∆RO 10 %
Change in |VOD| Between 0 and 1, |∆VOD| 25 mV
Change in VOS Between 0 and 1, ∆VOS 25 mV
Output Current, Driver Shorted to Ground, ISA, ISB 20 mA
Output Current, Drivers Shorted Together, ISAB 4mA
Power-Off Output Leakage, |IXA|, |IXB| 10 mA
Maximum Clock Rate 625 MHz
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage 1.8 V
Common-Mode Voltage 900 mV
DAC Clock Rate 800 2500 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (fSCLK, 1/tSCLK) 20 MHz
Minimum Pulse Width High, tPWH 20 ns
Minimum Pulse Width Low, tPWL 20 ns
Minimum SDIO and CS to SCLK Setup, tDS 10 ns
Minimum SCLK to SDIO Hold, tDH 5 ns
Maximum SCLK to Valid SDIO and SDO, tDV 20 ns
Minimum SCLK to Invalid SDIO and SDO, tDNV 5 ns

AD9739
Rev. A | Page 5 of 56
Parameter Min Typ Max Unit
INPUTS (SDI, SDIO, SCLK, CS)
Voltage in High, VIH 2.0 3.3 V
Voltage in Low, VIL 0 0.8 V
Current in High, IIH −10 +10 μA
Current in Low, IIL −10 +10 μA
SDIO Output
Voltage Out High, VOH 2.4 3.6 V
Voltage Out Low, VOL 0 0.4 V
Current Out High, IOH 4 mA
Current Out Low, IOL 4 mA
AC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IFS = 20 mA.
Table 3.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
DAC Clock Rate 800 2500 MSPS
Adjusted DAC Update Rate 1800 2500 MSPS
Output Settling Time (tst) to 0.1% 13 ns
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 1200 MSPS
fOUT = 100 MHz 72 dBc
fOUT = 350 MHz 69 dBc
fOUT = 550 MHz 60 dBc
fDAC = 2000 MSPS
fOUT = 70 MHz 76 dBc
fOUT = 100 MHz 70.5 dBc
fOUT = 350 MHz 61.5 dBc
fOUT = 550 MHz 61.5 dBc
fOUT = 850 MHz 59 dBc
fDAC = 2400 MSPS
fOUT = 100 MHz 69.5 dBc
fOUT = 350 MHz 58.5 dBc
fOUT = 550 MHz 54 dBc
fOUT = 950 MHz 60 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 1200 MSPS, fOUT2 = fOUT1 + 1.25 MHz
fOUT = 100 MHz 92 dBc
fOUT = 350 MHz 90 dBc
fOUT = 550 MHz 81 dBc
fDAC = 2000 MSPS, fOUT2 = fOUT1 + 1.25 MHz
fOUT = 100 MHz 93 dBc
fOUT = 350 MHz 74 dBc
fOUT = 550 MHz 71 dBc
fOUT = 850 MHz 67.5 dBc
fDAC = 2400 MSPS
fOUT = 100 MHz 94 dBc
fOUT = 350 MHz 78 dBc
fOUT = 550 MHz 72 dBc
fOUT = 950 MHz 68 dBc

AD9739
Rev. A | Page 6 of 56
Parameter Min Typ Max Unit
NOISE SPECTRAL DENSITY (NSD)
Single Tone, fDAC = 2400 MSPS
fOUT = 100 MHz −166 dBm/Hz
fOUT = 350MHz −161 dBm/Hz
fOUT = 550 MHz −160 dBm/Hz
fOUT = 850 MHz −160 dBm/Hz
Eight-Tone, fDAC = 2400 MSPS, 500 kHz Tone Spacing
fOUT = 100 MHz −168 dBm/Hz
fOUT = 350 MHz −166 dBm/Hz
fOUT = 550 MHz −166 dBm/Hz
fOUT = 850 MHz −165 dBm/Hz
WCDMA Adjacent Channel Leakage Ratio (ACLR), Single Carrier
fDAC = 2457.6 MSPS, fOUT = 150 MHz 80.5 dBc
fDAC = 2457.6 MSPS fOUT = 350 MHz 80 dBc
fDAC= 2457.6 MSPS, fOUT = 550 MHz 79 dBc
fDAC= 2457.6 MSPS, fOUT = 950 MHz 78 dBc
WCDMA Second ACLR, Single Carrier
fDAC = 2457.6 MSPS, fOUT = 150 MHz 84 dBc
fDAC = 2457.6 MSPS, fOUT = 350 MHz 80 dBc
fDAC = 2457.6 MSPS, fOUT = 550 MHz 80 dBc
fDAC = 2457.6 MSPS, fOUT = 950 MHz 79 dBc
WCDMA ACLR, Single Carrier
(Mix Mode Second Nyquist Zone)
fDAC = 2457.6 MSPS, fOUT = 1300 MHz 73.5 dBc
fDAC = 2457.6 MSPS, fOUT = 1700 MHz 73.5 dBc
fDAC = 2457.6 MSPS, fOUT = 2100 MHz 69 dBc
fDAC = 2457.6 MSPS, fOUT = 2400 MHz 68 dBc
WCDMA Second ACLR, Single Carrier
(Mix Mode Second Nyquist Zone)
fDAC = 2457.6 MSPS, fOUT = 1300 MHz 74.5 dBc
fDAC = 2457.6 MSPS, fOUT = 1700 MHz 74 dBc
fDAC = 2457.6 MSPS, fOUT = 2100 MHz 72 dBc
fDAC = 2457.6 MSPS, fOUT = 2400 MHz 71 dBc
WCDMA ACLR, Single Carrier
(Mix Mode Third Nyquist Zone)
fDAC = 2457.6 MSPS, fOUT = 2500 MHz 68 dBc
fDAC = 2457. MSPS, fOUT = 2800 MHz 66 dBc
fDAC = 2457.6 MSPS, fOUT = 3200 MHz 66 dBc
fDAC = 2457.6 MSPS, fOUT = 3600 MHz 64 dBc
WCDMA ACLR, Single Carrier
(Mix Mode Third Nyquist Zone)
fDAC = 2457.6 MSPS, fOUT = 2500 MHz 70 dBc
fDAC = 2457.6 MSPS, fOUT = 2800 MHz 67 dBc
fDAC = 2457.6 MSPS, fOUT = 3200 MHz 67 dBc
fDAC = 2457.6 MSPS, fOUT = 3600 MHz 64.5 dBc
1Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus,
with fDAC = 2500 MSPS, fDAC adjusted = 2500 MSPS.

AD9739
Rev. A | Page 7 of 56
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
With
Respect To Rating
VDDA VSSA −0.3 V to +3.6 V
VDD33 VSS −0.3 V to +3.6 V
VDD VSS −0.3 V to +1.98 V
VDDC VSSC −0.3 V to +1.98 V
VSSA VSS −0.3 V to +0.3 V
VSSA VSSC −0.3 V to +0.3 V
VSS VSSC −0.3 V to +0.3 V
DACCLK_P,
DACCLK_N
VSSC −0.3 V to CVDD18 + 0.18 V
DCI, DCO VSS −0.3 V to DVDD33 + 0.3 V
LVDS Data Inputs VSS −0.3 V to DVDD33 + 0.3 V
IOUTP, IOUTN VSSA −1.0 V to AVDD33 + 0.3 V
I120, VREF, IPTAT VSSA −0.3 V to AVDD33 + 0.3 V
IRQ, CS, SCLK, SDO,
SDIO, RESET
VSS −0.3 V to DVDD33 + 0.3 V
Junction Temperature 150°C
Storage Temperature −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA θ
JC Unit
160-Ball CSP_BGA 31.2 7.0 °C/W1
1With no airflow movement.
ESD CAUTION

AD9739
Rev. A | Page 8 of 56
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
VSSA, ANALOG SUPPLY GROUND
VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD
VDDA, 3.3V, ANALOG SUPPLY
07851-002
Figure 2. Analog Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
VSS DIGITAL SUPPLY GROUND
VDD33, 3.3V DIGITAL SUPPLY
VDD, 1.8V, DIGITAL SUPPLY
07851-003
Figure 3. Digital Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
VSSC, CLOCK SUPPLY GROUND
VDDC, 1.8V, CLOCK SUPPLY
07851-004
Figure 4. Digital LVDS Clock Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
SYNC_OUT_P/_N
DB1[0:13] P
DB1[0:13]N
DB0[0:13] P
DB0[0:13]N
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
SYNC_IN_P/_N
DACCLK_N
DACCLK_P
N
P
1413121110876321954
DCI_P/_N
DCO_P/_N
07851-005
Figure 5. Digital LVDS Input, Clock I/O (Top View)

AD9739
Rev. A | Page 9 of 56
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1413121110876321954
IRQ
CS
SCLK
RESET
SDIO
SDO
IOUTN IOUTP
I120
VREF
IPTAT
07851-006
Figure 6. Analog I/O and SPI Control Pins (Top View)
Table 6. AD9739 Pin Function Descriptions
Pin No. Mnemonic Description
C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply.
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
C5, D4, D5
VSSC Clock Supply Ground.
A10, A11, B10, B11, C10, C11, D10, D11 VDDA 3.3 V Analog Supply.
A12, A13, B12, B13, C12, C13, D12, D13, VSSA Analog Supply Ground.
A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3,
F4, E11, E12, E13, E14, F11, F12
VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.
A14 NC
No Connect
A7, B7, C7, D7 IOUTN DAC Negative Output. 10 mA to 30 mA full-scale output
current.
A8, B8, C8, D8 IOUTP DAC Positive Output. 10 mA to 30 mA full-scale output current.
B14 I120 Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 μA reference current.
C14 VREF Band Gap Voltage Reference I/O. Tie to analog ground via a 1 nF
capacitor; output impedance is approximately 5 kΩ.
D14 IPTAT Factory Test Pin. Output current, proportional to absolute
temperature, is approximately 10 μA at 25°C with a slope of
approximately 20 nA/°C.
C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK).
F13 IRQ IRQ. Active low open-drain interrupt request output; pull up to
DVDD33 with a 10 kΩ resistor.
F14 RESET RESET. 1 resets the AD9739.
G13 CS See the Serial Peripheral Interface section for the pin
description.
G14 SDIO See the Serial Peripheral Interface section for the pin
description.
H13 SCLK See the Serial Peripheral Interface section for the pin
description.
H14 SDO See the Serial Peripheral Interface section for the pin
description.
J3, J4, J11, J12 VDD33 3.3 V Digital Supply.
G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply.
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground.
J1, J2 SYNC_OUT_P/SYNC_OUT_N Positive/Negative SYNC Output (SYNC_OUT).1
K1, K2 SYNC_IN_P/SYNC_IN_N Positive/Negative SYNC Input (SYNC_IN).1
J13, J14 DCO_P/DCO_N Positive/Negative Data Output Clock (DCO).1
K13, K14 DCI_P/DCI_N Positive/Negative Data Input Clock (DCI).1

AD9739
Rev. A | Page 10 of 56
Pin No. Mnemonic Description
L1, M1 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0.1
L2, M2 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1.1
L3, M3 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2.1
L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3.1
L5, M5 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4.1
L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5.1
L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6.1
L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7.1
L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8.1
L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9.1
L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10.1
L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11.1
L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12.1
L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13.1
N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0.1
N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1.1
N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2.1
N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3.1
N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4.1
N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5.1
N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6.1
N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7.1
N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8.1
N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9.1
N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10.1
N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11.1
N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12.1
N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.1
1Conforms to IEEE-1596 reduced range link.

AD9739
Rev. A | Page 11 of 56
TYPICAL PERFORMANCE CHARACTERISTICS
STATIC LINEARITY
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
CODE
ERROR (LSB)
20480 4096 6144 8192 10,240 12,288 14,336 16,384
07851-007
Figure 7. Typical INL, 20 mA @ 25°C
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
07851-010
Figure 8. Typical DNL, 20 mA @ 25°C
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
0
7851-008
Figure 9. Typical INL, 20 mA @ −40°C
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
07851-011
Figure 10. Typical DNL, 20 mA @ −40°C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
07851-009
Figure 11. Typical INL, 20 mA @ 85°C
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
07851-012
Figure 12. Typical DNL, 20 mA @ 85°C

AD9739
Rev. A | Page 12 of 56
CODE
ERROR (LSB)
20480 4096 6144 8192 10,240 12,288 14,336 16,384
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0
7851-013
Figure 13. Typical INL, 10 mA @ 25°C
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
07851-016
Figure 14. Typical DNL, 10 mA @ 25°C
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
07851-014
Figure 15. Typical INL, 30 mA @ 25°C
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0
CODE
ERROR (LSB)
2048 4096 6144 8192 10,240 12,288 14,336 16,384
0
7851-017
Figure 16. Typical DNL, 30 mA @ 25°C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0 250 500 750 1000 1250 1500 1750 2000 2250 2500
TOTAL
DVDD18
CLKVDD
AVDD
DVDD33
f
DAC (MHz)
POWER (W)
07851-015
Figure 17. Power Consumption vs. fDAC @ 25°C

AD9739
Rev. A | Page 13 of 56
DYNAMIC PERFORMANCE NORMAL MODE, 20 MA FULL SCALE (UNLESS OTHERWISE NOTED)
VBW 10kHz
10dB/DIV
STOP 2.4GHzSTART 20MHz
07851-018
Figure 18. Single Tone Spectrum @ fOUT = 91 MHz, fDAC = 2.4 GSPS
VBW 10kHz
10dB/DIV
STOP 2.4GHzSTART 20MHz
07851-021
Figure 19. Single Tone Spectrum @ fOUT = 1091 MHz, fDAC = 2.4 GSPS
f
OUT
(MHz)
SFDR (dBc)
30
35
40
45
50
55
60
65
70
75
80
0 100 200 300 400 500 600 700 800 900 1000 1100 1200
1.6GSPS
1.2GSPS
2.4GSPS
2.0GSPS
07851-019
Figure 20. SFDR vs. fOUT over fDAC
–3dBFS
0dBFS
f
OUT
(MHz)
SFDR (dBc)
30
40
50
60
70
80
90
0 100 200 300 400 500 600 700 800 900 1000
–6dBFS
07851-022
Figure 21. SFDR vs. fOUT over DIGFS @ 2.0 GSPS
f
OUT
(MHz)
SFDR (dB)
30
0 100 200 300 400 500 600 700 800 900 1000
07851-119
40
50
60
70
80
90
0dBFS –3dBFS
–6dBFS
Figure 22. SFDR for Second Harmonic over fOUT WRT DIGFS @ 2.0 GSPS
f
OUT
(MHz)
SFDR (dB)
30
0 100 200 300 400 500 600 700 800 900 1000
07851-118
40
50
60
70
80
90
–6dBFS
–3dBFS
0dBFS
Figure 23. SFDR for Third Harmonic over fOUT WRT DIGFS @ 2.0 GSPS

AD9739
Rev. A | Page 14 of 56
f
OUT
(MHz)
SFDR (dBc)
30
40
50
60
70
80
90
0 100 200 300 400 500 600 700 800 900 1000
10mA FS
20mA FS
30mA FS
07851-020
Figure 24. SFDR vs. fOUT over ANAFS @ 2.0 GSPS
f
OUT
(MHz)
SFDR (dBc)
30
40
50
60
70
80
90
0 100 200 300 400 500 600 700 800 900 1000
+25°C
+85°C
–40°C
07851-023
Figure 25. SFDR vs. fOUT over Temperature @ 2.0 GSPS
f
OUT
(MHz)
IMD (dBc)
30
0 100 200 300 400 500 600 700 800 900 1000
35
40
45
50
55
60
65
70
75
80
85
90
95
100
1100 1200
1.2GSPS
1.6GSPS
2.0GSPS
2.4GSPS
07851-024
Figure 26. IMD vs. fOUT over fDAC
f
OUT
(MHz)
IMD (dBc)
30
40
50
60
70
80
90
100
110
0 100 200 300 400 500 600 700 800 900 1000
0dBFS
–6dBFS
–3dBFS
07851-027
Figure 27. IMD vs. fOUT over DIGFS @ 2.0 GSPS
f
OUT
(MHz)
IMD (dBc)
30
40
50
60
70
80
90
100
110
0 100 200 300 400 500 600 700 800 900 1000
10mA FS
20mA FS
30mA FS
07851-025
Figure 28. IMD vs. fOUT over ANAFS @ 2.0 GSPS
f
OUT
(MHz)
IMD (dBc)
30
40
50
60
70
80
90
100
110
0 100 200 300 400 500 600 700 800 900 1000
+25°C
–40°C
+85°C
07851-028
Figure 29. IMD vs. fOUT over Temperature @ 2.0 GSPS

AD9739
Rev. A | Page 15 of 56
NSD (dBm/Hz)
–170
–168
–166
–164
–162
–160
–158
–156
–154
–152
–
150
1.2GSPS
2.4GSPS
f
OUT
(MHz)
0 100 200 300 400 500 600 700 800 900 1000 1100 1200
07851-026
Figure 30. Single-Tone NSD vs. fOUT over fDAC
f
OUT
(MHz)
NSD (dBm/Hz)
0 100 200 300 400 500 600 700 800 900 1000 1100 1200
–170
–169
–168
–167
–166
–165
–164
–163
–162
–161
–
160
2.4GSPS
1.2GSPS
07851-029
Figure 31. Eight-Tone NSD vs. fOUT over fDAC
–170
–168
–166
–164
–162
–160
–158
–156
–154
–152
–
150
0 200 400 600 800 1000100 300 500 700 900
f
OUT
(MHz)
NSD (dBm/Hz)
+25°C
–40°C
+85°C
07851-030
Figure 32. Single-Tone NSD vs. fOUT over Temperature @ 2.0 GSPS
–170
–168
–166
–164
–162
–160
–158
–156
–154
–152
–
150
0 200 400 600 800 1000100 300 500 700 900
f
OUT
(MHz)
NSD (dBm/Hz)
+25°C
–40°C
+85°C
07851-033
Figure 33. Eight-Tone NSD vs. fOUT over Temperature @ 2.0 GSPS
–90
–85
–80
–75
–70
–65
–60
–55
–
50
0
122.88
245.76
368.64
491.52
614.40
737.28
860.16
983.04
1105.90
1228.80
FIRST ADJ CH
SECOND ADJ CH
FIFTH ADJ CH
f
OUT
(MHz)
ACLR (dBc)
07851-031
Figure 34. Single-Carrier WCDMA ACLR vs. fOUT @ 2457.6 MSPS

AD9739
Rev. A | Page 16 of 56
VBW 300kHz
10dB/DIV
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
CENTER 350.27MHz
#RES BW 30kHz
07851-034
RMS RESULTS
CARRIER POWER
–14.54dBm/
3.84MHz
FREQ
OFFSET
(MHz)
5
10
15
20
25
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
(dBc)
–79.90
–80.60
–80.90
–80.62
–80.76
(dBm)
–94.44
–95.14
–95.45
–95.16
–95.30
LOWER
(dBc)
–79.03
–79.36
–80.73
–80.97
–80.95
(dBm)
–93.57
–94.40
–95.27
–95.51
–95.49
UPPER
VBW 300kHz
10dB/DIV
SPAN 63.84MHz
SWEEP 207ms (601pts)
CENTER 355.11MHz
#RES BW 30kHz
07851-032
RMS RESULTS
CARRIER POWER
–18.27dBm/
3.84MHz
FREQ
OFFSET
(MHz)
5
10
15
20
25
30
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
3.84
(dBc)
–0.29
–68.63
–70.92
–73.78
–75.26
–75.98
(dBm)
–18.57
–86.90
–89.19
–92.06
–93.54
–94.25
LOWER
(dBc)
–0.22
–0.23
–69.68
–72.41
–73.91
–76.38
(dBm)
–18.50
–18.50
–87.95
–90.68
–92.18
–94.65
UPPER
Figure 35. Typical Single-Carrier WCDMA ACLR Performance @ 350 MHz
fDAC = 2457.6 MSPS
Figure 36. Typical Four-Carrier WCDMA ACLR Performance @ 350 MHz,
fDAC = 2457.6 MSPS

AD9739
Rev. A | Page 17 of 56
DYNAMIC PERFORMANCE MIX MODE, 20 mA FULL SCALE
VBW 10kHz
10dB/DIV
STOP 2.4GHz
SWEEP 28.7s (601pts)
START 20MHz
#RES BW 10kHz
0
7851-035
Figure 37. Single-Tone Spectrum in Mix Mode @ fOUT = 2.31 GHz,
fDAC = 2.4 GSPS
VBW 10kHz
10dB/DIV
STOP 2.4GHzSTART 20MHz
07851-038
STOP 2.4GHz
SWEEP 28.7s (601pts)
START 20MHz
#RES BW 10kHz
Figure 38. Single-Tone Spectrum in Mix Mode @ fOUT = 1.31 GHz,
fDAC = 2.4 GSPS
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
f
OUT
(MHz)
SFDR (dBc)
07851-036
Figure 39. SFDR in Mix Mode vs. fOUT @ 2.4 GSPS
30
35
40
45
50
55
60
65
70
75
80
85
90
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
f
OUT
(MHz)
IMD (dBc)
07851-039
Figure 40. IMD in Mix Mode vs. fOUT @ 2.4 GSPS
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–
40
1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686
SECOND NYQUIST ZONE THIRD NYQUIST ZONE
FIRST ADJ CH
SECOND ADJ CH
FIFTH ADJ CH
f
OUT
(MHz)
ACLR (dBc)
07851-037
Figure 41. Single-Carrier WCDMA ACLR vs. fOUT @ 2457.6 MSPS
VBW 300kHz
10dB/DIV
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
CENTER 2.10706MHz
#RES VW 30kHz
RMS RESULTS
CARRIER POWER
–21.43dBm/
3.84MHz
FREQ
OFFSET
(MHz)
5
10
15
20
25
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
(dBc)
–68.99
–72.09
–72.86
–74.34
–74.77
(dBm)
–90.43
–93.52
–94.30
–95.77
–96.20
LOWER
(dBc)
–63.94
–71.07
–71.34
–72.60
–73.26
(dBm)
–90.37
–92.50
–92.77
–94.03
–94.70
UPPER
07851-040
Figure 42. Typical Single-Carrier WCDMA ACLR Performance @ 2.1 GHz,
fDAC = 2457.6 MSPS (Second Nyquist Zone)

AD9739
Rev. A | Page 18 of 56
VBW 300kHz
10dB/DIV
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
CENTER 2.807GHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–24.4dBm/
3.84MHz
FREQ
OFFSET
(MHz)
5
10
15
20
25
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
(dBc)
–64.90
–66.27
–68.44
–70.20
–70.85
(dBm)
–89.30
–90.67
–92.84
–94.60
–95.25
LOWER
(dBc)
–63.82
–65.70
–66.55
–68.95
–70.45
(dBm)
–88.22
–90.10
–90.95
–93.35
–94.85
UPPER
07851-041
Figure 43. Typical Single-Carrier WCDMA ACLR Performance @ 2.8 GHz,
fDAC = 2457.6 MSPS (Third Nyquist Zone)
VBW 300kHz
10dB/DIV
SPAN 63.84MHz
SWEEP 207ms (601pts)
CENTER 2.09758GHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–25.53dBm/
3.84MHz
FREQ
OFFSET
(MHz)
5
10
15
20
25
30
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
3.84
(dBc)
0.22
–66.68
–68.01
–68.61
–68.87
–69.21
(dBm)
–25.31
–92.21
–93.53
–94.14
–94.40
–94.74
LOWER
(dBc)
0.24
0.14
–66.82
–67.83
–67.64
–68.50
(dBm)
–25.29
–25.38
–92.35
–93.36
–93.17
–94.03
UPPER
07851-043
Figure 44. Typical Four-Carrier WCDMA ACLR Performance @ 2.1 GHz,
fDAC = 2457.6 MSPS (Second Nyquist Zone)
VBW 300kHz
10dB/DIV
SPAN 63.84MHz
SWEEP 207ms (601pts)
CENTER 2.81271GHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–27.98dBm/
3.84MHz
FREQ
OFFSET
(MHz)
5
10
15
20
25
30
REF
BW
(MHz)
3.84
3.84
3.84
3.84
3.84
3.84
(dBc)
–0.42
–64.32
–66.03
–66.27
–66.82
–67.16
(dBm)
–28.40
–92.30
–94.01
–94.24
–94.79
–95.13
LOWER
(dBc)
–0.10
–0.08
–65.37
–66.06
–63.36
–66.54
(dBm)
–28.07
–28.06
–93.34
–94.03
–93.34
–94.51
UPPER
07851-042
Figure 45. Typical Four-Carrier WCDMA ACLR Performance @ 2.8 GHz
fDAC = 2457.6 MSPS (Third Nyquist Zone)

AD9739
Rev. A | Page 19 of 56
DOCSIS PERFORMANCE
0 100 200 300 400 500 600 700 800 900 1000
f
OUT
(MHz)
ACLR (dBc)
07851-044
0
–10
–20
–30
–40
–50
–60
–90
–80
–70
Figure 46. Single-Carrier DOCSIS ACLR Spectral Plot @ 91 MHz
(DOCSIS SPEC (Red Line) Is 73 dBc ; Harmonic Exception Is 63 dBc)
VBW 500kHz
10dB/DIV
SPAN 18MHz
SWEEP 16.76ms (601pts)
CENTER 95.08GHz
#RES BW 56kHz
RMS RESULTS
CARRIER POWER
–14.51dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
REF
BW
(MHz)
750
5.25
(dBc)
–71.50
–76.09
(dBm)
–86.01
–90.59
LOWER
(dBc)
–71.01
–76.20
(dBm)
–85.52
–90.70
UPPER
07851-045
Figure 47. Single-Carrier DOCSIS Close-in ACLR Plot @ 91 MHz
(Two Closest Channels)
VBW 300kHz
10dB/DIV
SPAN 42MHz
SWEEP 136.2ms (601pts)
CENTER 95.08GHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–14.48dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
12.00
18.00
REF
BW
(MHz)
750
5.25
6
6
(dBc)
–73.50
–76.03
–82.65
–82.62
(dBm)
–86.01
–90.59
–97.13
–97.10
LOWER
(dBc)
–71.04
–76.81
–82.35
–82.50
(dBm)
–85.52
–90.70
–96.83
–96.98
UPPER
07851-046
Figure 48. Single-Carrier DOCSIS Close-in ACLR Plot @ 91 MHz
0 100 200 300 400 500 600 700 800 900 1000
f
OUT (MHz)
ACLR (dBc)
07851-047
0
–10
–20
–30
–40
–50
–60
–90
–80
–70
Figure 49. Single-Carrier DOCSIS ACLR Spectral Plot @ 325 MHz
(DOCSIS SPEC (Red Line) Is 73 dBc ; Harmonic Exception Is 63 dBc)
VBW 300kHz
10dB/DIV
SPAN 18MHz
SWEEP 58.4ms (601pts)
CENTER 322.35MHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–17.11dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
REF
BW
(MHz)
750
5.25
(dBc)
–74.62
–77.09
(dBm)
–91.73
–94.19
LOWER
(dBc)
–74.66
–77.55
(dBm)
–91.77
–94.66
UPPER
07851-048
Figure 50. Single-Carrier DOCSIS Close-in ACLR Plot @ 325 MHz
(Two Closest Channels)
VBW 300kHz
10dB/DIV
SPAN 42MHz
SWEEP 136.2ms (601pts)
CENTER 322.35MHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–17.06dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
12.00
18.00
REF
BW
(MHz)
750
5.25
6
6
(dBc)
–72.35
–76.50
–79.37
–79.38
(dBm)
–89.41
–93.56
–96.43
–96.45
LOWER
(dBc)
–72.58
–77.89
–79.00
–79.04
(dBm)
–89.64
–94.95
–96.06
–96.10
UPPER
07851-049
Figure 51. Single-Carrier DOCSIS Close-in ACLR Plot @ 325 MHz

AD9739
Rev. A | Page 20 of 56
0 100 200 300 400 500 600 700 800 900 1000
f
OUT
(MHz)
ACLR (dBc)
07851-050
0
–10
–20
–30
–40
–50
–60
–90
–80
–70
Figure 52. Single-Carrier DOCSIS ACLR Spectral Plot @ 825 MHz (DOCSIS SPEC
(Red Line) Is 73 dBc ; Harmonic Exception Is 63 dBc)
VBW 300kHz
10dB/DIV
SPAN 18MHz
SWEEP 58.4ms (601pts)
CENTER 817.2MHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–17.35dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
REF
BW
(MHz)
750
5.25
(dBc)
–74.94
–75.03
(dBm)
–92.28
–92.38
LOWER
(dBc)
–73.72
–75.21
(dBm)
–91.07
–92.56
UPPER
07851-051
Figure 53. Single-Carrier DOCSIS Close-in ACLR Plot @ 825 MHz
(Two Closest Channels)
VBW 300kHz
10dB/DIV
SPAN 42MHz
SWEEP 136.2ms (601pts)
CENTER 817.20GHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–17.39dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
12.00
18.00
REF
BW
(MHz)
750
5.25
6
6
(dBc)
–72.21
–75.11
–78.15
–78.26
(dBm)
–89.60
–92.50
–95.55
–95.65
LOWER
(dBc)
–71.78
–75.07
–78.07
–78.14
(dBm)
–89.17
–92.46
–95.46
–95.53
UPPER
07851-052
Figure 54. Single-Carrier DOCSIS Close-in ACLR Plot @ 825 MHz
f
OUT
(MHz)
0 100 200 300 400 500 600 700 800 900 1000
ACLR (dBc)
07851-053
0
–10
–20
–30
–40
–50
–60
–80
–70
Figure 55. Four-Carrier DOCSIS ACLR Spectral Plot @ 91 MHz (DOCSIS SPEC
(Red Line) Is 67 dBc; Harmonic Exception Is 61 dBc)
VBW 300kHz
10dB/DIV
SPAN 18MHz
SWEEP 58.4ms (601pts)
CENTER 107.1MHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–20.06dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
REF
BW
(MHz)
750
5.25
(dBc)
–10.59
–0.11
(dBm)
–30.65
–20.17
LOWER
(dBc)
–76.34
–74.41
(dBm)
–96.40
–94.47
UPPER
07851-054
Figure 56. Four-Carrier DOCSIS Close-in ACLR Plot @ 91 MHz
(Two Closest Channels)
VBW 300kHz
10dB/DIV
SPAN 42MHz
SWEEP 136.2ms (601pts)
CENTER 107.1MHz
#RES BW 30kHz
RMS RESULTS
CARRIER POWER
–20.03dBm/
6MHz
FREQ
OFFSET
(MHz)
3.375
6.375
12.00
18.00
REF
BW
(MHz)
750
5.25
6
6
(dBc)
–10.02
–0.15
0.26
–0.07
(dBm)
–30.84
–20.17
–19.76
–20.10
LOWER
(dBc)
–76.21
–74.60
–76.30
–76.06
(dBm)
–96.24
–94.63
–96.32
–96.09
UPPER
07851-055
Figure 57. Single-Carrier DOCSIS Close-in ACLR Plot @ 91 MHz