Analog Devices ADSP-219 Series Application guide

ADSP-219x/2192 DSP Hardware Reference B-1
B ADSP-2192 DSP PERIPHERAL
REGISTERS
Figure B-0.
Table B-0.
Listing B-0.
Overview
The DSP has general-purpose and dedicated registers in each of its func-
tional blocks. The register reference information for each functional block
includes bit definitions, initialization values, and (for I/O processor regis-
ters) memory-mapped addresses. Information on each type of register is
available at the following locations:
•“Core Status Registers” on page A-8
•“Computational Unit Registers” on page A-16
•“Program Sequencer Registers” on page A-19
•“Data Address Generator Registers” on page A-26
•“Peripheral Registers” on page B-2
When writing DSP programs, it is often necessary to set, clear, or test bits
in the DSP’s registers. While these bit operations can be done by referring
to the bit’s location within a register or (for some operations) the register’s
address with a hexadecimal number, it is much easier to use symbols that
correspond to the bit’s or register’s name.
For convenience and consistency, Analog Devices provides header files
that define these bit and register definitions (def2192_IO.h,
def2192_PCI.h, def2192_USB.h, def2192-12.h, and def219x.h). Note
that the def2192-12.h file also contains the definitions from the IO, PCI,
and USB header files.

Peripheral Registers
B-2 ADSP-219x/2192 DSP Hardware Reference
A sample of def219x.h is shown in “Register & Bit #Defines File”on
page A-29, and a sample of def2192-12.h is shown in “Register and Bit
#Defines File”on page B-95.
LMany registers have reserved bits. When writing to a register, pro-
grams may clear (write zero to) the register’s reserved bits only.
Peripheral Registers
There are three groups of registers for the ADSP-2192:
•“ADSP-2192 DSP Core Registers”on page A-1
•“ADSP-2192 System Control Registers”on page B-6
•“ADSP-2192 Peripheral Device Control Registers”on page B-11
This appendix describes system control registers and peripheral device
control registers. A general description of DSP peripheral architecture,
which follows, provides an overview of peripheral registers.

ADSP-219x/2192 DSP Hardware Reference B-3
ADSP-2192 DSP Peripheral Registers
DSP Peripherals Architecture
Figure B-1 shows the DSP’s on-chip peripherals, which include the Host
port (PCI or USB), AC’97 port, JTAG test and emulation port, flags, and
interrupt controller.
Figure B-1. ADSP-2192 Dual-Core DSP Block Diagram
The ADSP-2192 can respond to up to fourteen interrupts at any given
time. A list of these interrupts can be found in the table “Interrupt Vectors
for an ADSP-2192 DSP Core”on page 6-14.
The AC’97 codec port on the ADSP-2192 provides a complete synchro-
nous, full-duplex serial interface. This interface completely supports the
AC’97 standard.
The ADSP-2192 provides up to eight general-purpose I/O pins, which are
programmable as either inputs or outputs. These pins are dedicated gen-
eral-purpose programmable flag pins.
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Peripheral Device Register Groups
B-4 ADSP-219x/2192 DSP Hardware Reference
Peripheral Device Register Groups
The registers that control FIFO DMA transfers are accessible only from
within the DSP. They are defined as part of the Core Register Space.
Summary
Each of the DSPs integrated within the ADSP-2192 and the interfaces
(PCI, USB Sub-ISA, Cardbus) needs to be capable of controlling and
monitoring a variety of registers external to the DSP core. This section
describes how the DSPs access these Peripheral Device Control (PDC)
registers. The operation of the Peripheral Device Control (PDC) Bus that
connects the DSPs and Interfaces to the PDC Registers is also described in
this section.
Writes to AC’97 codec registers are posted, but only one may complete
per AC’97 frame. Up to two writes may be pending at any one time. The
first write completes with zero PDC wait states. A second write launched
immediately after the first incurs PDC wait states equivalent to a few
AC’97 BITCLKs. A third write in a row blocks for an entire AC’97 frame.
Use the Frame interrupt to time AC’97 codec writes out to one per frame,
assuring that they will all complete with zero wait states.
Reads from AC’97 codec registers must always wait for the data to be
returned. A read must also wait for any pending AC’97 codec register
writes to complete before it can begin. In the best case, a read takes one
full AC’97 frame plus another three AC’97 slots (25.39 µs, or approxi-
mately 3,744 DSP cycles). This is also the typical case when the AC’97
Frame Interrupt is used to time the Read.
The worst case AC’97 read time is four frames plus three slots (87.89 µs,
or approximately 12,960 DSP cycles). This occurs only when there are
already two AC’97 codec register writes pending just after the start of a
frame.

ADSP-219x/2192 DSP Hardware Reference B-5
ADSP-2192 DSP Peripheral Registers
Most AC’97 codec registers may be shadowed, and actual reads should be
rare.
Example
In the worst case, DSP core P1 posts two AC’97 codec register writes just
after the start of a new Frame. DSP core P0 immediately follows with a
read to an AC’97 codec register. DSP core P0 will be unable to compute,
DMA, or interrupt for 87.89 µs. DSP core P1 can compute with data in
its own memory, but cannot communicate with DSP core P0 or access any
PDC bus register for 87.89 µs. The external bus interface can communi-
cate with DSP core P1, but cannot communicate with DSP core P0 or
access any PDC bus register for 87.89 µs. In the state, the entire
ADSP-2192 system is highly constrained.

ADSP-2192 System Control Registers
B-6 ADSP-219x/2192 DSP Hardware Reference
ADSP-2192 System Control Registers
The following tables show the System Control Registers in each DSP core.
Table B-1. ADSP-2192 System Control Registers
Address Register Function
00 B0 Base Register0
01 B1 Base Register1
02 B2 Base Register2
03 B3 Base Register3
04 B4 Base Register4
05 B5 Base Register5
06 B6 Base Register6
07 B7 Base Register7
08 - 0B Reserved
0C DMAPAGE DMA Page Register
0D - 0E Reserved
0F CACTL Cache Control Register
10 STCTL0 FIFO0 Transmit Control Register
11 SRCTL0 FIFO0 Receive Control Register
12 TX0 FIFO0 Transmit Data (TX) register
13 RX0 FIFO0 Receive Data (RX) register

ADSP-219x/2192 DSP Hardware Reference B-7
ADSP-2192 DSP Peripheral Registers
14 - 1F Reserved
20 STCTL1 FIFO1 Transmit Control Register
21 SRCTL1 FIFO1 Receive Control Register
22 TX1 FIFO1 Transmit Data (TX) register
23 RX1 FIFO1 Receive Data (RX) register
24 - 2F Reserved
30 TPERIOD Timer Period Register
31 TCOUNT Timer Counter Register
32 TSCALE Timer Scaling Register
33 TSCALECNT Timer Scale Count Register
34 FLAGS Flags Register
35 - 3F Reserved
40 - 43 Reserved
44 MASTADDR DMA Address, DSP Master DMA
45 MASTNXTADDR DMA Next Address, DSP Master DMA
46 MASTCNT DMA Count, DSP Master DMA
47 MASTCURCNT DMA Current Count, DSP Master DMA
48 TX0ADDR DMA Address, FIFO0 Transmit
49 TX0NXTADDR DMA Next Address, FIFO0 Transmit
Table B-1. ADSP-2192 System Control Registers (Continued)
Address Register Function

ADSP-2192 System Control Registers
B-8 ADSP-219x/2192 DSP Hardware Reference
4A TX0CNT DMA Count, FIFO0 Transmit
4B TX0CURCNT DMA Current Count, FIFO0 Transmit
4C RX0ADDR DMA Address, FIFO0 Receive
4D RX0NXTADDR DMA Next Address, FIFO0 Receive
4E RX0CNT DMA Count, FIFO0 Receive
4F RX0CURCNT DMA Current Count, FIFO0 Receive
50 TX1ADDR DMA Address, FIFO1 Transmit
51 TX1NXTADDR DMA Next Address, FIFO1 Transmit
52 TX1CNT DMA Count, FIFO1 Transmit
53 TX1CURCNT DMA Current Count, FIFO1 Transmit
54 RX1ADDR DMA Address, FIFO1 Receive
55 RX1NXTADDR DMA Next Address, FIFO1 Receive
56 RX1CNT DMA Count, FIFO1 Receive
57 RX1CURCNT DMA Current Count, FIFO1 Receive
58-5F Reserved
60 DBGCTRL Test and Emulation Debug Control Register
61 DBGSTAT Test and Emulation Debug Status Register
62 CNT0 Cycle Counter 0 Register (LSB)
63 CNT1 Cycle Counter 1 Register
Table B-1. ADSP-2192 System Control Registers (Continued)
Address Register Function

ADSP-219x/2192 DSP Hardware Reference B-9
ADSP-2192 DSP Peripheral Registers
STCTLx FIFO Transmit Control Register
These include the STCTL0 and STCTL1 registers in each DSP core.
SRCTLx FIFO Receive Control Register
These include the SRCTL0 and SRCTL1 registers in each DSP core.
64 CNT2 Cycle Counter 2 Register
65 CNT3 Cycle Counter 3 Register (MSB)
66-FF Reserved
1514131211109876543210
FLOW EMPTY FULL LOOP SDEN FIP2 FIP1 FIP0 SSEL3 SSEL2 SSEL1 SSEL0 DSP FLSH SDEN SPEN
1514131211109876543210
FLOW EMPTY FULL LOOP SDEN FIP2 FIP1 FIP0 SSEL3 SSEL2 SSEL1 SSEL0 DSP FLSH SDEN SPEN
Table B-1. ADSP-2192 System Control Registers (Continued)
Address Register Function

ADSP-2192 System Control Registers
B-10 ADSP-219x/2192 DSP Hardware Reference
xxxADDR DMA Address Register
This group of registers include Rx0ADDR, Rx1ADDR, Tx0ADDR, Tx1ADDR, and MAS-
TADDR registers for each DSP core. Each register is a 16-bit register
containing a 16-bit word.
xxxNXTADDR DMA Next Address Register
This group of registers include Rx0NXTADDR, Rx1NXTADDR, Tx0NXTADDR, Tx1NXTADDR,
and MASTNXTADDR for each DSP core. Each register is a 16-bit register con-
taining a 16-bit word.
xxxCNT DMA Count Register
This group of registers include Rx0CNT, Rx1CNT, Tx0CNT, Tx1CNT, and MASTCNT for
each DSP core. Each register is a 16-bit register containing a 16-bit word.
xxxCURCNT DMA Current Count Register
This group of registers include Rx0CURCNT, Rx1CURCNT, Tx0CURCNT, Tx1CURCNT,
and MASTCURCNT for each DSP core. Each register is a 16-bit register contain-
ing a 16-bit word.

ADSP-219x/2192 DSP Hardware Reference B-11
ADSP-2192 DSP Peripheral Registers
ADSP-2192 Peripheral Device Control
Registers
The following tables show the Peripheral Device Control Registers accessi-
ble by both DSP cores and the PCI and USB interfaces.
The following is a summary of the various classes of I/O registers and their
organization within DSP I/O pages.
LAddresses are 8-bit values. The Page is also an 8-bit value.
Table B-2. Register Group Descriptions
Page Addresses Descriptions Access
permitted by
Refer to
0x00 0x00-0x0F ADSP-2192 Chip Control
Registers
DSP / PCI / USB page B-13
0x10-0x1F General Purpose I/O
(GPIO) Control Registers
DSP / PCI / USB page B-24
0x20-0x2F Host Mailbox Registers DSP / PCI / USB page B-30
0x30 EEPROM Register DSP / PCI / USB page B-28
0xA0-0xBF JTAG ID Registers DSP Only page B-32
0xC0-0xFF AC’97 Controller Registers DSP / PCI / USB page B-41
0x01 0x00-0x2D CardBus Function Event
Registers
DSP / PCI page B-32
0x02-0x03 Reserved
0x04 0x00-0x7E AC’97 Codec Register
Space,
Primary Codec 0
DSP / PCI / USB page B-45

ADSP-2192 Peripheral Device Control Registers
B-12 ADSP-219x/2192 DSP Hardware Reference
0x05 0x00-0x7E AC’97 Codec Register
Space,
Secondary Codec 1
DSP / PCI / USB page B-45
0x06 0x00-0x7E AC’97 Codec Register
Space,
Secondary Codec 2
DSP / PCI / USB page B-46
0x07 Reserved
0x08 0x00-0x7F DMA Address, Count
Registers
DSP / PCI page B-46
0x80-0x87 DMA Control Registers DSP / PCI page B-46
0x88-0x8A PCI Interrupt, Control
Registers
DSP / PCI page B-47
0x09 0x00-0xFF PCI Configuration
Register Space, Function 0 DSP1/ PCI page B-56
0x0A 0x00-0xFF PCI Configuration
Register Space, Function 1 DSP1/ PCI page B-58
0x0B 0x00-0xFF PCI Configuration
Register Space, Function 2 DSP1/ PCI page B-59
0x0C 0x00-0x4F USB DSP Registers DSP / USB page B-71
0x0D-0xFF Reserved
1 PCI configuration spaces should be accessed only by the DSP, and only during the boot process.
After the PCI interface has been configured, bit 2 (ConfRdy) of the PCI_CFGCTL register
should be set by the DSP. This allows the PCI interface access to these registers while at the same
time denying the DSP access.
Table B-2. Register Group Descriptions (Continued)
Page Addresses Descriptions Access
permitted by
Refer to

ADSP-219x/2192 DSP Hardware Reference B-13
ADSP-2192 DSP Peripheral Registers
ADSP-2192 Chip Control Registers
The chip control registers provide support for the following:
•General status for the chip as a whole
•Power-down operations
•Other control functions
The following table lists the PDC register space. The register addresses
from PCI space, USB space, and DSP I/O space are listed.
Table B-3. ADSP-2192 Chip Control Registers
Register
Name
Description PCI
Address
USB
Address
DSP
I/O
Page
DSP
I/O
Address
SYSCON Chip Mode/Status 0x01-0x00 0x01-0x00 0x00 0x00
PWRCFG0 Function 0 Power
Management
0x03-0x02 0x03-0x02 0x00 0x02
PWRCFG1 Function 1 Power
Management
0x05-0x04 0x05-0x04 0x00 0x04
PWRCFG2 Function 2 Power
Management
0x07-0x06 0x07-0x06 0x00 0x06
PWRP0 DSP 0 Interrupt/Pow-
erdown
0x09-0x08 0x09-0x08 0x00 0x08
PWRP1 DSP 1 Interrupt/Pow-
erdown
0x0B-0x0A 0x0B-0x0A 0x00 0x0A
PLLCTL DSP PLL Control 0x0D-0x0C 0x0D-0x0C 0x00 0x0C

ADSP-2192 Peripheral Device Control Registers
B-14 ADSP-219x/2192 DSP Hardware Reference
Chip Control (SYSCON) Registers
1514131211109876543210
PCI RST VAUX PCI_5V B5V BUS<1:0> CRST<1:0> REGD VXPD VXPW ACVX XON RDIS Reserved RST
Table B-4. SYSCON Register Bit Descriptions
Bit Position Bit Name Description
0 RST Soft Chip Reset.
A write of 1 causes a soft reset to the ADSP-2192. A write of
0 has no effect. Always reads 0. Soft Reset affects the DSPs
and the GPIOs. Soft Reset does not affect the PCI, USB,
Mailboxes, AC’97, or EEPROM.
Note that the DSP memory pipeline (last 2 writes per bank) is
lost upon reset. If desired, it may be flushed by three writes
in a row to the same location.
Note: This bit resets to zero.
1 Reserved

ADSP-219x/2192 DSP Hardware Reference B-15
ADSP-2192 DSP Peripheral Registers
2 RDIS Reset Disable.
When 1, disables a PCI/ISA/CBUS bus reset from affecting
any portions of the ADSP-2192 except the bus interface
itself. When 0 (default), a bus reset causes the DSPs and
AC’97 subsystem to be reset.
Note: If RDIS is set, the DSP can detect that the bus is in
reset by the PCIRST bit in the CMSR register. Un-masked Bus
Reset affects the DSPs, the GPIOs, the AC’97, and the
PCI/USB interface.
Un-masked Bus Reset does not affect the Mailboxes or
EEPROM.
Note that the DSP memory pipeline (last 2 writes per bank) is
lost upon reset. If desired, it may be flushed by three writes
in a row to the same location.
Note: This bit resets to zero.
3 XON XTAL Force On.
When 1, causes the XTAL oscillator to run even if all other
subsystems are powered down. This permits access to the
on-chip control registers when the part is powered down. If
the chip and the XTAL oscillator are powered off, attempting
to write PDC registers including this one will result in power-
ing up the XTAL and setting the XON bit. The write will suc-
ceed, after a delay for the oscillator to stabilize. Subsequent
writes or reads should not be attempted until the oscillator
has stabilized, about 8K clocks or 333us.
When 0, the XTAL oscillator stops whenever it is not needed
by any on-chip subsystem.
Note: This bit resets to zero.
Table B-4. SYSCON Register Bit Descriptions (Continued)
Bit Position Bit Name Description

ADSP-2192 Peripheral Device Control Registers
B-16 ADSP-219x/2192 DSP Hardware Reference
4ACVXAC’97 External Devices Vaux Powered.
Controls the AC’97 interface during D3cold (RST asserted).
0 = Disable the interface (drive 0, disable all inputs). This is
used if external AC’97 devices are NOT powered
during d3cold, and protects the ADSP-2192 from
floating inputs and from outputs driving input clamps
on an external device. (default)
1 = Interface enabled during RST.
Note: This bit resets to zero.
5 Reserved Reserved
6 Reserved Reserved
7 REGD 2.5V Regulator Control Disable.
Disables the on-chip 2.5V Regulator controller when the
2.5V (IVDD) supply is derived from an external regulator (e.g.
in USB and Mini-PCI applications).
0 = On-Chip 2.5V Regulator Control Enabled. (default)
1 = On-Chip 2.5V Regulator Control Disabled.
Note: This bit resets to zero.
9:8 CRST<1:0> Chip Reset Source.
Indicates the source of the last reset to the chip (Read-Only)
00 = Power-On Reset
01 = Reserved.
10 = PCI/ISA/CBUS/USB bus interface hard reset
11 = Soft Reset from the CMSR:RST bit
Note: the fifth possible reset source, DIP Soft Reset, is
indicated by DIP1/2:RD = 1. Each DSP must check its
DIP<n>:RD bit and clear it to zero upon reset.
Table B-4. SYSCON Register Bit Descriptions (Continued)
Bit Position Bit Name Description

ADSP-219x/2192 DSP Hardware Reference B-17
ADSP-2192 DSP Peripheral Registers
11:10 BUS<1:0> Bus Mode.
Mode Pin status. Sampled at Power-On Reset (Read-Only).
00= PCI
01= CardBus
10= USB
11= Sub-ISA
12 B5V AC’97 5V level.
1= If the AC’97 interface is powered
from nominal 5V; 0 if nominal 3.3V.
13 PCI 5V PCI 5V level.
1= If the PCI/ISA/CBUS interface is powered from
nominal 5V; 0 if nominal 3.3V. Monitors the level
of the PCIVDD pins (Read Only).
14 Vaux Vaux Present.
1= If Vaux is currently powered (Read-Only).
15 PCIRST PCI Reset.
0= If PCI/CBUS/ISA RST is asserted (which may indi-
cate D3Cold powerdown state).
Note: This bit resets to one.
Table B-4. SYSCON Register Bit Descriptions (Continued)
Bit Position Bit Name Description

ADSP-2192 Peripheral Device Control Registers
B-18 ADSP-219x/2192 DSP Hardware Reference
Power Management Functions
Power management registers share the same bit specifications. Each regis-
ter corresponds to one of the PCI functions:
LAll bits in this register reset to zero.
1514 13:9 876543210
PME SPME
Reserved
PME EN
Reserved GPME APME
Reserved
PWRST[1:0]
Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2
Registers
Bit Position Bit Name Description
1:0 PWRST<1:0> PCI Function Power State.
Reports this function’s PCI Power Management state from its
PMCSR register in PCI Configuration Space. (Read Only)
4:2 Reserved
5APMEAC’97 Power Management Event Enable.
1= Enables setting this function’s PME bit upon
an AC’97 interrupt/wake event. (Read/Write)
6 GPME GPIO Power Management Event Enable.
1= Enables setting this function’s PME bit upon a
GPIO Wakeup event. (Read/Write)
7 Reserved Reserved
8 PME_EN Power Management Event Enable.
1= PME_EN bit is set in this function’s PMCSR
register in PCI Configuration space.
13:9 Reserved

ADSP-219x/2192 DSP Hardware Reference B-19
ADSP-2192 DSP Peripheral Registers
DSP Powerdown (PWRPx) Registers
These two registers share the following bit layout. One register corre-
sponds to each DSP.
LAll bits in this register reset to zero.
14 SPME Power Management Event (Set).
A write of 1 to this bit sets the PME bit for this
function. A write of 0 has no effect. Always
reads 0.
15 PME Power Management Event (Status/Clear).
1= A power management event has been detected for this
function. This is an alias of the PME bit in the Power
Management Control/Status Register in PCI Configura-
tion Space for this function. A write of 1 to this bit
clears PME.
0= A write of 0 has no effect.
1514131211109876543210
RINT GINT AINT PMINT RIEN GIEN AIEN PMIEN RWE GWE AWE PMWE FIEN RSTD PU PD
Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2
Registers (Continued)
Bit Position Bit Name Description

ADSP-2192 Peripheral Device Control Registers
B-20 ADSP-219x/2192 DSP Hardware Reference
Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions
Bit Position Bit Name Description
0PDDSPPowerDown.
When written to a 1, causes the DSP to power down (enter its
power-down handler). Can also be used to abort a power-up:
if the DSP is in the power-down handler after executing an
IDLE, writing a 1 will cause the DSP to immediately re-enter
the PowerDown interrupt handler after it executes the RTI.
When read, PD=1 indicates that this DSP is powered down:
either (a) it is in the powerdown handler and has executed an
IDLE instruction), and/or (b) the DSP Clock Generator
(PLL) is not running and stable. When both DSPs are pow-
ered down, the DSP Clock Generator is powered down, and
automatically restarts when either DSP wakes up.
Note: DSP memory cannot be accessed via PCI or USB when
the DSP is powered down. There is a delay after powering up
the DSPs with the PU bit during which memory reads must
not be performed, because the XTAL or the DSP PLL is not
yet running and stable. After powering up by writing a 1 to
the PU bit, the PD bit must be polled until it becomes 0, after
which the clock generator will be running and it is safe to
access DSP memory again.
1PUDSPPowerUp.
When written to a 1, causes the DSP to power up (exit the
IDLE within its power-down handler). Can also be used to
abort a powerdown: when written to 1 while the DSP is
within its powerdown handler prior to the IDLE, writing a 1
will cause execution to immediately continue through the
IDLE without stopping clocks.
When read, PU=1 indicates that this DSP is in the powerdown
interrupt handler, whether or not it has executed the power-
down IDLE.