Analog Devices Linear LTM 4700 User manual

LTM4700
1
Rev. B
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual 50A or Single 100A µModule Regulator
with Digital Power System Management
APPLICATIONS
n Dual 50A or Single 100A Digitally Adjustable Outputs with
Digital Interface for Control, Compensation and Monitoring
n Wide Input Voltage: 4.5V to 16V
n Output Voltage Range: 0.5V to 1.8V
n ~90% Full Load Efficiency from 12VIN to 1VOUT at 100A
n ±0.5% Maximum DC Output Error Over Temperature
n ±3% Current Readback Accuracy (25°C to 125°C)
n Integrated Input Current Sense Amplifier
n 400kHz PMBus-Compliant I2C Serial Interface
n Supports Telemetry Polling Rates Up to 125Hz
n Integrated 16-Bit ∆ΣADC
n Constant Frequency Current Mode Control
n Parallel and Current Share Multiple Modules
n 15mm × 22mm × 7.87mm BGA Package
Readable Data:
n Input and Output Voltages, Currents, and Temperatures
n Running Peak Values, Uptime, Faults and Warnings
n Internal EEPROM and Fault Logging with ECC
Writable Data and Configurable Parameters:
n Output Voltage, Voltage Sequencing and Margining
n Digital Soft-Start/Stop Ramp
n Optimize Analog Loop Compensation
n OV/UV/OT, UVLO, Frequency and Phasing
n System Optimization, Characterization and Data Min-
ing in Prototype, Production and Field Environments
n Telecom, Datacom, and Storage Systems
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,
7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
Dual 50A µModule Regulator with Digital Interface
for Control and Monitoring*
Efficiency vs Current at 12V Input
22µF
×8
ON/OFF CONTROL
FAULT INTERRUPTS,
POWER SEQUENCING
PWM CLOCK AND
TIME-BASE
SYNCHRONIZATION
VIN
5.75V TO 16V
VOSNS0–
VOSNS1–
VOUT0,
ADJUSTABLE
UP TO 50A
220µF
×8
VOSNS0+
VOUT0 VIN0
VIN1
SVIN LOAD0
VOUT1,
ADJUSTABLE
UP TO 50A
220µF
×8
I2C/SMBus I/F WITH
PMBus COMMAND SET
TO/FROM IPMI OR OTHER BOARD
MANAGEMENT CONTROLLER
LOAD1
RUN0
RUN1
WP
*FOR COMPLETE CIRCUIT, SEE FIGURE 46
LTM4700
GND
4700 TA01a
SGND
SCL
SDA
ALERT
VOSNS1+
VOUT1
FAULT0
FAULT1
REGISTER WRITE
PROTECTION
SYNC
SHARE_CLK
LOAD CURRENT (A)
0
70
EFFICIENCY (%)
85
80
90
95
10 20 30 50
4700 TA01b
75
40
100
1.5VOUT
1.0VOUT
The LTM
®
4700 is a dual 50A or single 100A step-down
µModule
®
(power module) DC/DC regulator featuring
remote configurability and telemetry-monitoring of power
managementparametersoverPMBus—anopenstandard
I2C-based digital interface protocol. The LTM4700 is
comprised of fast analog control loops, precision mixed-
signal circuitry, EEPROM, power MOSFETs, inductors and
supporting components. The LTM4700 product video is
available on website.
The LTM4700’s 2-wire serial interface allows outputs to
be margined, tuned and ramped up and down at program-
mable slew rates with sequencing delay times. Input and
outputcurrents and voltages, output power
,temperatures,
uptime and peak values are readable. Custom configura-
tion of the EEPROM contents is not required. At start-up,
output voltages, switching frequency, and channel phase
angle as-signments can be set by pin-strapping resistors.
The LTpowerPlay
®
GUI and DC1613 USB-to-PMBus con-
verter and demo kits are available.
The LTM4700 is offered in a 15mm × 22mm × 7.87mm
BGA package available with SnPb or RoHS compliant
terminal finish.
Click to view associated Video Design Idea.

LTM4700
2
Rev. B
For more information www.analog.com
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics ................................. 5
Typical Performance Characteristics .................. 12
Pin Functions .............................................. 15
Simplified Block Diagram ............................... 19
Decoupling Requirements............................... 19
Functional Diagram ...................................... 20
Test Circuits ............................................... 21
Operation................................................... 22
Power Module Introduction ...................................22
Power Module Overview, Major Features................22
EEPROM with ECC .................................................23
Power-Up and Initialization .................................... 24
Soft-Start ...............................................................25
Time-Based Sequencing ........................................25
Voltage-Based Sequencing ....................................25
Shutdown ..............................................................26
Light-Load Current Operation ................................26
Switching Frequency and Phase .............................27
PWM Loop Compensation .....................................27
Output Voltage Sensing .........................................27
INTVCC and Build-in 5V Bias Converter .................27
Output Current Sensing and Sub Milliohm
DCR Current Sensing .............................................28
Input Current Sensing ............................................28
PolyPhase Load Sharing ........................................28
External/Internal Temperature Sense .....................29
RCONFIG (Resistor Configuration) Pins .................29
Fault Detection and Handling .................................32
Status Registers and ALERT Masking ................33
Mapping Faults to FAU LT Pins ...........................35
Power Good Pins ...............................................35
CRC Protection ..................................................35
Serial Interface ......................................................35
Communication Protection ................................35
Device Addressing .................................................35
Responses to VOUT and IIN/IOUT Faults ..................36
Output Overvoltage Fault Response ..................36
Output Undervoltage Response .........................37
Peak Output Overcurrent Fault Response ..........37
Responses to Timing Faults ...................................37
Responses to VIN OV Faults ...................................37
Responses to OT/UT Faults ....................................37
Internal Overtemperature Fault Response .........37
External Overtemperature and
Undertemperature FaultResponse .................38
Responses to Input Overcurrent and Output
Undercurrent Faults ...............................................38
Responses to External Faults .................................38
Fault Logging .........................................................38
Bus Timeout Protection .........................................38
Similarity Between PMBus, SMBus and
I2C 2-Wire Interface ...............................................39
PMBus Serial Digital Interface ...............................39
Figures 7 to 24 PMBus Protocols ........................... 41
PMBus Command Summary ............................ 44
PMBus Commands ................................................44
Applications Information ................................ 50
VIN to VOUT Step-Down Ratios ...............................50
Input Capacitors ....................................................50
Output Capacitors ..................................................50
Light Load Current Operation .................................50
Switching Frequency and Phase ............................ 51
Output Current Limit Programming .......................52
Minimum On-Time Considerations .........................53
Variable Delay Time, Soft-Start and
Output Voltage Ramping ........................................53
Digital Servo Mode ................................................53
Soft Off (Sequenced Off) .......................................54
Undervoltage Lockout ............................................55
Fault Detection and Handling .................................55
Open-Drain Pins ....................................................55
Phase-Locked Loop and Frequency
Synchronization .....................................................56
Input Current Sense Amplifier ................................57

LTM4700
3
Rev. B
For more information www.analog.com
TABLE OF CONTENTS
Programmable Loop Compensation ......................57
Checking Transient Response ................................58
PolyPhase Configuration ...................................59
Connecting The USB to I2C/SMBus/
PMBus Controller to the LTM4700 In System ........59
LTpowerPlay: An Interactive GUI for Digital Power .60
PMBus Communication and Command
Processing .............................................................60
Thermal Considerations and Output
CurrentDerating ....................................................62
Applications Information-Derating Curves............ 68
EMI Performance ...................................................69
Safety Considerations ............................................69
Layout Checklist/Example .....................................69
Typical Applications ...................................... 71
PMBus Command Details ............................... 76
Addressing and Write Protect.................................76
General Configuration Commands..........................78
On/Off/Margin ........................................................79
PWM Configuration ................................................ 81
Voltage....................................................................84
Input Voltage and Limits.....................................84
Output Voltage and Limits..................................85
Output Current and Limits ......................................88
Input Current and Limits ....................................90
Temperature............................................................91
External Temperature Calibration........................91
Timing ....................................................................92
Timing—On Sequence/Ramp.............................92
Timing—Off Sequence/Ramp ............................93
Precondition for Restart .....................................94
Fault Response .......................................................94
Fault Responses All Faults..................................94
Fault Responses Input Voltage ...........................95
Fault Responses Output Voltage.........................95
Fault Responses Output Current.........................98
Fault Responses IC Temperature ........................99
Fault Responses External Temperature............. 100
Fault Sharing......................................................... 101
Fault Sharing Propagation ................................ 101
Fault Sharing Response.................................... 103
Scratchpad ........................................................... 103
Identification......................................................... 104
Fault Warning and Status...................................... 105
Telemetry...............................................................111
NVM Memory Commands .................................... 115
Store/Restore ................................................... 115
Fault Logging.................................................... 116
Block Memory Write/Read................................ 120
Typical Applications .................................... 121
Package Description ................................... 122
Revision History ........................................ 125
Package Photograph ................................... 126
Related Parts ............................................ 126

LTM4700
4
Rev. B
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Terminal Voltages:
VINn(Note 4), SVIN, IIN+, IIN−...................... –0.3V to 18V
SW0, SW1 .................. −1V to 18V, −5V to 25V Transient
VOUTn........................................................ –0.3V to 3.6V
INTVCC, VBIAS .............................................. –0.3V to 6V
VOSNS0+, VOSNS1+......................................... –0.3V to 6V
VOSNS0−, VOSNS1−...................................... –0.3V to 0.3V
RUNn, SDA, SCL, ALERT ........................... –0.3V to 5.5V
FSWPH_CFG, VOUTn_CFG, VTRIMn_CFG, ASEL...–0.3V to 2.75V
FAULTn, SYNC, SHARE_CLK, WP,
PGOOD0, PGOOD1.................................... −0.3V to 3.6V
(SVIN – IN+), (IIN+– IIN–)......................... –0.3V to +0.3V
COMPna, COMPnb, .................................. –0.3V to 2.7V
TSNS0a, TSNS1a...................................... –0.3V to 2.2V
TSNS0b, TSNS1b...................................... –0.3V to 0.8V
RUNP ........................................................ –0.3V to SVIN
Temperatures
Internal Operating Temperature Range
(Notes 2, 13, 17, 18)............................... –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature... 245°C
(Note 1)
BGA PACKAGE
330-PIN (15mm ×22mm ×7.87mm)
TJMAX = 125°C, θJCtop = 3.1°C/W, θJCbottom = 1°C/W, θJB = 1.75°C/W, θJA = 8.5°C/W
θVALUES DETERMINED PER JESD51-12
WEIGHT = 9.5g
TOP VIEW
5 6 7 8 9 10 11 12 13 141
GND GND GND
GND GND GND
GND
GND GND GND
GND VDD25 GND GND GND TSNS1b
VIN1
VIN0 VOUT0
VOUT1
VTRIM1_CFGVOUT1_CFG ASEL FAULT1 FAULT0 SDA
WP VTRIM0_CFG VOUT0_CFG
FSWPH_CFG RUN0 ALERT SCL
SHARE_CLK VDD33 GND GND RUN1 TSNS0a SYNC
VOSNS1–VOSNS1+SGND COMP0b GND GND
GND PGOOD1 GND GND GND COMP0a VOSNS0–
GND GND GND GND GND IIN–VOSNS0+
GND INTVCC GND GND IIN+PGOOD0
GND GND VBIAS GND GND TSNS0b
GND GND GND
GND GND GND
GND RUNP GND
SVIN GND GND
COMP1a COMP1b TSNS1a GND GND
GND GND GND
SW1
GND GND GND
GND GND GND
432 15
5 6 7 8 9 10 11 12 13 141 432 15
A
B
C
D
E
F
G
H
K
J
L
T
R
P
N
M
U
AB
AA
Y
W
V
GND GND GND
SW0
GND GND GND
ORDER INFORMATION
PART NUMBER PAD OR BALL FINISH
PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)DEVICE FINISH CODE
LTM4700EY#PBF SAC305 (RoHS) LTM4700Y e1 BGA 4 –40°C to 125°C
LTM4700IY#PBF LTM4700Y
LTM4700IY SnPb (63/37) LTM4700Y e0 BGA 4 –40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings

LTM4700
5
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN = 12V, RUNn = 3.3V,
FREQUENCY_SWITCH = 350kHz and VOUTncommanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input DC Voltage Test Circuit 1
Test Circuit 2; VIN_OFF < VIN_ON = 4V
l
l
5.75
4.5
16
5.75
V
V
VOUTnRange of Output Voltage Regulation VOUT0 Differentially Sensed on VOSNS0+/VOSNS0– Pin-Pair;
VOUT1 Differentially Sensed on VOSNS1+/VOSNS1– Pin-Pair;
Commanded by Serial Bus or with Resistors Present at
Start-Up on VOUTn_CFG
l
l
0.5
0.5
1.8
1.8
V
V
VOUTn(DC) Output Voltage, Total Variation with
Line and Load
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
VOUTnCommanded to 1.000V, VOUTnLow Range
(MFR_PWM_MODEn[1] = 1b) (Note 5)
l 0.995
0.985
1.000
1.000
1.005
1.015
V
V
VUVLO Undervoltage Lockout Threshold,
When VIN < 4.3V
VINTVCC Falling
VINTVCC Rising
3.55
3.90
V
V
Input Specifications
IINRUSH(VIN) Input Inrush Current at
Start-Up
Test Circuit 1, VOUTn=1V, VIN = 12V; No Load Besides
Capacitors; TON_RISEn= 3ms
100 mA
IQ(SVIN) Input Supply Bias Current Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
RUNn= 3.3V
Shutdown, RUN0 = RUN1 = 0V
50
25
mA
mA
IS(VINn,PSM) Input Supply Current in Pulse-
Skipping Mode Operation
Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b,
IOUTn= 100mA
20 mA
IS(VINn,FCM) Input Supply Current in Forced-
Continuous Mode Operation
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
IOUTn= 100mA
IOUTn= 50A
110
5.8
mA
A
IS(VINn,SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUNn= 0V 500 µA
Output Specifications
IOUTnOutput Continuous Current Range (Note 6) Utilizing MFR_PWM_MODE[7] = 1 and Using
~IOUT = 50A, Page 89
0 50 A
∆VOUTn(LINE)
VOUTn
Line Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
SVIN and VINnElectrically Shorted Together and INTVCC
Open Circuit;IOUTn= 0A, 5.0V ≤ VIN ≤ 16V, VOUT Low Range
(MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH =
350kHz (Note 5)
l
0.03
0.3 0.5
%/V
%/V
∆VOUTn(LOAD)
VOUTn
Load Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0A ≤ IOUTn≤ 50A, VOUT Low Range, (MFR_PWM_
MODEn[1] = 1b) (Note 5)
l
0.03
0.2 0.75
%
%
VOUTn(AC) Output Voltage Ripple 10 mVP-P
fS(Each Channel) VOUTnRipple Frequency FREQUENCY_SWITCH Set to 350kHz (0xFABC) l320 350 370 kHz
∆VOUTn(START) Turn-On Overshoot TON_RISEn= 3ms (Note 12) 8 mV
tSTART Turn-On Start-Up Time Time from VIN Toggling from 0V to 12V to Rising Edge
PGOODn. TON_DELAYn= 0ms, TON_RISEn= 3ms
l30 ms
tDELAY(0ms) Turn-On Delay Time Time from First Rising Edge of RUNnto Rising Edge of
PGOODn. TON_DELAYn= 0ms, TON_RISEn= 3ms,
VIN Having Been Established for at Least 70ms
l2.95 3.3 3.75 ms
∆VOUTn(LS) Peak Output Voltage Deviation for
Dynamic Load Step
Load: 0A to 12.5A and 12.5A to 0A at 10A/µs,
VOUTn= 1V, VIN = 12V (Note 12)
55 mV

LTM4700
6
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN = 12V, RUNn= 3.3V,
FREQUENCY_SWITCH = 350kHz and VOUTncommanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSETTLE Settling Time for Dynamic Load
Step
Load: 0A to 12.5A and 12.5A to 0A at 10A/µs,
VOUTn= 1V, VIN = 12V (Note 12)
50 µs
IOUTn(OCL_PK) Output Current Limit, Peak High
Range
Cycle-by-Cycle Inductor Peak Current Limit Inception,
Utilizing MFR_PWM_MODE[7] = 1, Using ~IOUT = 50A,
Page 89
60 A
IOUTn(OCL_AVG) Output Current Limit, Time
Averaged
Time-Averaged Output Inductor Current Limit Inception
Threshold, Commanded by IOUT_OC_FAULT_LIMITn (Note
12)
Utilizing MFR_PWM_MODE[7] = 1, Using ~IOUT = 50A,
Page 89
52A; See IO-RB-ACC
Specification (Output Current
Readback Accuracy)
Control Section
VFBCM0 Channel 0 Feedback Input Common
Mode Range
VOSNS0–Valid Input Range (Referred to SGND)
VOSNS0+Valid Input Range (Referred to SGND)
l
l
–0.1 0.3
3.6
V
V
VFBCM1 Channel 1 Feedback Input Common
Mode Range
VOSNS1–Valid Input Range (Referred to GND)
VOSNS1+Valid Input Range (Referred to SGND)
l
l
–0.3 0.3
3.6
V
V
VOUT-RNGL Full-Scale Command Voltage,
Range Low (0.6V to 2.75V, Notes
7, 15)
VOUTnCommanded to 2.750V, MFR_PWM_MODEn[1] = 1b
Set Point Accuracy
Resolution
LSB Step Size
2.7
−0.5
12
0.688
2.8
−0.5
V
%
Bits
mV
RVSNS0+VOSNS0+Impedance to SGND 0.05V ≤ VVOSNS0+– VSGND ≤ 1.8V 50 kΩ
RVSNS1+VOSNS1 Impedance to SGND 0.05V ≤ VVOSNS1 – VSGND ≤ 1.8V 50 kΩ
tON(MIN) Minimum On-Time (Note 8 ) 60 ns
Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)
NOV/UV_COMP Resolution, Output Voltage
Supervisors
(Notes 14, 15) 9 Bits
VOV-RNG Output OV Comparator Threshold
Detection Range
(Notes 14, 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
0.5
3.6
2.7
V
V
VOUSTP Output OV and UV Comparator
Threshold Programming LSB Step
Size
(Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
11.2
5.6
mV
mV
VOUT-RNGH Full-Scale Command Voltage,
Range Low (0.6V to 3.6V, Notes
7, 15)
VOUTnCommanded to 3.6V, MFR_PWM_MODEn[0] = 1b
Set Point Accuracy
Resolution
LSB Step Size
3.4
–0.5
12
1.375
3.6
–0.5
V
%
Bits
mV
gm0,1 Resolution
Error Amplifier gm(MAX)
Error Amplifier gm(MIN)
LSB Step Size
COMP0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7 3
5.76
1
0.68
Bits
mmho
mmho
mmho
RCOMP0,1 Resolution
Compensation Resistor RTH(MAX)
Compensation Resistor RTH(MIN)
MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, Note
Section)
5
62
0
Bits
kΩ
kΩ
VOV-ACC-0,1 Output OV Comparator Threshold
Accuracy Channel 0 and 1
(See Note 14)
1V ≤VVOSNS0+– VVOSNS0–≤ 1.8V, MFR_PWM_MODE0[1] = 1b
0.5V ≤ VVOSNS0+– VVOSNS0–< 1V, MFR_PWM_MODE0[1] = 1b
1V ≤ VVOSNS1+– VVOSNS1–≤ 1.8V, MFR_PWM_MODE1[1] = 1b
0.5V ≤ VVOSNS1+– VVOSNS1–< 1V, MFR_PWM_MODE1[1] = 1b
l
l
l
l
±1.5
±30
±1.5
±30
%
mV
%
mV
VUV-RNG Output UV Comparator Threshold
Detection Range (Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
0.5
3.6
2.7
V
V

LTM4700
7
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN = 12V, RUNn= 3.3V,
FREQUENCY_SWITCH = 350kHz and VOUTncommanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VUV-ACC Output UV Comparator Threshold
Accuracy (See Note 14)
1V ≤ VVOSNS0+– VVOSNS0–≤ 1.8V, MFR_PWM_MODE0[1] = 1b
0.5V ≤ VVSNS0+– VVSNS0–< 1V, MFR_PWM_MODE0[1] = 1b
1V ≤ VVOSNS1+– VVOSNS1–≤ 1.8V, MFR_PWM_MODE1[1] = 1b
0.5V ≤ VVOSNS1+– VVOSNS1–< 1V, MFR_PWM_MODE1[1] = 1b
l
l
l
l
±1.5
±30
±1.5
±30
%
mV
%
mV
tPROP-OV Output OV Comparator Response
Times
Overdrive to 10% Above Programmed Threshold 100 µs
tPROP-UV Output UV Comparator Response
Times
Under Drive to 10% Below Programmed Threshold 100 µs
Analog OV/UV SVIN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)
NSVIN-OV/UV-COMP SVIN OV/UV Comparator Threshold-
Programming Resolution
(Notes 14, 15) 9 Bits
SVIN-OU-RANGE SVIN OV/UV Comparator Threshold-
Programming Range
l4.5 18 V
SVIN-OU-STP SVIN OV/UV Comparator Threshold-
Programming LSB Step Size
(Note 15) 76 mV
SVIN-OU-ACC SVIN OV/UV Comparator Threshold
Accuracy
9V < SVIN ≤ 16V
4.5V ≤ SVIN ≤ 9V
l
l
±3
±225
%
mV
tPROP-SVIN-HIGH-VIN SVIN OV/UV Comparator Response
Time, High VIN Operating
Configuration
Test Circuit 1, and:
VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V
VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V
l
l
100
100
µs
µs
tPROP-SVIN-LOW-VIN SVIN OV/UV Comparator Response
Time, Low VIN Operating
Configuration
Test Circuit 2, and:
VIN_ON = 4.5V; SVIN Driven from 4.225V to 4.725V
VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V
l
l
100
100
µs
µs
Channels 0 and 1 Output Voltage Readback (READ_VOUTn)
NVO-RB Output Voltage Readback
Resolution and LSB Step Size
(Note 15) 16
244
Bits
µV
VO-F/S Output Voltage Full-Scale Digitizable
Range
VRUNn= 0V (Note 15) 8 V
VO-RB-ACC Output Voltage Readback Accuracy Channel 0: 1V ≤ VVOSNS0+ – VVOSNS0–≤ 1.8V
Channel 0: 0.5V ≤ VVOSNS0+– VVOSNS0–< 1V (Note 15)
Channel 1: 1V ≤ VVOSNS1+ – VVOSNS1–≤ 1.8V
Channel 1: 0.5V ≤ VVOSNS1+– VVOSNS1–< 1V
l
l
l
l
Within±0.5%of Reading
Within±5mVof Reading
Within±0.5%of Reading
Within±5mVof Reading
tCONVERT-VO-RB Output Voltage Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 15)
MFR_ADC_CONTROL Section
90
8
ms
ms
ms
Input Voltage (SVIN) Readback (READ_VIN)
NSVIN-RB Input Voltage Readback Resolution
and LSB Step Size
(Notes 10, 15) 10
15.625
Bits
mV
SVIN-F/S Input Voltage Full-Scale Digitizable
Range
(Notes 11, 15) 43 V
SVIN-RB-ACC Input Voltage Readback Accuracy READ_VIN, 4.5V ≤ SVIN ≤ 16V lWithin ±2% of Reading
tCONVERT-SVIN-RB Input Voltage Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 (Notes 9, 15)
90
8
ms
ms

LTM4700
8
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN = 12V, RUNn= 3.3V,
FREQUENCY_SWITCH = 350kHz and VOUTncommanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Channels0 and 1Output Current(READ_IOUTn), DutyCycle (READ_DUTY_CYCLEn),and ComputedInput Current (MFR_READ_IINn)Readback
NIO-RB Output Current Readback
Resolution and LSB Step Size
(Notes 10, 12) 10
34.1
Bits
mA
IO-F/S Output Current Full-Scale
Digitizable Range
(Note 12)
Utilizing MFR_PWM_MODE[7] = 1, Using ~IOUT = 50A,
Page 89
50 A
IO-RB-ACC Output Current, Readback Accuracy READ_IOUTn, Channels 0 and 1, 0 ≤ IOUTn≤ 50A,
Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 1b
(Note 19)
25°C to 125°C
–45°C to 125°C
l
Within 1.5A of Reading
Within 2.5A of Reading
IO-RB(50A) Full Load Output Current Readback IOUTn= 50A (Note 12). See Histograms in Typical
Performance Characteristics
50 A
tCONVERT-IO-RB Output Current Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x06 (CH0 IOUT) or 0x01 (CH1 IOUT)
(Notes 9, 15) See MFR_ADC_CONTROL SECTION
90
8
ms
ms
Input Current Readback
N Resolution (Note 10) 10 Bits
VIINSTP LSB Step Size Full-Scale Range =
16mV
LSB Step Size Full-Scale Range =
32mV
LSB Step Size Full-Scale Range =
64mV
Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV
Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV
Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV
15.26
30.52
61
µV
µV
µV
IIN_TUE Total Unadjusted Error Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–| VIN = 8V (Note 15)
Gain = 4, 4mV ≤ |VIIN+ – VIIN–| VIN = 8V (Note 15)
Gain = 2, 6mV ≤ |VIIN+ – VIIN–| VIN = 8V (Note 15)
l
l
l
±2
±1.3
±1.2
%
%
%
VOS Zero-Code Offset Voltage ±50 µV
tCONVERT Update Rate (Notes 9,15) See MFR_ADC_CONTROL SECTION for Faster
Update Rates
90 ms
Supply Current Readback
N Resolution (Note 10) 10 Bits
VICHIPSTP LSB Step Size Full-Scale Range =
256mV
Onboard 1Ω Resistor 244 µV
ICHIPTUE Total Unadjusted Error |VIIN+– VIN| ≤ 150mV l±3 %
tCONVERT Update Rate (Notes 9,15) See MFR_ADC_CONTROL SECTION for Faster
Update Rates
90 ms
Temperature Readback (T0, T1)
TRES-RB Temperature Readback Resolution Channel 0, Channel 1, and Controller (Note 15) 0.25 °C
T0_TUE External Temperature Total
Unadjusted Readback Error
Supporting Only ∆VBE Sensing
3 °C
°C
T1_TUE Internal TSNS TUE VRUN0,1 = 0.0, fSYNC = 0kHz (Note 15) ±1 °C
tCONVERT Update Rate (Note 9)
MFR_ADC_CONTROL = 0x04 or 0x0C (Notes 9, 15)
90
8
ms
ms

LTM4700
9
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN = 12V, RUNn= 3.3V,
FREQUENCY_SWITCH = 350kHz and VOUTncommanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Regulator
VINTVCC Internal VCC Voltage No Load 6V ≤ VIN ≤ 16V 5.25 5.5 5.75 V
VLDO_INT INTVCC Load Regulation ICC = 0mA to 20mA, 6V ≤ VIN ≤ 16V 0.5 ±2 %
VBIAS Internal Bias Regulation 7V ≤ VIN ≤ 16V 5 V
VDD33 Regulator
VVDD33 Internal VDD33 Voltage 4.5V < VINTVCC 3.2 3.3 3.4 V
ILIM VDD33 Current Limit VDD33 = GND, VIN = INTVCC = 4.5V 100 mA
VVDD33_OV VDD33 Overvoltage Threshold 3.5 V
VVDD33_UV VDD33 Undervoltage Threshold 3.1 V
VDD25 Regulator
VVDD25 Internal VDD25 Voltage 2.5 V
ILIM VDD25 Current Limit VDD25 = GND, VIN = INTVCC = 4.5V 80 mA
Oscillator and Phase-Locked Loop (PLL)
fRANGE PLL SYNC Range Synchronized with Falling Edge of SYNC l200 1000 kHz
fOSC Oscillator Frequency Accuracy Frequency Switch = 500kHz l±7.5 %
VTH(SYNC) SYNC Input Threshold VSYNC Falling
VSYNC Rising
1
1.5
V
V
VOL(SYNC) SYNC Low Output Voltage ILOAD = 3mA 0.2 0.4 V
ILEAK(SYNC) SYNC Leakage Current in Slave
Mode
0V ≤ VPIN ≤ 3.6V ±5 µA
θSYNC-θ0 SYNC to Ch0 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG0
MFR_PWM_CONFIG[2:0] = 0,2,3
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
0
60
90
120
Deg
Deg
Deg
Deg
θSYNC-θ1 SYNC to Ch1 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG1
MFR_PWM_CONFIG[2:0] = 3
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
EEPROM Characteristics
Endurance (Note 13) 0°C ≤ TJ≤ 85°C During EEPROM Write Operations l10,000 Cycles
Retention (Note 13) TJ< 125°C l10 Years
Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ< 85°C
During EEPROM Write Operation
440 4100 ms
Leakage Current SDA, SCL, ALERT, RUN
IOL Input Leakage Current OV ≤ VPIN ≤ 5.5V l±5 µA
Leakage Current FAULTn, PGOODn
IGL Input Leakage Current OV ≤ VPIN ≤ 3.6V l±2 µA
Digital Inputs SCL, SDA, RUNn, GPI0n
VIH Input High Threshold Voltage l1.35 V
VIL Input Low Threshold Voltage l0.8 V
VHYST Input Hysteresis SCL, SDA 0.08 V
CPIN Input Capacitance 10 pF

LTM4700
10
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA= 25°C, VIN = 12V, RUNn= 3.3V,
FREQUENCY_SWITCH = 350kHz and VOUTncommanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Input WP
IPUWP Input Pull-Up Current WP 10 µA
Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn
VOL Output Low Voltage ISINK = 3mA 0.4 V
Digital Inputs SHARE_CLK, WP (Note 15)
VIH Input High Threshold Voltage l1.5 1.8 V
VIL Input Low Threshold Voltage l0.6 1 V
Digital Filtering of FAULTn(Note 15)
IFLTG Input Digital Filtering FAULTn3 µs
Digital Filtering of PGOODn(Note 15)
IFLTG Output Digital Filtering PGOODn100 µs
Digital Filtering of RUNn(Note 15)
IFLTG Input Digital Filtering RUN 10 µs
PMBus Interface Timing Characteristics (Note 15)
fSCL Serial Bus Operating Frequency l10 400 kHz
tBUF Bus Free Time Between Stop and
Start
l1.3 µs
tHD(STA) Hold Time After Repeated Start
Condition After This Period, the
First Clock is Generated
l0.6 µs
tSU(STA) Repeated Start Condition Setup
Time
l0.6 10000 µs
tSU(ST0) Stop Condition Setup Time l0.6 µs
tHD(DAT) Date Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3 0.9
µs
µs
tSU(DAT) Data Setup Time
Receiving Data 0.1 µs
tTIMEOUT_SMB Stuck PMBus Timer Non-Block
Reads
Stuck PMBus Timer Block Reads
Measured from the Last PMBus Start Event 32
255
ms
tLOW Serial Clock Low Period l1.3 10000 µs
tHIGH Serial Clock High Period l0.6 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:The LTM4700 is tested under pulsed-load conditions such that
TJ≈TA. The LTM4700E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4700I is guaranteed to meet specifications over the full
–40°C to 125°C internal operating temperature range. TJis calculated from
the ambient temperature TAand the power dissipation PD according to the
formula:
TJ=TA+ (PD•θJA)
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.