Analog Devices AD9843A User manual

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no res onsibility is assumed by Analog Devices for its
use, nor for any infringements of atents or other rights of third arties
which may result from its use. No license is granted by im lication or
otherwise under any atent or atent rights of Analog Devices.
a
AD9843A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U. .A.
Tel: [phone] World Wide Web ite: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000
Complete 10-Bit 20 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHP
BANDGAP
REFERENCE
2:1
MUX DOUT
AUX2IN
CLPDM
CCDIN
OFFSET
DAC
PBLK
AUX1IN
VRT
VRB
INTERNAL
TIMING
INTERNAL
BIAS
2dB~36dB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
10
8
CML
DIGITAL
INTERFACE
SDATASCK
SL
CLPOB
10
CDS
VGA
CLP
BUF
2:1
MUX
CLP
AD9843A
4dB6dB
INTERNAL
REGISTERS
CLP
10-BIT
ADC
6
FEATURE
20 M P Correlated Double ampler (CD )
4 dB  6 dB Variable CD Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 20 M P A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire erial Digital Interface
3 V ingle upply Operation
Low Power: 65 mW @ 2.7 V upply
48-Lead LQFP Package
APPLICATION
Digital till Cameras
Digital Video Camcorders
PC Cameras
PRODUCT DESCRIPTION
The AD9843A is a complete analog signal processor for CCD
applications. It features a 20 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9843A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, input configuration, and power-
down modes.
The AD9843A operates from a single 3 V power supply, typi-
cally dissipates 78 mW, and is packaged in a 48-lead LQFP.

–2– REV. 0
AD9843A–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating –20 +85 °C
Storage –65 +150 °C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver 2.7 3.6 V
POWER CONSUMPTION
Normal Operation (Specified Under Each Mode of Operation)
Power-Down Modes
Fast Recovery Mode 45 mW
Standby 5 mW
Total Power-Down 1 mW
MAXIMUM CLOCK RATE 20 MHz
A/D CONVERTER
Resolution 10 Bits
Differential Nonlinearity (DNL) ±0.4 ±1.0 LSB
No Missing Codes 10 Bits Guaranteed
Full-Scale Input Voltage 2.0 V
Data Output Coding Straight Binary
VOLTAGE REFERENCE
Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA V
OH
2.2 V
Low Level Output Voltage, I
OL
= 2 mA V
OL
0.5 V
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
(DRVDD = 2.7 V, CL= 20 pF unless otherwise noted.)

–3–
REV. 0
AD9843A
Parameter Min Typ Max Unit Notes
P OWER CONSUMPTION 78 mW See TPC 1 for Power Curves
MAXIMUM CLOCK RATE 20 MHz
CDS
Allowable CCD Reset Transient
1
500 mV See Input Waveform in Note 1
Max CCD Black Pixel Amplitude
1
200 mV
Max Input Range Before Saturation
1
1.0 V p-p With 4 dB CDS Gain
Max Input Range Before Saturation 1.5 V p-p With –2 dB CDS Gain
Max Input Range Before Saturation 0.5 V p-p With 10 dB CDS Gain
Max Output Range 1.6 V p-p At Any CDS Gain Setting
Gain Resolution 64 Steps
Gain Range (Two’s Complement Coding) See Figure 12 for CDS Gain Curve
Min Gain (CDS Gain Register Code 32) –2 dB
Medium Gain (CDS Gain Code 63) 4 dB 4 dB Is Default with CDS Gain Disabled
Max Gain (CDS Gain Code 31) 10 dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range See Figure 13 for VGA
Gain Curve
Low Gain (VGA Register Code 91) 2 dB See Page 13 for Gain Equations
Max Gain (VGA Code 1023) 36 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output
Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB
SYSTEM PERFORMANCE Specifications Include Entire Signal Chain
Gain Accuracy, VGA Code 91 to 1023 –0.5 +0.5 dB Use Equations on Page 13 to Calculate Gain
Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied (4 dB CDS Gain)
Peak Nonlinearity, 800 mV Input Signal 0.4 % 8 dB Gain Applied (4 dB CDS Gain)
Total Output Noise 0.2 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply
POWER-UP RECOVERY TIME Clocks Must Be Applied, as in Figures 5 and 6
From Fast Recovery Mode 0.1 ms
From Reference Standby Mode 1 ms
From Total Shutdown Mode 3 ms
From Power-Off Condition 15 ms
NOTES
1
Input Signal Characteristics defined as follows, with 4 dB CDS gain:
1V MAX
INPUT
SIGNAL RANGE
200mV MAX
OPTICAL
BLACK PIXEL
500mV TYP
RESET
TRANSIENT
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless otherwise noted.)

–4– REV. 0
AD9843A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 60 mW
MAXIMUM CLOCK RATE 20 MHz
INPUT BUFFER
Gain 0dB
Max Input Range 1.0 V p-p
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 1023 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 36 dB
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 60 mW
MAXIMUM CLOCK RATE 20 MHz
INPUT BUFFER (Same as AUX1-MODE)
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 512 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 18 dB
ACTIVE CLAMP
Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)
Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB
Specification subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)

AD9843A
–5–
REV. 0
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
48 50 ns
DATACLK High/Low Pulsewidth t
ADC
20 25 ns
SHP Pulsewidth t
SHP
712.5 ns
SHD Pulsewidth t
SHD
712.5 ns
CLPDM Pulsewidth t
CDM
4 10 Pixels
CLPOB Pulsewidth
1
t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
012.5 ns
SHP Rising Edge to SHD Rising Edge t
S2
20 25 ns
Internal Clock Delay t
ID
3.0 ns
Inhibited Clock Period t
INH
10 ns
DATA OUTPUTS
Output Delay t
OD
14.5 16 ns
Output Hold Time t
H
7.0 7.6 ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
NOTES
1
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9843A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
(CL= 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter To Min Max Unit
AVDD1, AVDD2 AVSS –0.3 +3.9 V
DVDD1, DVDD2 DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V
BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C
(10 sec)
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9843AJST –20°C to +85°C Thin Plastic ST-48
Quad Flatpack
(LQFP)
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 92°C
WARNING!
ESD SENSITIVE DEVICE

AD9843A
–6– REV. 0
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
(LSB) D0
D1
D2
D3
D4
NC = NO CONNECT
D5
D6
D7
D8
BYP2
BYP1
AVDD1
AVSS
AD9843A
(MSB) D9 AVSS
SCK SDATA SL NC STBY NC THREE-STATE DVSS DVDD2 VRB VRT CML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
DVSS
PBLK
CLPOB
SHP
SHD
CLPDM
DVSS
DRVSS
DRVSS
PIN FUNCTION DESCRIPTIONS
Pin Number Name Type Description
1, 2 DRVSS P Digital Driver Ground
3–12 D0–D9 DO Digital Data Outputs
13 DRVDD P Digital Output Driver Supply
14 DRVSS P Digital Output Driver Ground
15, 18, 24, 41 DVSS P Digital Ground
16 DATACLK DI Digital Data Output Latch Clock
17 DVDD1 P Digital Supply
19 PBLK DI Preblanking Clock Input
20 CLPOB DI Black Level Clamp Clock Input
21 SHP DI CDS Sampling Clock for CCD’s Reference Level
22 SHD DI CDS Sampling Clock for CCD’s Data Level
23 CLPDM DI Input Clamp Clock Input
25, 26, 35 AVSS P Analog Ground
27 AVDD1 P Analog Supply
28 BYP1 AO Internal Bias Level. Decoupling
29 BYP2 AO Internal Bias Level Decoupling
30 CCDIN AI Analog Input for CCD Signal
31 NC NC Leave Floating or Decouple to Ground with 0.1 ␮F
32 BYP4 AO Internal Bias Level Decoupling
33 AVDD2 P Analog Supply
34 AUX2IN AI Analog Input
36 AUX1IN AI Analog Input
37 CML AO Internal Bias Level Decoupling
38 VRT AO A/D Converter Top Reference Voltage Decoupling
39 VRB AO A/D Converter Bottom Reference Voltage Decoupling
40 DVDD2 P Digital Supply
42 THREE-STATE DI Digital Output Disable. Active High
43 NC NC May be tied High or Low. Should not be left floating.
44 STBY DI Standby Mode, Active High. Same as Serial Interface Standby Mode
45 NC NC Internally Not Connected. May be Tied High or Low
46 SL DI Serial Digital Interface Load Pulse
47 SDATA DI Serial Digital Interface Data
48 SCK DI Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

AD9843A
–7–
REV. 0
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to
the peak deviation of the output of the AD9843A from a true
straight line. The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined
as a Level 1, 1/2 LSB beyond the last code transition. The devia-
tion is measured from the middle of each particular output
code to the true straight line. The error is then expressed as a
percentage of the 2 V ADC full-scale signal. The input signal is
always appropriately gained up to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
N
codes) when N is the bit resolution of the
ADC. For the AD9843A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9843A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9843A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
330
DVDD
DVSS
Figure 1. Digital In uts—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DVSS DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Data Out uts
ACVDD
ACVSS ACVSS
Figure 3. CCDIN (Pin 30)
330
DVDD
DVDD
DVSS
DATA IN
RNW
DATA OUT
DVSS
DVSS
Figure 4. SDATA (Pin 47)

AD9843A
–8– REV. 0
SAMPLE RATE – MHz
100
70
40
52010
POWER DISSIPATION – mW
50
60
80
90
15
V
DD
= 3.3V
V
DD
= 3.0V
V
DD
= 2.7V
TPC 1. Power vs. Sam le Rate
01000 400200 600 800
0
–0.5
0.5
0.25
–0.25
TPC 2. Ty ical DNL Performance
–Typical Performance Characteristics
VGA GAIN CODE –LSB
4
2
0
01000 400
OUTPUT NOISE –LSB
200
1
600
3
800
TPC 3. Out ut Noise vs. VGA Gain

AD9843A
–9–
REV. 0
CCD-MODE AND AUX-MODE TIMING
N–10 N–9N–8N–1N
N N+1 N+2 N+9 N+10
t
ID
t
ID
t
S1
t
S2
t
CP
t
INH
t
OD t
H
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
Figure 5. CCD-Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
Figure 6. Ty ical CCD-Mode Line Clam Timing
DATACLK
OUTPUT
DATA
VIDEO
SIGNAL
NN+1
N+2
N+8
N+9
N–10 N–9N–8N–1N
tID
tCP
tOD tH
Figure 7. AUX-Mode Timing

AD9843A
–10– REV. 0
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register Address Data Bits
Name A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Operation 0 0 0 Channel Select Power-Down Software OB Clamp 0*1** 0*0*0*
CCD/AUX Modes Reset On/Off
VGA Gain 1 0 0 LSB MSB X
Clamp Level 0 1 0 LSB MSB X X X
Control 1 1 0 0*0*0*CDS Gain Clock Polarity Select for 0*0*Three- X
On/Off SHP/SHD/CLP/DATA State
CDS Gain 0 0 1 LSB MSB X X X X X
*
Internal use only, must be set to zero. **Should be set to one.
SDATA
SCK
SL
RNW TEST
0A2 0
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS tDH
tLS tLH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 8. Serial Write O eration
SDATA
SCK
SL
RNW TEST
10
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK
FALLING EDGES.
t
DV
A2
Figure 9. Serial Readback O eration
SDATA
SCK
SL
A0 A1
D0 D2 D3 D10
RNW
00 D9 000 D0
12173534
27
26166543 44
...
...
... ...
10 BITS
AGC GAIN
D7 D0 D9
...
...
... ... ...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING
ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
8 BITS
CLAMP LEVEL
10 BITS
CONTROL
11 BITS
OPERATION
D1 D0 D2 D3D1
18 19 20789
Figure 10. Continuous Serial Write O eration to Multi le Registers