Analog Devices ADAU1961 User manual

Stereo, Low Power, 96 kHz, 24-Bit
Audio Codec with Integrated PLL
ADAU1961
Rev. 0
Information furnished by Analo
responsibility is assumed by Ana
rights of third parties that may re
license is granted by implication
Trademarks and registered trad
MA 02062-9106, U.S.A.
www.analog.com
Inc. All rights reserved.
g Devices is believed to be accurate and reliable. However, no
log Devices for its use, nor for any infringements of patents or other
sult from its use. Specifications subject to change without notice. No
or otherwise under any patent or patent rights of Analog Devices.
emarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood,
Tel: [phone]
Fax: [phone] ©2010 Analog Devices,
FEATURES
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 17 mW record, 18 mW playback, 48 kHz
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
Analog and digital I/O: 3.3 V
I2C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
32-lead, 5 mm × 5 mm LFCSP
−40°C to +105°C operating temperature range
Qualified for automotive applications
APPLICATIONS
Automotive head units
Automotive amplifiers
Navigation systems
Rear-seat entertainment systems
GENERAL DESCRIPTION
The ADAU1961 is a low power, stereo audio codec that supports
stereo 48 kHz record and playback at 35 mW from a 3.3 V analog
supply. The stereo audio ADCs and DACs support sample rates
from 8 kHz to 96 kHz as well as a digital volume control.
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1961 includes a stereo digital microphone input.
The ADAU1961 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
The serial control bus supports the I2C and SPI protocols. The
serial audio bus is programmable for I2S, left-/right-justified,
and TDM modes. A programmable PLL supports flexible clock
generation for all standard integer rates and fractional master
clocks from 8 MHz to 27 MHz.
FUNCTIONAL BLOCK DIAGRAM
CM IOVDD DGND DVDDOUT AGND AVDD AVDD AGND
HP JACK
DETECTION REGULATOR
INPUT
MIXERS
ALC
MICROPHONE
BIAS PLL
LINN
LINP
LAUX
JACKDET/MICIN
RINP
RINN
RAUX
LHP
LOUTN
LOUTP
ADAU1961
RHP
MONOOUT
ROUTP
ROUTN
MICBIAS
OUTPUT
MIXERS
DAC
ADC
DIGITAL
FILTERS
DAC
DIGITAL
FILTERS
ADC DAC
ADC
I
2
C/SPI
CONTROL PORT
SERIAL DATA
INPUT/OUTPUT PORTS
K
SDA/
COUT
MCLK ADC_SDATA
BCL
SCL/
CCLK
ADDR1/
CDATA
ADDR0/
CLATCH
LRCL
DAC_SDATA
K
0
8915-001
Figure 1.
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ADAU1961
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Performance Specifications, TA= 25°C ....................... 3
Analog Performance Specifications, −40°C < TA< +105°C ... 5
Power Supply Specifications........................................................ 7
Digital Filters................................................................................. 8
Digital Input/Output Specifications........................................... 8
Digital Timing Specifications ..................................................... 9
Digital Timing Diagrams........................................................... 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 15
System Block Diagrams ................................................................. 18
Theory of Operation ...................................................................... 21
Startup, Initialization, and Power................................................. 22
Power-Up Sequence ................................................................... 22
Power Reduction Modes............................................................ 22
Digital Power Supply.................................................................. 22
Input/Output Power Supply...................................................... 22
Clock Generation and Management........................................ 22
Clocking and Sampling Rates ....................................................... 24
Core Clock................................................................................... 24
Sampling Rates............................................................................ 24
PLL ............................................................................................... 25
Record Signal Path ......................................................................... 27
Input Signal Paths....................................................................... 27
Analog-to-Digital Converters................................................... 29
Automatic Level Control (ALC)................................................... 30
ALC Parameters.......................................................................... 30
Noise Gate Function .................................................................. 31
Playback Signal Path ...................................................................... 33
Output Signal Paths ................................................................... 33
Headphone Output .................................................................... 34
Pop-and-Click Suppression ...................................................... 35
Line Outputs ............................................................................... 35
Control Ports................................................................................... 36
Burst Mode Writing and Reading ............................................ 36
I2C Port ........................................................................................ 36
SPI Port ........................................................................................ 39
Serial Data Input/Output Ports .................................................... 40
Applications Information .............................................................. 42
Power Supply Bypass Capacitors.............................................. 42
GSM Noise Filter ........................................................................ 42
Grounding................................................................................... 42
Exposed Pad PCB Design ......................................................... 42
Control Registers ............................................................................ 43
Control Register Details ............................................................ 44
Outline Dimensions....................................................................... 75
Ordering Guide .......................................................................... 75
Automotive Products................................................................. 75
REVISION HISTORY
10/10—Revision 0: Initial Version
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ADAU1961
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SPECIFICATIONS
Supply voltage (AVDD) = 3.3 V, TA= 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fSmode), input sample rate = 48 kHz, measurement
bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V,
unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase
deviation specifications.
ANALOG PERFORMANCE SPECIFICATIONS, TA= 25°C
IOVDD = 3.3 V ± 10%.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS ADC performance excludes mixers
and PGA
ADC Resolution All ADCs 24 Bits
Digital Attenuation Step 0.375 dB
Digital Attenuation Range 95 dB
INPUT RESISTANCE
Single-Ended Line Input −12 dB gain 80.4 kΩ
0 dB gain 21 kΩ
6 dB gain 10.5 kΩ
PGA Inverting Inputs −12 dB gain 84.5 kΩ
0 dB gain 53 kΩ
35.25 dB gain 1.7 kΩ
PGA Noninverting Inputs All gains 105 kΩ
SINGLE-ENDED LINE INPUT
Full-Scale Input Voltage (0 dB) 1.0 (2.83) V rms (V p-p)
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 83.5 99 dB
No Filter (RMS) 83 96 dB
Total Harmonic Distortion + Noise −1 dBFS −90 −71 dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS) 99 dB
No Filter (RMS) 96 dB
Input Mixer Gain per Step −12 dB to +6 dB range 2.89 3 3.07 dB
Mute Attenuation LINPG[2:0], LINNG[2:0] = 000,
RINPG[2:0], RINNG[2:0] = 000,
MX1AUXG[2:0], MX2AUXG[2:0] = 000
−85.5 −77 dB
Interchannel Gain Mismatch −0.3 +0.032 +0.3 dB
Offset Error −5 0 +5 mV
Gain Error −17 −12 −8 %
Interchannel Isolation 68 dB
Power Supply Rejection Ratio CM capacitor = 20 F, 100 mV p-p @ 1 kHz 67 dB
PSEUDO-DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB) 1.0 (2.83) V rms (V p-p)
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 94 98 dB
No Filter (RMS) 91 95 dB
Total Harmonic Distortion + Noise −1 dBFS −89 −83 dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS) 98 dB
No Filter (RMS) 95 dB
PGA Boost Gain Error 20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−8 +0.4 +8 dB
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Parameter Test Conditions/Comments Min Typ Max Unit
Mute Attenuation PGA muted
LDMUTE, RDMUTE = 0 −76 −73 dB
RDBOOST[1:0], LDBOOST[1:0] = 00 −87 −82 dB
Interchannel Gain Mismatch −0.6 −0.073 +0.6 dB
Offset Error −6 0 +6 mV
Gain Error −24 −14 −3 %
Interchannel Isolation 83 dB
Common-Mode Rejection Ratio 100 mV rms, 1 kHz −58 dB
100 mV rms, 20 kHz −52 −48 −44 dB
FULL DIFFERENTIAL PGA INPUT Differential PGA inputs
Full-Scale Input Voltage (0 dB) 1.0 (2.83) V rms (V p-p)
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 94 98 dB
No Filter (RMS) 91 95 dB
Total Harmonic Distortion + Noise −1 dBFS −78 −74 dB
Signal-to-Noise Ratio
With A-Weighted Filter (RMS) 98 dB
No Filter (RMS) 95 dB
PGA Boost Gain Error 20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−8 −0.15 +8 dB
Mute Attenuation PGA muted
LDMUTE, RDMUTE = 0 −76 −73 dB
RDBOOST[1:0], LDBOOST[1:0] = 00 −87 −82 dB
Interchannel Gain Mismatch −0.3 −0.0005 +0.3 dB
Offset Error −6 0 +6 mV
Gain Error −17 −14 −9 %
Interchannel Isolation 83 dB
Common-Mode Rejection Ratio 100 mV rms, 1 kHz −58 dB
100 mV rms, 20 kHz −52 −48 −44 dB
MICROPHONE BIAS MBIEN = 1
Bias Voltage
0.65 × AVDD MBI = 1, MPERF = 0 2.00 2.145 2.19 V
MBI = 1, MPERF = 1 2.04 2.13 2.21 V
0.90 × AVDD MBI = 0, MPERF = 0 2.89 2.97 3.04 V
MBI = 0, MPERF = 1 2.89 2.99 3.11 V
Bias Current Source MBI = 0, MPERF = 1 3 mA
Noise in the Signal Bandwidth 1 kHz to 20 kHz
MBI = 0, MPERF = 0 42 nV/√Hz
MBI = 0, MPERF = 1 85 nV/√Hz
MBI = 1, MPERF = 0 25 nV/√Hz
MBI = 1, MPERF = 1 13 22 36 nV/√Hz
DIGITAL-TO-ANALOG CONVERTERS DAC performance excludes mixers and
headphone amplifier
DAC Resolution All DACs 24 Bits
Digital Attenuation Step 0.375 dB
Digital Attenuation Range 95 dB
DAC TO LINE OUTPUT
Full-Scale Output Voltage (0 dB) 0.92 (2.60) V rms (V p-p)
Dynamic Range 20 Hz to 20 kHz, −60 dBFS input, line
output mode
With A-Weighted Filter (RMS) 95 101 dB
No Filter (RMS) 93.5 98 dB
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Parameter Test Conditions/Comments Min Typ Max Unit
Total Harmonic Distortion + Noise 0 dBFS, 10 kΩ load
Line Output Mode −92 −77 dB
Headphone Output Mode −89 −79 dB
Signal-to-Noise Ratio Line output mode
With A-Weighted Filter (RMS) 101 dB
No Filter (RMS) 98 dB
Mute Attenuation
Mixer 3 and Mixer 4 Muted MX3RM, MX3LM, MX4RM, MX4LM = 0,
MX3AUXG[3:0], MX4AUXG[3:0] = 0000,
MX3G1[3:0], MX3G2[3:0] = 0000,
MX4G1[3:0], MX4G2[3:0] = 0000
−85 −78 dB
Mixer 5, Mixer 6, and Mixer 7 Muted MX5G3[1:0], MX5G4[1:0], MX6G3[1:0],
MX6G4[1:0], MX7[1:0] = 00
−89 −80 dB
All Volume Controls Muted LOUTM, ROUTM = 0 −82 −74 dB
MONOM, LHPM, RHPM = 0 −74 −69 dB
Interchannel Gain Mismatch −0.3 −0.005 +0.3 dB
Offset Error −22 0 +22 mV
Gain Error −10 +3 +10 %
Interchannel Isolation 1 kHz, 0 dBFS input signal 100 dB
Power Supply Rejection Ratio CM capacitor = 20 F, 100 mV p-p @ 1 kHz 70 dB
DAC TO HEADPHONE/EARPIECE
OUTPUT
LOUTx, ROUTx, LHP, RHP in headphone
output mode; PO= output power per
channel
Full-Scale Output Voltage (0 dB) Scales linearly with AVDD 0.92 (2.60) V rms (V p-p)
Total Harmonic Distortion + Noise −4 dBFS, 16 Ω load, PO= 21.1 mW −82 dB
−4 dBFS, 32 Ω load, PO= 10.6 mW −82 dB
Capless Headphone Mode −2 dBFS, 16 Ω load −78 −71 dB
−2 dBFS, 32 Ω load −75 −65 dB
Headphone Output Mode 0 dBFS, 10 kΩ load −86 −77 dB
Interchannel Isolation 1 kHz, 0 dBFS input signal, 32 Ω load
Referred to GND 73 dB
Referred to CM (capless headphone
mode)
50 dB
Power Supply Rejection Ratio CM capacitor = 20 F, 100 mV p-p @ 1 kHz 67 dB
REFERENCE
Common-Mode Reference Output CM pin 1.62 1.65 1.67 V
ANALOG PERFORMANCE SPECIFICATIONS, −40°C < TA< +105°C
IOVDD = 3.3 V ± 10%.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
SINGLE-ENDED LINE INPUT
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 74 dB
No Filter (RMS) 71 dB
Total Harmonic Distortion + Noise −1 dBFS −67 dB
Input Mixer Gain per Step −12 dB to +6 dB range 2.88 3.09 dB
Mute Attenuation LINPG[2:0], LINNG[2:0] = 000,
RINPG[2:0], RINNG[2:0] = 000,
MX1AUXG[2:0], MX2AUXG[2:0] = 000
−77 dB
Interchannel Gain Mismatch −0.5 +0.5 dB
Offset Error −5 +5 mV
Gain Error −22 −6 %
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Parameter Test Conditions/Comments Min Typ Max Unit
PSEUDO-DIFFERENTIAL PGA INPUT
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 94 dB
No Filter (RMS) 91 dB
Total Harmonic Distortion + Noise −1 dBFS −75 dB
PGA Boost Gain Error 20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−11 −7 dB
Mute Attenuation PGA muted
LDMUTE, RDMUTE = 0 −73 dB
RDBOOST[1:0], LDBOOST[1:0] = 00 −82 dB
Interchannel Gain Mismatch −0.6 +0.6 dB
Offset Error −6 +6 mV
Gain Error −24 −3 %
Common-Mode Rejection Ratio 100 mV rms, 1 kHz −64 −38 dB
100 mV rms, 20 kHz −53 −43 dB
FULL DIFFERENTIAL PGA INPUT Differential PGA inputs
Dynamic Range 20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS) 89 dB
No Filter (RMS) 86 dB
Total Harmonic Distortion + Noise −1 dBFS −70 dB
PGA Boost Gain Error 20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−11 −7 dB
Mute Attenuation PGA muted
LDMUTE, RDMUTE = 0 −73 dB
RDBOOST[1:0], LDBOOST[1:0] = 00 −82 dB
Interchannel Gain Mismatch −0.4 +0.4 dB
Offset Error −6 +6 mV
Gain Error −21 −7 %
Common-Mode Rejection Ratio 100 mV rms, 1 kHz −64 −38 dB
100 mV rms, 20 kHz −53 −43 dB
MICROPHONE BIAS MBIEN = 1
Bias Voltage
0.65 × AVDD MBI = 1, MPERF = 0 1.85 2.45 V
MBI = 1, MPERF = 1 1.87 2.45 V
0.90 × AVDD MBI = 0, MPERF = 0 2.65 3.40 V
MBI = 0, MPERF = 1 2.65 3.40 V
Noise in the Signal Bandwidth 1 kHz to 20 kHz 11 36 nV/√Hz
DAC TO LINE OUTPUT
Dynamic Range 20 Hz to 20 kHz, −60 dB input, line
output mode
With A-Weighted Filter (RMS) 85 dB
No Filter (RMS) 78 dB
Total Harmonic Distortion + Noise 0 dBFS, 10 kΩ load
Line Output Mode −76 dB
Headphone Output Mode −78 dB
Mute Attenuation
Mixer 3 and Mixer 4 Muted MX3RM, MX3LM, MX4RM, MX4LM = 0,
MX3AUXG[3:0], MX4AUXG[3:0] = 0000,
MX3G1[3:0], MX3G2[3:0] = 0000,
MX4G1[3:0], MX4G2[3:0] = 0000
−77 dB
Mixer 5, Mixer 6, and Mixer 7 Muted MX5G3[1:0], MX5G4[1:0], MX6G3[1:0],
MX6G4[1:0], MX7[1:0] = 00
−77 dB
All Volume Controls Muted LOUTM, ROUTM = 0 −74 dB
MONOM, LHPM, RHPM = 0 −69 dB
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Parameter Test Conditions/Comments Min Typ Max Unit
Interchannel Gain Mismatch −0.3 +0.3 dB
Offset Error −22 +22 mV
Gain Error −10 +10 %
DAC TO HEADPHONE/EARPIECE
OUTPUT
LOUTx, ROUTx, LHP, RHP in headphone
output mode; PO= output power per
channel
Total Harmonic Distortion + Noise
Capless Headphone Mode −2 dBFS, 16 Ω load −61 dB
−2 dBFS, 32 Ω load −63 dB
Headphone Output Mode 0 dBFS, 10 kΩ load −76 dB
REFERENCE
Common-Mode Reference Output CM pin 1.47 1.83 V
POWER SUPPLY SPECIFICATIONS
Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, ADC input @ −1 dBFS, DAC input @ 0 dBFS,
−40°C < TA< +105°C, IOVDD = 3.3 V ± 10%. For total power consumption, add the IOVDD current listed in Table 3 .
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
SUPPLIES
Voltage DVDDOUT 1.56 V
AVDD 2.97 3.3 3.65 V
IOVDD 2.97 3.3 3.65 V
Digital I/O Current (IOVDD) 20 pF capacitive load on all digital pins
Slave Mode fS= 48 kHz 0.48 mA
f
S= 96 kHz 0.9 mA
f
S= 8 kHz 0.13 mA
Master Mode fS= 48 kHz 1.51 mA
f
S= 96 kHz 3 mA
f
S= 8 kHz 0.27 mA
Analog Current (AVDD)
Record Stereo Differential to ADC
PLL bypass 5.24 mA
Integer PLL 6.57 mA
DAC Stereo Playback to Line Output 10 kΩ load
PLL bypass 5.55 mA
Integer PLL 6.90 mA
DAC Stereo Playback to Headphone 32 Ω load
PLL bypass 30.9 mA
Integer PLL 32.25 mA
DAC Stereo Playback to Capless Headphone 32 Ω load
PLL bypass 56.75 mA
Integer PLL 58 mA
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DIGITAL FILTERS
Table 4.
Parameter Mode Factor Min Typ Max Unit
ADC DECIMATION FILTER All modes, typ @ 48 kHz
Pass Band 0.4375 fS21 kHz
Pass-Band Ripple ±0.015 dB
Transition Band 0.5 fS24 kHz
Stop Band 0.5625 fS27 kHz
Stop-Band Attenuation 67 dB
Group Delay 22.9844/fS479 µs
DAC INTERPOLATION FILTER
Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 fS22 kHz
96 kHz mode, typ @ 96 kHz 0.3646 fS35 kHz
Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB
96 kHz mode, typ @ 96 kHz ±0.05 dB
Transition Band 48 kHz mode, typ @ 48 kHz 0.5 fS24 kHz
96 kHz mode, typ @ 96 kHz 0.5 fS48 kHz
Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 fS26 kHz
96 kHz mode, typ @ 96 kHz 0.6354 fS61 kHz
Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 69 dB
96 kHz mode, typ @ 96 kHz 68 dB
Group Delay 48 kHz mode, typ @ 48 kHz 25/fS521 µs
96 kHz mode, typ @ 96 kHz 11/fS115 µs
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA< +105°C, IOVDD = 3.3 V ± 10%.
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT SPECIFICATIONS
Input Voltage High (VIH) 0.7 × IOVDD V
Input Voltage Low (VIL) 0.3 × IOVDD V
Input Leakage
Pull-Ups/Pull-Downs Disabled IIH @ VIH = 3.3 V −0.17 +0.17 µA
I
IL @ VIL = 0 V −0.17 +0.17 µA
I
IL @ VIL = 0 V (MCLK pin) −13.5 −0.5 µA
Pull-Ups Enabled IIH @ VIH = 3.3 V −0.7 +0.7 µA
I
IL @ VIL = 0 V −13.5 −0.5 µA
Pull-Downs Enabled IIH @ VIH = 3.3 V 2.7 8.3 µA
I
IL @ VIL = 0 V −0.18 +0.18 µA
Input Capacitance 5 pF
OUTPUT SPECIFICATIONS
Output Voltage High (VOH) IOH = 2 mA @ 3.3 V 0.8 × IOVDD V
Output Voltage Low (VOL) IOL = 2 mA @ 3.3 V 0.1 × IOVDD V
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DIGITAL TIMING SPECIFICATIONS
−40°C < TA< +105°C, IOVDD = 3.3 V ± 10%.
Table 6. Digital Timing
Parameter
Limit
Unit DescriptiontMIN t
MAX
MASTER CLOCK
tMP 74 488 ns MCLK period, 256 × fSmode.
tMP 37 244 ns MCLK period, 512 × fSmode.
tMP 24.7 162.7 ns MCLK period, 768 × fSmode.
tMP 18.5 122 ns MCLK period, 1024 × fSmode.
SERIAL PORT
tBIL 5 ns BCLK pulse width low.
tBIH 5 ns BCLK pulse width high.
tLIS 5 ns LRCLK setup. Time to BCLK rising.
tLIH 5 ns LRCLK hold. Time from BCLK rising.
tSIS 5 ns DAC_SDATA setup. Time to BCLK rising.
tSIH 5 ns DAC_SDATA hold. Time from BCLK rising.
tSODM 50 ns ADC_SDATA delay. Time from BCLK falling in master mode.
SPI PORT
fCCLK 10 MHz CCLK frequency.
tCCPL 10 ns CCLK pulse width low.
tCCPH 10 ns CCLK pulse width high.
tCLS 5 ns
CLATCH setup. Time to CCLK rising.
tCLH 10 ns
CLATCH hold. Time from CCLK rising.
tCLPH 10 ns
CLATCH pulse width high.
tCDS 5 ns CDATA setup. Time to CCLK rising.
tCDH 5 ns CDATA hold. Time from CCLK rising.
tCOD 50 ns
COUT three-stated. Time from CLATCH rising.
I2C PORT
fSCL 400 kHz SCL frequency.
tSCLH 0.6 µs SCL high.
tSCLL 1.3 µs SCL low.
tSCS 0.6 µs Setup time; relevant for repeated start condition.
tSCH 0.6 µs Hold time. After this period, the first clock is generated.
tDS 100 ns Data setup time.
tSCR 300 ns SCL rise time.
tSCF 300 ns SCL fall time.
tSDR 300 ns SDA rise time.
tSDF 300 ns SDA fall time.
tBFT 0.6 µs Bus-free time. Time between stop and start.
DIGITAL MICROPHONE RLOAD = 1 MΩ, CLOAD = 14 pF.
tDCF 10 ns Digital microphone clock fall time.
tDCR 10 ns Digital microphone clock rise time.
tDDV 22 30 ns Digital microphone delay time for valid data.
tDDH 0 12 ns Digital microphone delay time for data three-stated.
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DIGITAL TIMING DIAGRAMS
BCLK
LRCLK
DAC_SDATA
LEFT-JUSTIFIED
MODE
LSB
DAC_SDATA
I
2
S MODE
DAC_SDATA
RIGHT-JUSTIFIED
MODE
t
BIH
MSB MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LIS
t
SIS
t
SIH
t
SIH
t
SIS
t
SIS
t
SIH
t
SIS
t
SIH
t
LIH
t
BIL
08915-002
Figure 2. Serial Input Port Timing
BCLK
LRCLK
ADC_SDATA
LEFT-JUSTIFIED
MODE
LSB
ADC_SDATA
I
2
S MODE
ADC_SDATA
RIGHT-JUSTIFIED
MODE
t
BIH
MSB MSB – 1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
SODM
t
BIL
t
SODM
t
SODM
08915-003
Figure 3. Serial Output Port Timing
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CLATCH
CCLK
CDATA
COUT
t
CLS
t
CDS
t
CDH
t
COD
t
CCPH
t
CCPL
t
CLH
t
CLPH
08915-004
Figure 4. SPI Port Timing
t
SCH
t
SCLH
t
SCR
t
DS
SDA
t
SCLL
t
SCF
SCL
t
SCH
t
BFT
t
SCS
08915-005
Figure 5. I2C Port Timing
CLK
DATA1/
DATA2 DATA1 DATA1 DATA2DATA2
08915-006
t
DCF
t
DDH
t
DDH
t
DDV
t
DDV
t
DCR
Figure 6. Digital Microphone Timing
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ADAU1961
Rev. 0 | Page 12 of 76
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter Rating
Power Supply (AVDD) −0.3 V to +3.65 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to IOVDD + 0.3 V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
θJA represents thermal resistance, junction-to-ambient; θJC repre-
sents thermal resistance, junction-to-case. All characteristics are
for a 4-layer board.
Table 8. Thermal Resistance
Package Type θJA θ
JC Unit
32-Lead LFCSP 50.1 17 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
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ADAU1961
Rev. 0 | Page 13 of 76
AGND
LINP
LINN
RINP
RINN
RAUX
ROUTP
ROUTN
SCL/CCLK SDA/COUT ADDR1/CDATA LRCLK BCLK DAC_SDATA ADC_SDATA DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1IOVDD 2MCLK 3ADDR0/CLATCH 4JACKDET/MICIN 5MICBIAS 6LAUX 7CM 8AVDD
24 DVDDOUT
23 AVDD
22 AGND
21 MONOOUT
20 LHP
19 RHP
18 LOUTP
17 LOUTN
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
TOP VIEW
(Not to Scale)
ADAU1961
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1961 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
08915-007
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1 IOVDD PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set to 3.3 V. The current draw of this pin is variable because it is dependent
on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 F capacitor.
2 MCLK D_IN External Master Clock Input.
3 ADDR0/CLATCH D_IN I2C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
4 JACKDET/MICIN D_IN Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
5 MICBIAS A_OUT Bias Voltage for Electret Microphone.
6 LAUX A_IN Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
7 CM A_OUT
AVDD/2 V Common-Mode Reference. A 10 F to 47 F standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
8 AVDD PWR
3.3 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled locally to
AGND with a 100 nF capacitor.
9 AGND PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
10 LINP A_IN Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
11 LINN A_IN Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
12 RINP A_IN Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
13 RINN A_IN Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
14 RAUX A_IN Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
15 ROUTP A_OUT Right Line Output, Positive. Biased at AVDD/2.
16 ROUTN A_OUT Right Line Output, Negative. Biased at AVDD/2.
17 LOUTN A_OUT Left Line Output, Negative. Biased at AVDD/2.
18 LOUTP A_OUT Left Line Output, Positive. Biased at AVDD/2.
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ADAU1961
Rev. 0 | Page 14 of 76
Pin No. Mnemonic Type1Description
19 RHP A_OUT Right Headphone Output. Biased at AVDD/2.
20 LHP A_OUT Left Headphone Output. Biased at AVDD/2.
21 MONOOUT A_OUT
Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono
output.
22 AGND PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
23 AVDD PWR
3.3 V Analog Supply for ADC, Output Driver, and Input to Digital Supply Regulator. This pin
should be decoupled locally to AGND with a 100 nF capacitor.
24 DVDDOUT PWR
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to DGND
with a 100 nF capacitor and a 10 F capacitor.
25 DGND PWR
Digital Ground. The AGND and DGND pins can be tied together on a common ground plane.
DGND should be decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 F
capacitors.
26 ADC_SDATA D_OUT ADC Serial Output Data.
27 DAC_SDATA D_IN DAC Serial Input Data.
28 BCLK D_IO Serial Data Port Bit Clock.
29 LRCLK D_IO Serial Data Port Frame Clock.
30 ADDR1/CDATA D_IN I2C Address Bit 1 (ADDR1).
SPI Data Input (CDATA).
31 SDA/COUT D_IO
I2C Data (SDA). This pin is a bidirectional open-collector input/output. The line connected to
this pin should have a 2 kΩ pull-up resistor.
SPI Data Output (COUT). This pin is used for reading back registers and memory locations. It is
three-state when an SPI read is not active.
32 SCL/CCLK D_IN
I2C Clock (SCL). This pin is always an open-collector input when in I2C control mode. The line
connected to this pin should have a 2 kΩ pull-up resistor.
SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions.
EP Exposed Pad Exposed Pad. The exposed pad is connected internally to the ADAU1961 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is recommended
that the pad be soldered to the ground plane. See the Exposed Pad PCB Design section for
more information.
1A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, D_OUT = digital output, PWR = power.
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ADAU1961
Rev. 0 | Page 15 of
–60 0–10–20–30–40–50 DIGITAL 1kHz INPUT SIGNAL (dBFS)
76
TYPICAL PERFORMANCE CHARACTERISTICS
28
0
2
4
6
8
10
12
14
16
18
20
22
24
26
STEREO OUTPUT POWER (mW)
–30
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–60 0–10–20–30–40–50
THD + N (dBV)
DIGITAL 1kHz INPUT SIGNAL (dBFS)
08915-056
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–60 0–10–20–30–40–50
THD + N (dBV)
DIGITAL 1kHz INPUT SIGNAL (dBFS)
08915-055
–60 0–10–20–30–40–50 DIGITAL 1kHz INPUT SIGNAL (dBFS)
Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load
18
0
2
4
6
8
10
12
14
16
STEREO OUTPUT POWER (mW)
08915-057
Figure 9. Headphone Amplifier Power vs. Input Level, 32 Ω Load
100
90
80
70
60
50
40
30
20
10
0
FREQUENCY (NORMALIZED TO fS )
MAGNITUDE (dBFS)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
08915-008
Figure 10. ADC Decimation Filter, 64× Oversampling, Normalized to fS
Figure 11. Headphone Amplifier THD + N vs. Input Level, 16 Ω Load
08915-058
Figure 12. Headphone Amplifier THD + N vs. Input Level, 32 Ω Load
0 0.05 0.10 0.20 0.30 0.400.15 0.25 0.35
0.06
0.04
0.02
0
0.02
0.04
FREQUENCY (NORMALIZED TO f
S
)
MAGNITUDE (dBFS)
08915-009
Figure 13. ADC Decimation Filter Pass-Band Ripple, 64× Oversampling,
Normalized to fS
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ADAU1961
Rev. 0 | Page 16 of 76
100
90
MAGNITUDE (dBFS)
80
70
60
50
40
30
20
10
0
FREQUENCY (NORMALIZED TO f
S
)
0.10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
915-010
0
08
Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized to fS
100
90
80
70
60
50
40
30
20
10
0
FREQUENCY (NORMALIZED TO f
S
)
MAGNITUDE (dBFS)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
915-01208
Figure 15. ADC Decimation Filter, 128× Oversampling, Double-Rate Mode,
Normalized to fS
100
90
FREQUENCY (NORMALIZED TO
f
S
)
80
70
60
50
40
30
20
10
0
MAGNITUDE (dBFS)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
08915-014
00.050.100.200.300.400.15 0.25 0.35 0.500.45
0.10
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08
0.10
FREQUENCY (NORMALIZED TO f
S
)
MAGNITUDE (dBFS)
08915-011
Figure 16. DAC Interpolation Filter, 64× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 17. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0 0.05 0.10 0.20 0.30 0.400.15 0.25 0.35
0.06
0.04
0.02
0
0.02
0.04
FREQUENCY (NORMALIZED TO f
S
)
MAGNITUDE (dBFS)
08915-013
Figure 18. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Double-Rate Mode, Normalized to fS
0 0.05 0.10 0.20 0.30 0.400.15 0.25 0.35
0.15
0.20
0.10
0.05
0
0.05
0.15
0.20
0.10
MAGNITUDE (dBFS)
FREQUENCY (NORMALIZED TO
f
S
)
08915-015
Figure 19. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling,
Double-Rate Mode, Normalized to fS
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ADAU1961
Rev. 0 | Page 17 of
0.05
0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
0.05
100
90
80
70
60
50
40
30
20
10
0
MAGNITUDE (dBFS)
76
FREQUENCY (NORMALIZED TO
f
S
)
0.10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
915-01608
Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized to fS
100
90
FREQUENCY (NORMALIZED TO
f )
MAGNITUDE (dBFS)
80
70
60
50
40
30
20
10
0
S
0.10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
915-01808
Figure 21. DAC Interpolation Filter, 128× Oversampling, Double-Rate Mode,
Normalized to fS
0
35.00 32.75 30.50 28.25 26.00 23.75 21.50 19.25 17.00 14.75 12.50 10.25
8.00 5.75 3.50 1.25
–1.00 –3.25 –5.50 –7.75
–10.00 –12.25
GAIN (dB)
10
20
30
40
50
60
70
80
90
IMPEDANCE (k)
08915-125
Figure 22. Input Impedance vs. Gain for Analog Inputs
0 0.05 0.10 0.20 0.30 0.400.15 0.25 0.35 0.500.45
FREQUENCY (NORMALIZED TO
f
S
)
MAGNITUDE (dBFS)
08915-017
Figure 23. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0 0.05 0.10 0.20 0.30 0.400.15 0.25 0.35
FREQUENCY (NORMALIZED TO
f
S)
MAGNITUDE (dBFS)
08915-019
Figure 24. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Double-Rate Mode, Normalized to fS
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ADAU1961
Rev. 0 | Page 18 of 76
SYSTEM BLOCK DIAGRAMS
AVDDIOVDD AVDDDVDDOUT
LINN
RINN
RINP
LINP
JACK
DETECTION
SIGNAL
LAUX
RAUX
LEFT
MICROPHONE
RIGHT
MICROPHONE
+
++
AUX RIGHT
AUX LEFT
JACKDET/MICIN
MCLK
AGND AGND DGND
ADC_SDATA
DAC_SDATA
LRCLK
BCLK
SERIAL DATA
CM
SYSTEM
CONTROLLER
ADDR1/CDATA
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
MICBIAS
LOUTP
LOUTN
LHP
MONOOUT
RHP
ROUTP
ROUTN
CAPLESS
HEADPHONE
OUTPUT
EARPIECE
SPEAKER
EARPIECE
SPEAKER
CLOCK
SOURCE
THE INPUT CAPACITOR VALUE DEPENDS ON THE
INPUT IMPEDANCE, WHICH VARIES WITH THE
VOLUME SETTING.
ADAU1961
10µF
10µF
10µF
0.1µF
10µF
10µF
0.1µF
0.1µF
0.1µF
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
9.1pF
2k
2k
1k
1k
49.9
0.1µF
1.2nH
10µF
10µF
10µF
10µF
10µF +
08915-045
Figure 25. System Block Diagram
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ADAU1961
Rev. 0 | Page 19 of 76
AVDDIOVDD AVDDDVDDOUT
LINN
RINN
RINP
LINP
JACK
DETECTION
SIGNAL
LAUX
RAUX
+
++
AUX RIGHT
AUX LEFT
CM
JACKDET/MICIN
MCLK
AGND AGND DGND
ADC_SDATA
DAC_SDATA
LRCLK
BCLK
SERIAL DATA
CM
SYSTEM
CONTROLLER
ADDR1/CDATA
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
MICBIAS
CLOCK
SOURCE
THE INPUT CAPACITOR VALUE DEPENDS ON THE
INPUT IMPEDANCE, WHICH VARIES WITH THE
VOLUME SETTING.
ADAU1961
10µF
10µF
CM
10µF
10µF
10µF
0.1µF
10µF
10µF
0.1µF
0.1µF
9.1pF
0.1µF
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
1k
1k
49.9
1.2nH
08915-059
VDD
GND
SINGLE-ENDED
ANALOG
MICROPHONE OUTPUT
VDD
GND
SINGLE-ENDED
ANALOG
MICROPHONE OUTPUT
LOUTP
LOUTN
LHP
MONOOUT
RHP
ROUTP
ROUTN
CAPLESS
HEADPHONE
OUTPUT
EARPIECE
SPEAKER
EARPIECE
SPEAKER
0.1µF 10µF +
Figure 26. System Block Diagram with Analog Microphones
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ADAU1961
Rev. 0 | Page 20 of 76
AVDDIOVDD AVDDDVDDOUT
LINN
RINN
RINP
LINP
LAUX
RAUX
+
++
AUX LEFT
MCLK
AGND AGND DGND
ADC_SDATA
DAC_SDATA
LRCLK
BCLK
SERIAL DATA
CM
SYSTEM
CONTROLLER
ADDR1/CDATA
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
MICBIAS
LOUTP
LOUTN
ROUTP
ROUTN
CLOCK
SOURCE
ADAU1961
10µF
CM
10µF
0.1µF
10µF
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
9.1pF
22nF
R
EXT
0.1µF
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
1k
AUX RIGHT
10µF
1k
49.9
BCLK
0.1µF 10µF +
1.2nH
08915-060
22nF
R
EXT
22nF
R
EXT
R
EXT
22nF INL+
INL–
INR+
INR–
OUTL+
OUTL–
OUTR+
OUTR–
SSM2306
CLASS-D 2W
STEREO SPEAKER
DRIVER
VDDVDD
GNDSD GND
2.5V TO 5.0V
RIGHT
SPEAKER
LEFT
SPEAKER
LHP
MONOOUT
RHP
CAPLESS
HEADPHONE
OUTPUT
BCLK
JACKDET/MICIN
GNDL/R SELECT
DATA
V
DD
CLK
DIGITAL
MICROPHONE
GNDL/R SELECT
DATA
V
DD
CLK
DIGITAL
MICROPHONE
SHUTDOWN
Figure 27. System Block Diagram with Digital Microphones and SSM2306 Class-D Speaker Driver
Downloaded from Elcodis.com electronic components distributor