Analog Devices ADPA1105-EVALZ User manual

ADPA1105-EVALZ User Guide
UG-1674
One Technology Way •P.O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluating the ADPA1105 46 dBm (40 W), 0.9 GHz to 1.6 GHz, GaN Power Amplifier
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 13
FEATURES
2-Layer Rogers 4350B evaluation board with heat spreader
End launch SMA jack RF connectors
Through calibration path
Drain or gate pulsing capability
EVALUATION KIT CONTENTS
ADPA1105-EVALZ evaluation board
50 V drain pulser board
EQUIPMENT NEEDED
Pulse generator
Oscilloscope
50 V, 2 A power supply
−4 V power supply
Tektronix TCPA312A current probe
Tektronix TCPA300 current probe amplifier
RF signal generator
Directional coupler
RF power sensor
RF power meter
RF attenuator
DOCUMENTS NEEDED
ADPA1105 data sheet
GENERAL DESCRIPTION
The ADPA1105-EVALZ consists of a 2-layer printed circuit
board (PCB) fabricated from a 10 mil thick, Rogers 4350B
copper clad mounted to an aluminum heat spreader. The heat
spreader assists in providing thermal relief to the device as well
as mechanical support to the PCB. Mounting holes on the heat
spreader allow the spreader to be attached to a heat sink.
Alternatively, the spreader can be clamped to a hot and cold
plate. The RFIN and RFOUT ports on the ADPA1105-EVALZ
are populated by Subminiature Version A (SMA) female
coaxial connectors, and the respective RF traces have a 50 Ω
characteristic impedance. The ADPA1105-EVALZ is populated
with components suitable for use over the entire operating
temperature range of the device. To calibrate board trace losses,
a through calibration path is provided between the J6 and J5
connectors. J6 and J5 must be populated with SMA RF
connectors to use the through calibration path.
Ground, power, gate control, and the detector output voltage
are provided through two 4-pin headers (P1 and P2) and two
24-pin headers (P3 and P4) on the ADPA1105-EVALZ. The
pinouts for these four headers are shown in Table 1.
RF traces on the ADPA1105-EVALZ are 50 Ω, grounded, coplanar
waveguide. The package ground leads and the exposed paddle
connect directly to the ground plane. Multiple vias connect the
top and bottom ground planes with particular focus on the area
directly beneath the ground pad to provide adequate electrical
conduction and thermal conduction to the heat spreader.
The ADPA1105-EVALZ ships with a drain pulsing board
(pulser board) that can be plugged into the ADPA1105-EVALZ
headers and configured to control the biasing of the ADPA1105
by providing a negative gate voltage and a control signal that
connects and disconnects the drain voltage to the ADPA1105-
EVALZ. The ADPA1105-EVALZ can also be operated alone in
gate pulsed mode where a negative pulse is applied to the
ADPA1105 VGG1 and VGG2 pins.
For full details on the ADPA1105, see the ADPA1105 data
sheet, which must be consulted in conjunction with this user
guide when using the ADPA1105-EVALZ.

UG-1674 ADPA1105-EVALZ User Guide
Rev. 0 | Page 2 of 13
TABLE OF CONTENTS
Features.............................................................................................. 1
Evaluation Kit Contents .................................................................. 1
Equipment Needed........................................................................... 1
Documents Needed.......................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Evaluation Board Photographs....................................................... 3
Header Pinout................................................................................... 4
Insertion Loss of the Through Calibration Path.......................... 5
Operating the ADPA1105-EVALZ with a Pulsed Gate Voltage 6
Setup............................................................................................... 6
Operation .......................................................................................6
Operating the ADPA1105-EVALZ with the Drain Bias Pulser
Board...................................................................................................7
Setup................................................................................................8
Operation .......................................................................................8
Making Average to Pulsed Approximations .............................. 10
Evaluation Board Schematic and Artwork ................................. 11
Ordering Information.................................................................... 13
Bill of Materials .......................................................................... 13
REVISION HISTORY
10/2020—Revision 0: Initial Version

ADPA1105-EVALZ User Guide UG-1674
Rev. 0 | Page 3 of 13
EVALUATION BOARD PHOTOGRAPHS
22011-001
Figure 1. ADPA1105-EVALZ Evaluation Board, Primary Side
22011-002
Figure 2. ADPA1105-EVALZ Evaluation Board, Secondary Side

UG-1674 ADPA1105-EVALZ User Guide
Rev. 0 | Page 4 of 13
HEADER PINOUT
The schematic for the ADPA1105-EVALZ is shown in Figure 6.
The ADPA1105-EVALZ contains four headers, P1, P2, P3, and
P4. Table 1 describes the pinout of these headers.
Table 1. P1 to P4 Header Connections on the ADPA1105-EVALZ
Header Header Pin Number Header Pin Name
P1 1, 3 GND
2 DET2_OUT
4 DET2_BIAS
P2 1, 3 GND
2 DET1_OUT
4 DET1_BIAS
P3 1, 3, 5, 7, 9, 10, 11, 12, 13, 14, 15, 17, 19, 21, 22, 23, 24 GND
2, 16, 18, 20 Not connected
4, 6 VDD2
8 VDD1
P4 1, 2, 3, 4, 5, 7, 9, 11, 12, 13, 14, 15, 16, 17, 19, 21, 23 GND
18, 20, 22 Not connected
6, 8 VGG1
10 VGG2
24 DET2_BIAS

ADPA1105-EVALZ User Guide UG-1674
Rev. 0 | Page 5 of 13
INSERTION LOSS OF THE THROUGH CALIBRATION PATH
To calibrate board trace losses, a through calibration path is
provided between the J6 and J5 connectors. J6 and J5 must be
populated with SMA RF connectors to use the through calibration
path. Figure 3 shows the insertion loss, input return loss, and
output return loss of the through calibration path. Table 2 lists
the insertion loss of the through path vs. frequency.
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
012345678910
INSERTION LOSS, INPUT RETURN LOSS AND
OUTPUT RETURN LOSS (dB)
FREQUENCY (GHz)
22011-003
OUTPUT RETURN LOSS
INPUT RETURN LOSS
INSERTION LOSS
Figure 3. Insertion Loss, Input Return Loss, and Output Return Loss of
Through Calibration Path
Table 2. Insertion Loss of Through Calibration Path
Frequency (GHz) Insertion Loss (dB)
1 −0.24
2 −0.36
3 −0.48
4 −0.45
5 −0.5
6 −0.55
7 −0.61
8 −0.64
9 −0.65
10 −0.65

UG-1674 ADPA1105-EVALZ User Guide
Rev. 0 | Page 6 of 13
OPERATING THE ADPA1105-EVALZ WITH A PULSED GATE VOLTAGE
To implement gate pulsed operation, apply a negative voltage
pulse to the ADPA1105 VGG1 and VGG2 inputs while the voltage
on the ADPA1105 VDD1 and VDD2 pins is held constant.
SETUP
All power supply, ground, and control signals are applied to
the P3 and P4 headers of the ADPA1105-EVALZ. For this
mode of operation, pulse the gate voltage between −4 V (off)
and approximately −2.3 V (on) to set the quiescent current
(IDQ) to approximately 400 mA. The pulse width and duty cycle
must be approximately 100 μs and 10%, respectively.
OPERATION
Take the following steps to power-up:
1. Set VDDx (P3 Pin 4, Pin 6, and Pin 8) to 0 V.
2. Set VGGx (P4 Pin 6, Pin 8, and Pin 10) to off (VGG1 =
VGG2 = −4 V).
3. Set VDD to 50 V.
4. Turn on the gate voltage pulse (VGG1 and VGG2 pulsing
between −4 V and approximately −2.3 V).
5. Fine tune the pulse high voltage to achieve the desired IDQ
(nominally 400 mA) while maintaining the pulse off
voltage level at −4 V.
6. Apply the RF input signal.
Take the following steps to power-down:
1. Turn off the RF signal.
2. Turn off the pulse to VGG1 and VGG2 (VGG1 = VGG2 = −4 V).
3. Set VDD to 0 V.
4. Increase the pulse to VGG1 and VGG2 to 0 V.

ADPA1105-EVALZ User Guide UG-1674
Rev. 0 | Page 7 of 13
OPERATING THE ADPA1105-EVALZ WITH THE DRAIN BIAS PULSER BOARD
The ADPA1105-EVALZ ships with a drain bias pulser board. A
block diagram of the pulser board is shown in Figure 4. The pulser
board has two primary components. The BSC340N08NS3 is an
80 V/23 A, metal-oxide semiconductor field effect transistor
(MOSFET) that switches the drain voltage to the ADPA1105
on and off, and the LTC7000 is a high-side, negative channel
metal-oxide semiconductor (NMOS), static switch driver that
controls the MOSFET.
The pulser board plugs into the P3 and P4 headers of
ADPA1105-EVALZ and can be configured to provide a pulsed
drain voltage and a negative gate control voltage to control the
biasing of the ADPA1105.
Table 3. Pulser Board J1, J2, and J3 Header Connections
to ADPA1105
VIN
C3
180pF
100V
VCC
VCCUV
FAULT
TIMER
PULSE
U2
PULSEPULSE
VDET_BIAS /
VREF_BIAS
VDET_BIAS /
VREF_BIAS
J3
J2
J4
CONNECTS DIRECTLY TO
EVAL BOARD P4
GND
GND
INP
1
3
5
6
7
8
16
P1
PEC02SAAN
14
12
11
10
D
S
G
81 Q1
BSC340N08NS3
9
SNS+
SNS–
BST
TS
TGUP
TGDN
PAD
CMPD3003
U1
LTC7000EMSE-13PBF
R5
0Ω
R1
100kΩ
R7
1kΩ
R3
1kΩ
VDD
C2
0.1µF
100V
C4
10µF
100V
C7
10µF
100V
C8
10µF
100V
C11
1000µF
80V
C13
1µF
C12
0.001µF
C1
0.1µF
C10
3300µF
80V
++
VDD VDD
J1
INPUTS
FROM USER
C9
10µF
100V
CONNECTS DIRECTLY
TO EVAL BOARD P3
PULSED_VDD_DUT
2526
2324
2122
1920
1718
1516
1314
1112
910
78
56
34
12
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
VGG1, VGG2
V
GG1, VGG2 VGG1, VGG2
7
6
2
3
54
R8
PULSED_VDD
PULSED_VDD
FOR MONITORING
WITH HIGH-Z
OSCILLOSCOPE PROBE
0Ω
22011-004
Figure 4. Analog Devices, Inc., Pulser Board Schematic
Header Header Pin Number Header Pin Name
J1 1, 2, 3, 4, 5, 6 VDD
7, 8, 25 No connect
9, 10, 11, 12, 13, 14 VGG1, VGG2
15, 16, 17, 18, 21, 22, 23, 24 GND
19, 20 PULSE
26 VDET_BIAS, VREF_BIAS
J2 1, 3, 5, 7, 9, 10, 11, 12, 13, 14, 15,
17, 19, 21, 22, 23, 24
GND
2, 16, 18, 20 No connect
4, 6, 8 PULSED_VDD_DUT
J3 1, 2, 3, 4, 5, 7, 9, 11, 12, 13, 14,
15, 16, 17, 19, 21, 23
GND
6, 8 ,10 VGG1, VGG2
24 VDET_BIAS, VREF_BIAS

UG-1674 ADPA1105-EVALZ User Guide
Rev. 0 | Page 8 of 13
SETUP
The connections required to use the ADPA1105-EVALZ with
the drain bias pulser board are shown in Figure 5. Before applying
any bias or signals, plug the pulser board into ADPA1105-EVALZ
so that the pulser board J2 header connector connects to the
ADPA1105-EVALZ P3 header, and the pulser board J3 header
connects to the ADPA1105-EVALZ P4 header. All external
supply voltages and control signals are applied to the pulser
board J1 header, which are listed in Table 3.
The gate control voltage applied to the J1 connector, Pin 9 to
Pin 14, passes directly through the pulser board and drives the
ADPA1105 VGG1 pin and VGG2 pin. Because the VDD and GND
lines carry currents up to 2 A, the use of heavy gauge twister
pair wires is recommended to minimize voltage drops. To
observe the pulsed drain voltage (PULSED_VDD) that drives
the ADPA1105 VDD1 and VDD2 pins, connect an oscilloscope to
the J4 coaxial connector on the pulser board.
Connect a digital pulse generator that can generate 0 V to 5 V
pulses with a pulse width of 100 μs and a duty cycle of 10% to the
pulse pins of J1, Pin 19 and Pin 20.
To observe and measure the drain current and the ADPA1105
RF output power, use a current probe and a pulsed RF power
meter. If these methods are not available, make approximations
as described in the Making Average to Pulsed Approximations
section.
OPERATION
Take the following steps to power-up (unless otherwise stated,
all signals are applied to the pulser board):
1. Set the voltage on Pin 19 and Pin 20 of J1 (PULSE) to 0 V.
2. Set the voltage on Pin 9 to Pin 14 of J1 (VGG1, VGG2) to
−4 V.
3. Set the voltage on Pin 1, Pin 2, Pin 3, Pin 4, Pin 5 and Pin 6
of J1 (VDDx) to 50 V.
4. Turn on PULSE (0 V/5 V, 100 μs, 10% duty cycle).
5. Increase the voltage on Pin 9 to Pin 14 of J1 (VGG1,
VGG2) until the target IDQ is reached (nominally 400 mA).
6. Apply the RF input signal to the ADPA1105-EVALZ RFIN
connector.
Take the following steps to power-down:
1. Turn off the RF input signal.
2. Set the voltage on Pin 9 to Pin 14 of J1 (VGG1, VGG2)
to −4 V.
3. Turn off PULSE (set to 0 V).
4. Set the voltage on Pin 1 to Pin 6 of J1 (VDD) to 0 V.
5. Set the voltage on Pin 9 to Pin 14 of J1 (VGG1, VGG2) to 0 V.

ADPA1105-EVALZ User Guide UG-1674
Rev. 0 | Page 9 of 13
22011-005
PULSE GENERATOR
SYNC OUT PULSE OUT
DRAIN PULSER
BOARD
ADPA1105 EVAL BOARD
J2
P3
RFOUTRFIN ATTENUATOR
INPUT OUTPUT
POWER METER
TRIGGER IN CH 1 CH 2
DIRECTIONAL
COUPLER
INPUT
COUPLED
OUTPUT
DIRECTIONAL
COUPLER
INPUT
COUPLED
OUTPUT
RF SIGNAL
GENERATOR
TRIGGER IN RF OUT
ATTENUATOR
POWER
SENSOR 1
OUTPUTINPUT
50Ω
TERMINATION
INPUT
AMPLIFIER
OUTPUT INPUT
OSCILLOSCOPE
CH 1 CH 3CH 2
VDD AND IDD
MONITORING
TRIGGER
TEKTRONIX
TCPA300
CURRENT
PROBE
TEKTRONIX
TCPA312A
DC SUPPLY
V
DD
+50V/2AGND
DC SUPPLY
V
GGx
0V TO –4V GND
J4
PULSED_VDD
VDD VGG1 GNDSENSE PULSE
J3
J1
P4
ATTENUATOR
POWER
SENSOR 2
OUTPUTINPUT
Figure 5. Setup Block Diagram

UG-1674 ADPA1105-EVALZ User Guide
Rev. 0 | Page 10 of 13
MAKING AVERAGE TO PULSED APPROXIMATIONS
Instruments that can be triggered are required to measure the RF
power, drain current, and power added efficiency (PAE) accurately
under pulsed operation. When such instrumentation is not
available, use averaging and approximations. The most
common approximations involve measuring the average values
and then adjusting those values to account for the duty cycle.
These approximations can result in errors because of limited
measurement bandwidths of instruments and/or the inclusion
of on and off transients and/or partial periods in the
measurement.
To ensure that partial periods do not contribute significant
errors to the measurements, perform averaging over a large
number of pulse periods. The results of such approximations
can vary with the instruments and settings used. Therefore,
experimentation can be necessary to achieve credible and
repeatable results. When it is not possible to make pulse
triggered measurements, the only pulse connection required is
the connection from the pulse generator to the J1 connector of
the pulser (see Figure 5).