Analog Devices ADF7021-V User manual

High Performance,
Narrow-Band Transceiver IC
ADF7021-V
Rev. 0
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FEATURES
High performance, low power, narrow-band transceiver
Enhanced performance ADF7021-N with external VCO
Frequency bands using external VCO: 80 MHz to 960 MHz
Improved adjacent channel power (ACP) and adjacent
channel rejection (ACR) compared with the ADF7021-N
Programmable IF filter bandwidths: 9 kHz, 13.5 kHz,
and 18.5 kHz
Modulation schemes: 2FSK, 3FSK, 4FSK, MSK
Spectral shaping: Gaussian and raised cosine filtering
Data rates: 0.05 kbps to 24 kbps
Power supply: 2.3 V to 3.6 V
Programmable output power: −16 dBm to +13 dBm
in 63 steps
Automatic power amplifier (PA) ramp control
Receiver sensitivity
−125 dBm at 250 bps, 2FSK
−122 dBm at 1 kbps, 2FSK
Patent pending, on-chip image rejection calibration
On-chip fractional-N PLL
On-chip, 7-bit ADC and temperature sensor
Fully automatic frequency control (AFC) loop
Digital received signal strength indication (RSSI)
Integrated Tx/Rx switch
Leakage current in power-down mode: 0.1 μA
APPLICATIONS
Narrow-band, short-range device (SRD) standards
ETSI EN 300 220
500 mW output power capability in 869 MHz g3 subband
with external PA
High performance receiver rejection, blocking, and
adjacent channel power (ACP)
FCC Part 90 (meets Emission Mask D requirements)
FCC Part 95
ARIB STD-T67
Wireless metering
Narrow-band wireless telemetry
FUNCTIONAL BLOCK DIAGRAM
2FSK
3FSK
4FSK
DEMODULATOR
CLOCK
AND DATA
RECOVERY
7-BIT ADC
GAIN
DIV R
RFOUT
LNA
PFD
CP
BUFFER
OSC1 OSC2
N/N + 1
DIV P
OSC
CLKOUT
TEST MUX
CPOUT
LDO[1:4]
MUXOUT
RSET C
R
EG[1:4]CE
ADF7021-V
TxRxCLK
SWD
TxRxDATA
SLE
SDATA
SREAD
SCLK
IF FILTER
PA RAMP
L2
MUX
2FSK
3FSK
4FSK
MOD CONTROL
GAUSSIAN/
RAISED COSINE
FILTER
3FSK
ENCODING
÷1/÷2
÷2
0
8635-001
CLK
DIV
Σ-Δ
MODULATOR
SERIAL
PORT
Tx/Rx
CONTROL
AGC
CONTROL
AFC
CONTROL
TEMP
SENSOR
RSSI/
LOG AMP
R
LNA
RFIN
RFIN
Figure 1.

ADF7021-V
Rev. 0 | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
RF and PLL Specifications........................................................... 4
Transmission Specifications........................................................ 5
Receiver Specifications ................................................................ 6
Digital Specifications ................................................................... 9
General Specifications ............................................................... 10
Timing Characteristics .............................................................. 10
Timing Diagrams........................................................................ 11
Absolute Maximum Ratings.......................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
Frequency Synthesizer ................................................................... 21
Reference Input........................................................................... 21
MUXOUT.................................................................................... 22
Voltage Controlled Oscillator (VCO) ...................................... 23
Choosing a VCO for Best System Performance ..................... 23
Transmitter ...................................................................................... 24
RF Output Stage.......................................................................... 24
Modulation Schemes.................................................................. 24
Spectral Shaping ......................................................................... 26
Modulation and Filtering Options........................................... 27
Transmit Latency ........................................................................ 27
Test Pattern Generator............................................................... 27
Receiver Section.............................................................................. 28
RF Front End............................................................................... 28
IF Filter......................................................................................... 28
RSSI/AGC.................................................................................... 28
Demodulation, Detection, and CDR....................................... 30
Receiver Setup............................................................................. 32
FSK Demodulator Optimization.............................................. 33
AFC Operation ........................................................................... 34
Automatic Sync Word Detection (SWD)................................ 35
Applications Information .............................................................. 36
IF Filter Bandwidth Calibration............................................... 36
LNA/PA Matching...................................................................... 37
Image Rejection Calibration ..................................................... 38
Packet Structure and Coding.................................................... 39
Programming After Initial Power-Up ..................................... 39
Applications Circuit................................................................... 42
Serial Interface ................................................................................ 43
Readback Format........................................................................ 43
Interfacing to a Microcontroller/DSP ..................................... 44
Register 0—N Register............................................................... 45
Register 1—Oscillator Register................................................. 46
Register 2—Transmit Modulation Register ............................ 47
Register 3—Transmit/Receive Clock Register........................ 48
Register 4—Demodulator Setup Register ............................... 49
Register 5—IF Filter Setup Register......................................... 50
Register 6—IF Fine Calibration Setup Register ..................... 51
Register 7—Readback Setup Register...................................... 52
Register 8—Power-Down Test Register .................................. 53
Register 9—AGC Register......................................................... 54
Register 10—AFC Register ....................................................... 55
Register 11—Sync Word Detect Register................................ 56
Register 12—SWD/Threshold Setup Register........................ 56
Register 13—3FSK/4FSK Demodulation Register................. 57
Register 14—Test DAC Register............................................... 58
Register 15—Test Mode Register ............................................. 59
Outline Dimensions....................................................................... 60
Ordering Guide .......................................................................... 60
REVISION HISTORY
4/10—Revision 0: Initial Version

ADF7021-V
Rev. 0 | Page 3 of 60
GENERAL DESCRIPTION
The ADF7021-V is a high performance, low power, narrow-band
RF transceiver based on the ADF7021-N. The architecture of
the ADF7021-V transceiver is similar to that of the ADF7021-N
except that an external VCO is used by the on-chip RF synthesizer
for applications that require improved phase noise performance.
The ADF7021-V is designed to operate in both the license-free
ISM bands and in the licensed bands from 80 MHz to 960 MHz.
To minimize RF feedthrough and spurious emissions, the
external VCO operates at 2× or 4× the desired RF frequency;
the ADF7021-V supports a maximum VCO frequency operation
of 1920 MHz. The 4× VCO operation is programmable by
enabling an additional on-chip divide-by-2 outside the RF
synthesizer loop and offers improved phase noise performance.
As with the ADF7021-N receiver, the IF filter bandwidths
of 9 kHz, 13.5 kHz, and 18.5 kHz are supported, making the
ADF7021-V ideally suited to worldwide narrow-band telemetry
applications.
The part has both Gaussian and raised cosine transmit data
filtering options to improve spectral efficiency for narrow-band
applications. It is suitable for circuit applications targeted at the
following:
•European ETSI EN 300 220
•North American FCC Part 15, Part 90, and Part 95
•Japanese ARIB STD-T67
•Korean short-range device regulations
•Chinese short-range device regulations
A complete transceiver can be built using a small number of
discrete external components, making the ADF7021-V very
suitable for area-sensitive, high performance driven applications.
The range of on-chip FSK modulation and data filtering options
allows users greater flexibility in their choice of modulation
schemes while meeting the tight spectral efficiency requirements.
The ADF7021-V also supports protocols that dynamically switch
among 2FSK, 3FSK, and 4FSK to maximize communication
range and data throughput.
The transmit section contains a low noise fractional-N PLL with
an output resolution of <1 ppm. The frequency-agile PLL allows
the ADF7021-V to be used in frequency-hopping spread spectrum
(FHSS) systems. The VCO is external, which provides better
phase noise and thus lower adjacent channel power (ACP) and
adjacent channel rejection (ACR) compared with the ADF7021-N.
The VCO tuning range extends from 0.2 V to 2 V, which should
be taken into account when choosing the external VCO.
The transmitter output power is programmable in 63 steps from
−16 dBm to +13 dBm and has an automatic power amplifier ramp
control to prevent spectral splatter and help meet regulatory
standards. The transceiver RF frequency, channel spacing, and
modulation are programmable using a simple 3-wire interface.
The device operates with a power supply range of 2.3 V to 3.6 V
and can be powered down when not in use.
A low IF architecture is used in the receiver (100 kHz), which
minimizes power consumption and the external component
count yet avoids dc offset and flicker noise at low frequencies.
The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz,
and 18.5 kHz. The ADF7021-V supports a wide variety of pro-
grammable features, including Rx linearity, sensitivity, and IF
bandwidth, allowing the user to trade off receiver sensitivity
and selectivity against current consumption, depending on
the application. The receiver also features a patented automatic
frequency control (AFC) loop with programmable pull-in range
that allows the PLL to remove the frequency error in the
incoming signal.
The receiver achieves an image rejection performance of 50 dB
using a patent-pending IR calibration scheme that does not
require the use of an external RF source.
An on-chip ADC provides readback of the integrated temper-
ature sensor, external analog input, battery voltage, and RSSI
signal, which can eliminate the need for an external ADC in
some applications. The temperature sensor is accurate to ±10°C
over the full operating temperature range of −40°C to +85°C.
This accuracy can be improved by performing a one-point cali-
bration at room temperature and storing the result in memory.

ADF7021-V
Rev. 0 | Page 4 of 60
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA= TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA= 25°C. All
measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version
number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth.
RF AND PLL SPECIFICATIONS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS
Phase Frequency Detector (PFD)
Frequency
RF/256 24 MHz Maximum usable PFD at a particular RF frequency
is limited by the minimum N divider value
PHASE-LOCKED LOOP (PLL)
Normalized In-Band Phase Noise
Floor1
−203 dBc/Hz
PLL Settling 155 μs Measured for a 100 kHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz
EXTERNAL VCO
Tuning Range 0.2 2 V
Pin L2 Input Sensitivity 0 dBm VCO frequency < 1920 MHz
REFERENCE INPUT
Crystal Reference23.625 24 MHz
External Oscillator2, 3 3.625 24 MHz
Crystal Start-Up Time410 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V
XTAL Bias = 20 μA 0.930 ms
XTAL Bias = 35 μA 0.438 ms
Input Level for External Oscillator
OSC1 Pin 0.8 V p-p Clipped sine wave
OSC2 Pin CMOS levels V
ADC PARAMETERS VDD = 2.3 V to 3.6 V, TA= 25°C
Integral Nonlinearity (INL) ±0.4 LSB
Differential Nonlinearity (DNL) ±0.4 LSB
1This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the power amplifier (PA) output: −203 + 10 log(fPFD) + 20 logN.
2Guaranteed by design. Sample tested to ensure compliance.
3A TCXO, VCXO, or OCXO can be used as an external oscillator.
4Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.

ADF7021-V
Rev. 0 | Page 5 of 60
TRANSMISSION SPECIFICATIONS
LBW = loop bandwidth.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DATA RATE Limited by the loop bandwidth
2FSK 0.05 18.5 kbps LBW must be ≥1.25 × data rate for correct operation
3FSK 0.05 18.5 kbps LBW = 18.5 kHz
4FSK 0.05 24 kbps LBW = 18.5 kHz
MODULATION
Frequency Deviation (fDEV) 0.056 28.26 kHz PFD = 3.625 MHz
0.306 156 kHz PFD = 20 MHz
Frequency Deviation Resolution 56 Hz PFD = 3.625 MHz
Gaussian Filter Bandwidth Time (BT) 0.5
Raised Cosine Filter Alpha 0.5/0.7 Programmable
TRANSMIT POWER
Maximum Transmit Power113 dBm VDD = 3.0 V, TA= 25°C
Transmit Power Variation vs.
Temperature
±1 dB TA= −40°C to +85°C
Transmit Power Variation vs. VDD ±1 dB VDD = 2.3 V to 3.6 V at 915 MHz, TA= 25°C
Transmit Power Flatness ±1 dB 902 MHz to 928 MHz, VDD = 3 V, TA= 25°C
Programmable Step Size 0.3125 dB −16 dBm to +13 dBm
ADJACENT CHANNEL POWER (ACP) Gaussian 2FSK modulation, 13 dBm output power,
PFD = 19.68 MHz, LBW = 6 kHz
460 MHz
12.5 kHz Channel Spacing −47 dBm Measured in a ±8.5 kHz bandwidth at ±12.5 kHz
offset, 2.4 kbps PN9 data, fDEV = 1.2 kHz
25 kHz Channel Spacing −53 dBm Measured in a ±16 kHz bandwidth at ±25 kHz
offset, 4.8 kbps PN9 data, fDEV = 2.4 kHz
868 MHz Compliant with ETSI EN 300 220
12.5 kHz Channel Spacing −44 dBm Measured in a ±8.5 kHz bandwidth at ±12.5 kHz
offset, 2.4 kbps PN9 data, fDEV = 1.2 kHz
25 kHz Channel Spacing −49 dBm Measured in a ±16 kHz bandwidth at ±25 kHz
offset, 4.8 kbps PN9 data, fDEV = 2.4 kHz
MODULATION BANDWIDTH 869.525 MHz, Gaussian 2FSK modulation, 4.8 kbps,
fDEV = 2.4 kHz, 10 dBm output power,2compliant
with ETSI EN 300 220, LBW = 6 kHz
125 kHz Offset −74.5 dBm/1 kHz
125 kHz + 200 kHz −79 dBm/1 kHz
125 kHz + 400 kHz −69.5 dBm/10 kHz
125 kHz + 1 MHz −62 dBm/100 kHz
EMISSION MASK FCC Part 90 Emission Mask D, 100 Hz resolution
bandwidth, Gaussian 2FSK modulation, LBW =
6 kHz, 10 dBm output power, 2.4 kbps PN9 data,
fDEV = 1.2 kHz
12.5 kHz Offset
460 MHz −77 dBc
OCCUPIED BANDWIDTH 99.0% of total mean power, LBW = 6 kHz, 10 dBm
output power
2FSK, Gaussian Data Filtering
12.5 kHz Channel Spacing 4.0 kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz
25 kHz Channel Spacing 8.5 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz
2FSK, Raised Cosine Data Filtering
12.5 kHz Channel Spacing 4.5 kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz
25 kHz Channel Spacing 9.6 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz

ADF7021-V
Rev. 0 | Page 6 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
3FSK, Raised Cosine Filtering
12.5 kHz Channel Spacing 4.3 kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz
25 kHz Channel Spacing 8.5 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz
4FSK, Raised Cosine Filtering
25 kHz Channel Spacing 11.3 kHz 9.6 kbps PN9 data, fDEV = 1.2 kHz
SPURIOUS EMISSIONS
Reference Spurs −65 dBc LBW = 8 kHz
HARMONICS313 dBm output power
Second Harmonic −35/−52 dBc Unfiltered conductive/filtered conductive
Third Harmonic −43/−60 dBc Unfiltered conductive/filtered conductive
All Other Harmonics −36/−65 dBc Unfiltered conductive/filtered conductive
OPTIMUM PA LOAD IMPEDANCE
fRF = 915 MHz 39 + j61 Ω
fRF = 868 MHz 48 + j54 Ω
fRF = 470 MHz 97.5 + j64.4 Ω
fRF = 450 MHz 98 + j65 Ω
fRF = 426 MHz 100 + j65 Ω
fRF = 315 MHz 129 + j63 Ω
fRF = 175 MHz 173 + j49 Ω
fRF = 169 MHz 74.5 + j48.5 Ω
1Measured as maximum unmodulated power.
2Suitable for ETSI 500 mW Tx requirements.
3Conductive filtered harmonic emissions measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor).
RECEIVER SPECIFICATIONS
LBW = loop bandwidth and IFBW = IF filter bandwidth.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DATA RATE Limited by the IF filter bandwidth1
2FSK 0.05 9.0 kbps IFBW = 9 kHz
0.05 13.5 kbps IFBW = 13.5 kHz
0.05 18.5 kbps IFBW = 18.5 kHz
3FSK 0.05 18.5 kbps IFBW = 18.5 kHz
4FSK 0.05 24 kbps IFBW = 18.5 kHz
SENSITIVITY Bit error rate (BER) = 10−3
2FSK
Sensitivity at 0.25 kbps −125 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 1 kbps −122 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 2.4 kbps −119 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 4.8 kbps −116 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 9.6 kbps −114 dBm fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz
Gaussian 2FSK
Sensitivity at 0.25 kbps −125 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 1 kbps −122 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 2.4 kbps −120 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 4.8 kbps −117 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 9.6 kbps −114 dBm fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz
GMSK
Sensitivity at 4.8 kbps −114.5 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz

ADF7021-V
Rev. 0 | Page 7 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
Raised Cosine 2FSK
Sensitivity at 0.25 kbps −125 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 1 kbps −121 dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 2.4 kbps −120 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 4.8 kbps −115 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz
Sensitivity at 9.6 kbps −114 dBm fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz
3FSK
Sensitivity at 4.8 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 18.5 kHz,
Viterbi detection on
Raised Cosine 3FSK
Sensitivity at 4.8 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 13.5 kHz,
alpha = 0.5, Viterbi detection on
4FSK
Sensitivity at 4.8 kbps −112 dBm fDEV (inner)2= 1.2 kHz, high sensitivity mode, IFBW = 13.5
kHz
Raised Cosine 4FSK
Sensitivity at 4.8 kbps −109 dBm fDEV (inner)2= 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz,
alpha = 0.5
INPUT IP3 Two-tone test, fLO = 860 MHz, f1 = fLO + 100 kHz,
f2 = fLO − 800 kHz
Low Gain, Enhanced Linearity
Mode
−3 dBm LNA_GAIN = 3, MIXER_LINEARITY = 1
Medium Gain Mode −13.5 dBm LNA_GAIN = 10, MIXER_LINEARITY = 0
High Sensitivity Mode −24 dBm LNA_GAIN = 30, MIXER_LINEARITY = 0
ADJACENT CHANNEL REJECTION
(ACR)
868 MHz Desired signal is 3 dB above the sensitivity point of
−109.5 dBm as per EN 300 220; rejection is measured as the
level of an unmodulated interferer to cause a BER of 10−2 for
the desired signal
12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz
25 kHz Channel Spacing −39 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz
12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz
25 kHz Channel Spacing −40 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz
12.5 kHz Channel Spacing −59.5 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz
25 kHz Channel Spacing −42 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz
12.5 kHz Channel Spacing −63 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz
25 kHz Channel Spacing −45 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz
25 kHz Channel Spacing −57 dBm IFBW = 18.5 kHz, data rate = 9.6 kbps, fDEV = 4.8 kHz, LBW = 6 kHz
460 MHz Desired signal is at −106.5 dBm; rejection is measured as the
level of an unmodulated interferer to cause a BER of 10−2 for
the desired signal
12.5 kHz Channel Spacing −59.5 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz
25 kHz Channel Spacing −37.5 dBm IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz
12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz
25 kHz Channel Spacing −41 dBm IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz
12.5 kHz Channel Spacing −62 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz
25 kHz Channel Spacing −43 dBm IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz
12.5 kHz Channel Spacing −61.5 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz
25 kHz Channel Spacing −44.5 dBm IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz
25 kHz Channel Spacing −56 dBm IFBW = 18.5 kHz, data rate = 9.6 kbps, fDEV = 4.8 kHz, LBW = 6 kHz
COCHANNEL REJECTION Desired signal is 3 dB above the sensitivity point of
−109.5 dBm; rejection is measured as the level of an
interferer to cause a BER of 10−2 for the desired signal
868 MHz −5 dB IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz

ADF7021-V
Rev. 0 | Page 8 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
IMAGE CHANNEL REJECTION Desired signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 3 dB
above the sensitivity point (BER = 10−2); modulated inter-
ferer (2FSK, 9.6 kbps, ±4 kHz deviation) is placed at the
image frequency of fRF − 200 kHz; the interferer level is
increased until BER = 10−2
868 MHz 26/39 dB Uncalibrated/calibrated,3VDD = 3.0 V, TA= 25°C
460 MHz 29/50 dB Uncalibrated/calibrated,3VDD = 3.0 V, TA= 25°C
BLOCKING
Desired signal is 3 dB above the sensitivity point of
−109.5 dBm; rejection is measured as the level of an
unmodulated interferer to cause a BER of 10−2 for the
desired signal; as per ETSI EN 300 220-1
±1 MHz −29.5 dBm
±2 MHz −26.5 dBm
±5 MHz −26 dBm
±10 MHz −25.5 dBm
SATURATION (MAXIMUM
INPUT LEVEL)
12 dBm 2FSK mode, BER = 10−3
RECEIVED SIGNAL STRENGTH
INDICATION (RSSI)
Input Power Range4−120 to −47 dBm
Linearity ±2 dB Input power range = −100 dBm to −47 dBm
Absolute Accuracy ±3 dB Input power range = −100 dBm to −47 dBm
Response Time 333 μs As per AGC gain stage, AGC clock = 3 kHz
AUTOMATIC FREQUENCY LOOP
(AFC)
Pull-In Range, Minimum 0.5 kHz Range is programmable in Register 10 (Bits[DB31:DB24])
Pull-In Range, Maximum 1.5 × IF_
FILTER_BW
kHz Range is programmable in Register 10 (Bits[DB31:DB24])
Response Time 96 Bits Dependent on modulation index
Accuracy 0.5 kHz Input power range = −100 dBm to +12 dBm
Rx SPURIOUS EMISSIONS5
External 920 MHz VCO −54/−88 dBm <1 GHz at antenna input, unfiltered conductive/filtered
conductive
External 920 MHz VCO −45/−66 dBm >1 GHz at antenna input, unfiltered conductive/filtered
conductive
External 1738 MHz VCO −85/−85 dBm <1 GHz at antenna input, unfiltered conductive/filtered
conductive
External 1738 MHz VCO −39/−52 dBm >1 GHz at antenna input, unfiltered conductive/filtered
conductive
LNA INPUT IMPEDANCE RFIN to RFGND; refer to the AN-859 Application Note for
other frequencies
fRF = 915 MHz 24 − j60 Ω
fRF = 868 MHz 26 − j63 Ω
fRF = 470 MHz 58 − j124 Ω
fRF = 450 MHz 63 − j129 Ω
fRF = 426 MHz 68 − j134 Ω
fRF = 315 MHz 96 − j160 Ω
fRF = 175 MHz 178 − j190 Ω
fRF = 169 MHz 182.5 − j194 Ω
1Using Gaussian or raised cosine filtering. The frequency deviation should be chosen to ensure that the transmit-occupied signal bandwidth is within the receiver
IF filter bandwidth.
24FSK fDEV is defined as the frequency spacing from the RF carrier to +fDEV or −fDEV. It is also equal to half the frequency spacing between adjacent symbols.
3Calibration of the image rejection used an external RF source.
4For received signal levels < −100 dBm, it is recommended that the RSSI readback value be averaged over a number of samples to improve RSSI accuracy at low input power.
5Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor).

ADF7021-V
Rev. 0 | Page 9 of 60
DIGITAL SPECIFICATIONS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
TIMING INFORMATION
Chip Enabled to Regulator
Ready
50 μs CREG[1:4] = 100 nF
Chip Enabled to Tx Mode 32-bit register write time = 50 μs
TCXO Reference 1 ms Depends on VCO settling
XTAL 2 ms Depends on VCO settling
Chip Enabled to Rx Mode 32-bit register write time = 50 μs, IF filter coarse
calibration only
TCXO Reference 1.2 ms Depends on VCO settling
XTAL 2.2 ms Depends on VCO settling
Tx-to-Rx Turnaround Time AGC settling +
(5 × tBIT)
ms
Time to synchronized data output; includes AGC
settling (three AGC levels) and CDR synchronization;
tBIT = data bit period; AFC settling not included
LOGIC INPUTS
Input High Voltage, VINH 0.7 × VDD V
Input Low Voltage, VINL 0.2 × VDD V
Input Current, IINH/IINL ±1 μA
Input Capacitance, CIN 10 pF
Control Clock Input 50 MHz
LOGIC OUTPUTS
Output High Voltage, VOH VDD2 − 0.4 V IOH = 500 μA
Output Low Voltage, VOL 0.4 V IOL = 500 μA
CLKOUT Rise/Fall Time 5 ns
CLKOUT Load 10 pF

ADF7021-V
Rev. 0 | Page 10 of 60
GENERAL SPECIFICATIONS
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE RANGE (TA) −40 +85 °C
POWER SUPPLIES
Voltage Supply, VDD 2.3 3.6 V All VDDx pins must be tied together
TRANSMIT CURRENT CONSUMPTION1, 2V
DD = 3.0 V, PA is matched into 50 Ω
868 MHz
0 dBm 17.6 mA
5 dBm 20.8 mA
10 dBm 27.1 mA
460 MHz
0 dBm 13.8 mA
5 dBm 17 mA
10 dBm 23 mA
RECEIVE CURRENT CONSUMPTION2 V
DD = 3.0 V
868 MHz
Low Current Mode 19.3 mA
High Sensitivity Mode 21.7 mA
460 MHz
Low Current Mode 16.3 mA
High Sensitivity Mode 18.3 mA
POWER-DOWN CURRENT CONSUMPTION2
Low Power Sleep Mode 0.1 1 μA CE low
1The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards.
Improved PA efficiency is achieved by using a separate PA matching network.
2Device current only. VCO and TCXO currents are excluded.
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, GND = 0 V, TA= 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 6.
Parameter Limit at TMIN to TMAX Unit Description
t1>10 ns SDATA to SCLK setup time
t2>10 ns SDATA to SCLK hold time
t3>25 ns SCLK high duration
t4>25 ns SCLK low duration
t5>10 ns SCLK to SLE setup time
t6>20 ns SLE pulse width
t8<25 ns SCLK to SREAD data valid, readback
t9<25 ns SREAD hold time after SCLK, readback
t10 >10 ns SCLK to SLE disable time, readback
t11 5 < t11 < (¼ × tBIT) ns TxRxCLK negative edge to SLE
t12 >5 ns TxRxDATA to TxRxCLK setup time (Tx mode)
t13 >5 ns TxRxCLK to TxRxDATA hold time (Tx mode)
t14 5 < t14 < (¼ × tBIT) μs TxRxCLK negative edge to SLE
t15 >¼ × tBIT μs SLE positive edge to positive edge of TxRxCLK (Rx mode)

ADF7021-V
Rev. 0 | Page 11 of 60
TIMING DIAGRAMS
Serial Interface
SCLK
SLE
DB31 (MSB) DB30 DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
S
DATA DB0 (LSB)
(CONTROL BIT C1)
t
6
t
1
t
2
t
3
t
4
t
5
08635-002
Figure 2. Serial Interface Timing Diagram
t8
t3
t1t2
t10
t9
XRV16
RV15 RV2
SCLK
SDATA
SLE
SREAD
REG 7 DB0
(CONTROL BIT C1)
RV1 X
08635-003
Figure 3. Serial Interface Readback Timing Diagram
2FSK/3FSK Timing
TxRxCLK
DATA
T
xRxDATA
±1 × DATA RATE/32 1/DATA RATE
08635-004
Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode
TxRxCLK
DATA
TxRxDATA
SAMPLEFETCH
1/DATA RATE
08635-005
Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode

ADF7021-V
Rev. 0 | Page 12 of 60
4FSK Timing
In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by detection of the SWD pin in the receive bit stream.
Rx SYMBOL
MSB Rx SYMBOL
LSB Rx SYMBOL
MSB Rx SYMBOL
LSB Tx SYMBOL
MSB
Tx SYMBOL
LSB
TxRxDATA
TxRxCLK
SLE
Rx MODE Tx MODE
REGISTER 0 WRITE
SWITCH FROM Rx TO Tx
Tx/Rx MODE
Tx SYMBOL
MSB
t
11
t
12
t
13
t
BIT
t
SYMBOL
08635-006
Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode
Tx SYMBOL
MSB Tx SYMBOL
LSB Tx SYMBOL
MSB Tx SYMBOL
LSB Rx SYMBOL
LSB
Rx SYMBOL
MSB
TxRxDATA
TxRxCLK
SLE
Tx MODE Rx MODE
REGISTER 0 WRITE
SWITCH FROM Tx TO Rx
Tx/Rx MODE
t
15
t
14
t
BIT
t
SYMBOL
08635-007
Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode

ADF7021-V
Rev. 0 | Page 13 of 60
UART/SPI Mode
UART mode is enabled by setting Register 0, Bit DB28 to 1. SPI mode is enabled by setting Register 0, Bit DB28 to 1 and setting Register 15,
Bits[DB19:DB17] to 0x7. The transmit/receive data clock is available on the CLKOUT pin.
Tx BIT Tx BIT Tx BIT Tx BIT
TxRxCLK
(TRANSMIT DATA INPUT
IN UART/SPI MODE.)
CLKOUT
(TRANSMIT/RECEIVE DATA
CLOCK IN SPI MODE.
NOT USED IN UART MODE.)
Tx MODE
Tx/Rx MODE
TxRxDATA
(RECEIVE DATA OUTPUT
IN UART/SPI MODE.) HIGH-Z
Tx BIT
t
BIT
FETCH SAMPLE
0
8635-008
Figure 8. Transmit Timing Diagram in UART/SPI Mode
Rx BIT Rx BIT Rx BIT Rx BIT
TxRxCLK
(TRANSMIT DATA INPUT
IN UART/SPI MODE.)
CLKOUT
(TRANSMIT/RECEIVE DAT
A
CLOCK IN SPI MODE.
NOT USED IN UART MODE.)
Rx MODE
Tx/Rx MODE
TxRxDATA
(RECEIVE DATA OUTPUT
IN UART/SPI MODE.)
HIGH-Z
Rx BIT
t
BIT
FETCH SAMPLE
0
8635-009
Figure 9. Receive Timing Diagram in UART/SPI Mode

ADF7021-V
Rev. 0 | Page 14 of 60
ABSOLUTE MAXIMUM RATINGS
TA= 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter Rating
VDD to GND1−0.3 V to +5 V
Analog I/O Voltage to GND1−0.3 V to VDDx + 0.3 V
Digital I/O Voltage to GND1−0.3 V to VDDx + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
MLF θJA Thermal Impedance 26°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
1 GND = GND1 = GND2 = GND4 = RFGND = 0 V.

ADF7021-V
Rev. 0 | Page 15 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
08635-011
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFIN
R
LNA
VDD4
RSET
CREG4
GND4
MIX_I MIX_I
MIX_Q MIX_Q
FILT_I FILT_I
GND4
FILT_Q FILT_Q
GND4
TEST_A
CE
CLKOUT
TxRxDATA
TxRxCLK
SWD
VDD2
CREG2
ADCIN
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE GROUND PLANE.
GND2
SCLK
SREAD
SDATA
SLE
CVCO GND1 L1 GND L2 VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT
1
2
3
4
5
6
7
8
9
10
11
12
PIN 1
INDICATOR
ADF7021-V
TOP VIEW
(Not to Scale)
Figure 10. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCOIN Do not connect.
2 CREG1 Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
3 VDD1 Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this
pin. Tie all VDDx pins together.
4 RFOUT The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components.
5 RFGND Ground for Output Stage of Transmitter. Tie all GND pins together.
6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer.
7 RFIN Complementary LNA Input.
8 RLNA External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9 VDD4 Voltage Supply for LNA/Mixer Block. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins
together.
10 RSET External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with
5% tolerance.
11 CREG4 Regulator Voltage for LNA/Mixer Block. Place a 100 nF capacitor between this pin and ground for
regulator stability and noise rejection.
12, 19, 22 GND4 Ground for LNA/Mixer Block. Tie all GND pins together.
13 to 16 MIX_I, MIX_I,
MIX_Q, MIX_Q
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
17, 18, 20,
21
FILT_I, FILT_I,
FILT_Q, FILT_Q,
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
23 TEST_A Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected.
24 CE Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost
when CE is low, and the part must be reprogrammed after CE is brought high.
25 SLE Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of
the 16 latches. A latch is selected using the control bits.
26 SDATA Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a
high impedance CMOS input.

ADF7021-V
Rev. 0 | Page 16 of 60
Pin No. Mnemonic Description
27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7021-V to the microcontroller. The
SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
28 SCLK Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched
into the 32-bit shift register on the SCLK rising edge. This pin is a digital CMOS input.
29 GND2 Ground for Digital Block. Tie all GND pins together.
30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is
0 V to 1.9 V. Readback is through the SREAD pin.
31 CREG2 Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator
stability and noise rejection.
32 VDD2 Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie
all VDDx pins together.
33 SWD Sync Word Detect. The ADF7021-V asserts this pin when it finds a match for the sync word sequence.
This provides an interrupt for an external microcontroller, indicating that valid data is being received.
34 TxRxDATA
Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In UART/SPI
receive mode, this pin provides an output for the received data. In UART/SPI transmit mode, this pin is
high impedance.
35 TxRxCLK Outputs the data clock in both receive and transmit modes. This is a digital pin, and normal CMOS levels
apply. The positive clock edge is matched to the center of the received data. In standard transmit mode,
this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at
the exact required data rate. In UART/SPI transmit mode, this pin is used to input the transmit data. In
UART/SPI receive mode, this pin is high impedance.
36 CLKOUT Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used
to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark/space
ratio and is inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the
pin in applications where the CLKOUT feature is used.
37 MUXOUT
Provides the DIGITAL_LOCK_DETECT signal. This signal is used to determine whether the PLL is locked to
the correct frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of
the status of the serial interface regulator.
38 OSC2 Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this
pin with CMOS levels and disabling the internal crystal oscillator.
39 OSC1 Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this
pin with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator.
40 VDD3 Voltage Supply for Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor. Tie
all VDDx pins together.
41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
43 VDD Voltage Supply for RF Circuitry. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie
all VDDx pins together.
44 L2 VCO Buffer Input.
45 GND Ground. Tie all GND pins together.
46 L1 Do not connect.
47 GND1 Ground. Tie all GND pins together.
48 CVCO Do not connect.
EP Exposed Paddle The exposed paddle must be connected to the ground plane.

ADF7021-V
Rev. 0 | Page 17 of 60
TYPICAL PERFORMANCE CHARACTERISTICS
–
80
–90
–100
–110
–120
–130
–140
–150
–1601 10 100 1k 10k 100k
FREQUENCY OFFSET (kHz)
PHASE NOISE (dBc/Hz)
08635-077
RF FREQ = 460MHz
TCXO = 19.2MHz
I
CP
= 0.3mA
I
CP
= 0.9mA
Figure 11. Phase Noise Response at 460 MHz, VDD = 3 V
–
60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–1601 10 100 1k 10k
FREQUENCY OFFSET (kHz)
PHASE NOISE (dBc/Hz)
08635-078
I
CP
= 0.3mA
I
CP
= 0.9mA
I
CP
= 1.5mA
I
CP
= 2.1mA
RF FREQ = 868MHz
TCXO = 19.2MHz
Figure 12. Phase Noise Response at 868 MHz, VDD = 2.3 V
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–25,000 –20,000 –15,000 –10,000
–5000
0
5000
10,000 15,000 20,000 25,000
FREQUENCY OFFSET FROM CARRIER (Hz)
OUTPUT POWER (dBm)
08635-079
FCC PART 90
EMISSION MASK D
DEMODULATION = GFSK
DATA RATE = 2.4kbps
fDEV = 1.2kHz
RF FREQ = 470MHz
IFBW = 4kHz
Figure 13. Output Spectrum in FCC Part 90 Emission Mask D
and GFSK Modes
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
4
8
12
16
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
PA SETTING
RF OUTPUT POWER (dBm)
PA_BIAS = 5µA
PA_BIAS = 11µA
PA_BIAS = 9µA
PA_BIAS = 7µA
08635-012
Figure 14. RF Output Power vs. PA Setting
20
0
–20
–40
–60
–80
–100
300 800 1300 1800 2300 2800
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-013
Figure 15. PA Output Harmonic Response with T-Stage LC Filter
10
0
–10
–20
–30
–40
–50
–60
–70
–80
867.97 867.98 867.99 868.00 868.01 868.02 868.03
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-014
2FSK
GFSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
Figure 16. Output Spectrum in 2FSK and GFSK Modes

ADF7021-V
Rev. 0 | Page 18 of 60
10
0
–10
–20
–30
–40
–50
–60
–70
–80
867.97 867.98 867.99 868.00 868.01 868.02 868.03
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-015
2FSK
RC2FSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
Figure 17. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes
10
0
–10
–20
–30
–40
–50
–60
–70
–80
867.97 867.98 867.99 868.00 868.01 868.02 868.03
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-016
3FSK
RC3FSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
Figure 18. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
867.94 867.96 867.98 868.00 868.02 868.04 868.06
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-017
4FSK
RC4FSK
DATA RATE = 9.6kbps
DATA = PRBS9
f
DEV
= 2.4kHz
RF FREQ = 868MHz
Figure 19. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes
FREQUENCY OFFSET (kHz)
OUTPUT POWER (dBm)
0
–10
10
–20
–30
–40
–100 –50 500 100
–50
–60
RAMP RATE:
CW ONLY
256 CODES/BIT
128 CODES/BIT
64 CODES/BIT
32 CODES/BIT
TRACE = MAX HOLD
PA ON/OFF RATE = 3Hz
PA ON/OFF CYCLES = 10,000
V
DD
= 3.0V
08635-018
Figure 20. Output Spectrum in Maximum Hold
for Various PA Ramp Rate Options
0
–1
–2
–3
–4
–5
–6
–7
–125 –123 –121 –119 –117 –115 –113 –111 –109 –107 –105
RF INPUT POWER (dBm)
LOG BE
R
08635-019
DATA RATE = 2.4kbps
f
DEV
= 4.8Hz
RF FREQ = 868MHz
IFBW = 9kHz
–40°C, 2.3V
–40°C, 3V
–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
+25°C, 3.6V
+85°C, 2.3V
+85°C, 3V
+85°C, 3.6V
Figure 21. 2FSK Sensitivity vs. VDD and Temperature at 868 MHz
0
–1
–2
–3
–4
–5
–6
–7
–127 –125 –123 –121 –119 –117 –115 –113 –111
RF INPUT POWER (dBm)
LOG BE
R
08635-020
DATA RATE = 1.2kbps
f
DEV
= 2.4Hz
RF FREQ = 460MHz
IFBW = 9kHz
–40°C, 2.3V
–40°C, 3V
–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
+25°C, 3.6V
+85°C, 2.3V
+85°C, 3V
+85°C, 3.6V
Figure 22. 2FSK Sensitivity vs. VDD and Temperature at 460 MHz

ADF7021-V
Rev. 0 | Page 19 of 60
0.6
0.5
0.4
0.3
0.2
0.1
0
–130 –125 –120 –115 –110 –105
RF INPUT POWER (dBm)
BIT ERROR RATE
08635-021
–40°C, 2.3V
–40°C, 3V
–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
+25°C, 3.6V
+85°C, 2.3V
+85°C, 3V
+85°C, 3.6V
DATA RATE = 1.2kbps
f
DEV
= 2.4Hz
RF FREQ = 868MHz
IFBW = 9kHz
Figure 23. 2FSK Sensitivity vs. VDD and Temperature at 868 MHz
0.6
0.5
0.4
0.3
0.2
0.1
0
–130 –125 –120 –115 –110 –105
RF INPUT POWER (dBm)
BIT ERROR RATE
08635-022
–40°C, 2.3V
–40°C, 3V
–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
+25°C, 3.6V
+85°C, 2.3V
+85°C, 3V
+85°C, 3.6V
DATA RATE = 1.2kbps
f
DEV
= 2.4Hz
RF FREQ = 460MHz
IFBW = 9kHz
Figure 24. 2FSK Sensitivity vs. VDD and Temperature at 460 MHz
90
100
70
50
30
10
80
60
40
20
0
–10
–20 –15 –10 –5 0 5 10 15 20
FREQUENCY OFFSET (MHz)
BLOCKING (dB)
08635-024
Figure 25. Wideband Interference Rejection (Modulated Carrier Is Swept 20 MHz
Either Side of an 868 MHz Modulated GFSK 2.4 kHz/4.8 kbps Wanted Signal at the
Sensitivity Point (−106.5 dBm); the Power Level of the Blocker Is Adjusted to
Give a BER of 10−2; Interferer Is a GFSK PRBS15 4.8 kHz/2.4 kHz Signal)
–140
–120
–100
–80
–60
–40
–
20
–122.5 –112.5 –102.5 –92.5 –82.5 –72.5 –62.5 –52.5 –42.5
ACTUAL RF INPUT LEVEL
RF INPUT POWER (dBm)
RSSI LEVEL (dBm)
RSSI
READBACK LEVEL
08635-023
Figure 26. Digital RSSI Readback Linearity
80
70
60
50
40
30
20
10
0
–10
459.75 459.70 459.80 459.85 459.90 459.95 460.00 460.05 460.10 460.15
BLOCKER FREQUENCY (MHz)
BLOCKING (dB)
08635-080
CALIBRATED
UNCALIBRATED
Figure 27. Image Rejection, Uncalibrated vs. Calibrated
08635-025
2.5
0
–2.5
–5.0
–7.5
–10.0
–12.5
–15.0
–17.5
–20.0
–22.5
–25.0
–27.5
–30.0
–32.5
–35.0
–37.590 92 94 96 98 100 102 104 106 108 110
ATTENUATION (dB)
IF FREQUENCY (kHz)
–40°C
+90°C
Figure 28. Variation of IF Filter Response with Temperature
(IF_FILTER_BW = 9 kHz, Temperature Range Is −40°C to +90°C in 10° Steps)

ADF7021-V
Rev. 0 | Page 20 of 60
LNA GAIN, FILTER GAIN
SENSITIVITY (dBm)
–130
–120
–110
–100
–90
–80
–
70
3, 72
(LOW GAIN MODE)
10, 72
(MEDIUM GAIN MODE)
30, 72
(HIGH GAIN MODE)
HIGH MIXER
LINEARITY
DEFAULT
MIXER
LINEARITY
2FSK MODULATION
DATA RATE = 9.6kbps
f
DEV
= 4kHz
IFBW = 12.5kHz
DEMOD = CORRELATOR
SENSITIVITY @ BER = 10
–3
IP3 = –3dBm
IP3 = –5dBm
IP3 = –9dBm
IP3 = –13.5dBm
IP3 = –24dBm
IP3 = –20dBm
08635-028
MODULATION INDEX
SENSITIVITY POINT (dBm)
–118
–116
–114
–112
–110
–108
–106
–104
–102
–
100
0 0.2 0.4 0.6 0.8 1.0 1.2
RF FREQ = 860MHz
2FSK MODULATION
DATA RATE = 9.6kbps
IFBW = 25kHz
VDD = 3.0V
TEMPERATURE = 25°C
DISCRIMINATOR BANDWIDTH =
1× FSK FREQUENCY DEVIATION
DISCRIMINATOR BANDWIDTH =
2× FSK FREQUENCY DEVIATION
08635-026
Figure 31. 2FSK Receiver Sensitivity vs. LNA Gain/IF Filter Gain and Mixer
Linearity Settings (Input IP3 at Each Setting Also Shown)
Figure 29. 2FSK Sensitivity vs. Modulation Index and Correlator
Discriminator Bandwidth
–120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100
3FSK MODULATION
V
DD
= 3.0V, TEMP = 25°C
DATA RATE = 9.6kbps
f
DEV
= 2.4kHz
RF FREQ = 868MHz
IFBW = 18.75kHz
INPUT POWER (dBm)
LOG BER
–7
–6
–5
–4
–3
–2
–1
0
VITERBI DETECTION
THRESHOLD DETECTION
08635-027
Figure 30. 3FSK Receiver Sensitivity Using Viterbi Detection and
Threshold Detection