Analog Devices ADSP-21261 SHARC Application guide

a
ADSP-2126x SHARC®Processor
Hardware Reference
Includes ADSP-21261, ADSP-21262
ADSP-21266, ADSP-21267
Revision 5.1, April 2013
Part Number
82-002002-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information
© 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
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third parties which may result from its use. No license is granted by impli-
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The Analog Devices logo, Blackfin, SHARC, TigerSHARC, CrossCore,
VisualDSP++, and EZ-KIT Lite are registered trademarks of Analog
Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.

ADSP-2126x SHARC Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual ............................................................. xxxi
Intended Audience ...................................................................... xxxi
Manual Contents ....................................................................... xxxii
What’s New in This Manual ...................................................... xxxiv
Technical Support ..................................................................... xxxiv
Supported Processors .................................................................. xxxv
Product Information .................................................................. xxxv
Analog Devices Web Site ..................................................... xxxvi
EngineerZone ...................................................................... xxxvi
Notation Conventions .............................................................. xxxvii
Register Diagram Conventions ................................................ xxxviii
INTRODUCTION
Design Advantages ........................................................................ 1-1
Architectural Overview ................................................................. 1-4

Contents
iv ADSP-2126x SHARC Processor Hardware Reference
Processor Core ........................................................................ 1-5
Processing Elements ............................................................ 1-5
Program Sequence Control ................................................. 1-6
Processor Internal Buses ...................................................... 1-9
Processor Peripherals ............................................................. 1-10
Dual-Ported Internal Memory (SRAM) ............................. 1-10
I/O Processor ................................................................... 1-11
Digital Audio Interface (DAI) ........................................... 1-13
Development Tools ..................................................................... 1-13
Differences From Previous SHARCs ............................................ 1-14
Processor Core Enhancements ............................................... 1-15
Processor Internal Bus Changes ............................................. 1-15
Memory Organization Enhancements .................................... 1-16
Parallel Port Enhancements ................................................... 1-16
I/O Architecture Enhancements ............................................ 1-16
Instruction Set Enhancements ............................................... 1-16
PROCESSING ELEMENTS
Numeric Formats .......................................................................... 2-3
IEEE Single-precision Floating-point Data Format ................... 2-4
Extended-precision Floating-Point Format ............................... 2-6
Short Word Floating-Point Format .......................................... 2-7
Packing for Floating-Point Data .............................................. 2-7
Fixed-Point Formats ................................................................ 2-9

ADSP-2126x SHARC Processor Hardware Reference v
Contents
Setting Computational Modes ..................................................... 2-12
32-Bit Floating-Point Format (Normal Word) ........................ 2-12
40-Bit Floating-Point Format ................................................. 2-14
16-Bit Floating-Point Format (Short Word) ........................... 2-14
32-Bit Fixed-Point Format ..................................................... 2-15
Rounding Mode .................................................................... 2-15
Using Computational Status ........................................................ 2-16
Arithmetic Logic Unit (ALU) ...................................................... 2-17
ALU Operation ..................................................................... 2-17
ALU Saturation ..................................................................... 2-18
ALU Status Flags ................................................................... 2-19
ALU Instruction Summary .................................................... 2-20
Multiply Accumulator (Multiplier) .............................................. 2-23
Multiplier Operation ............................................................. 2-23
Multiplier Result Register (Fixed-Point) ................................. 2-24
Multiplier Status Flags ........................................................... 2-27
Multiplier Instruction Summary ............................................ 2-28
Barrel Shifter (Shifter) ................................................................. 2-30
Shifter Operation .................................................................. 2-31
Shifter Status Flags ................................................................ 2-35
Shifter Instruction Summary .................................................. 2-36
Data Register File ........................................................................ 2-38
Alternate (Secondary) Data Registers ........................................... 2-40
Multifunction Computations ...................................................... 2-41

Contents
vi ADSP-2126x SHARC Processor Hardware Reference
Secondary Processing Element (PEy) ........................................... 2-45
Dual Compute Units Sets ...................................................... 2-47
Dual Register Files ................................................................ 2-49
Dual Alternate Registers ........................................................ 2-50
SIMD and Status Flags .......................................................... 2-50
SIMD (Computational) Operations ....................................... 2-50
PROGRAM SEQUENCER
Instruction Pipeline ...................................................................... 3-4
Instruction Cache ......................................................................... 3-5
Bus Conflicts .......................................................................... 3-5
Block Conflicts ....................................................................... 3-7
Using the Cache ...................................................................... 3-8
Optimizing Cache Usage ......................................................... 3-9
Branches and Sequencing ............................................................ 3-11
Conditional Branches ............................................................ 3-12
Delayed Branches .................................................................. 3-13
Loop and Status Stacks and Sequencing ....................................... 3-16
Conditional Sequencing .............................................................. 3-17
Core Stalls .................................................................................. 3-21
Execution Stalls ..................................................................... 3-23
DAG Stalls ........................................................................... 3-24
Memory Stalls ....................................................................... 3-24
IOP Register Stalls ................................................................ 3-24
DMA Stalls ........................................................................... 3-24

ADSP-2126x SHARC Processor Hardware Reference vii
Contents
Loops and Sequencing ................................................................. 3-25
Restrictions on Ending Loops ................................................ 3-27
Restrictions on Short Loops ................................................... 3-28
Loop Address Stack ............................................................... 3-31
Loop Counter Stack .............................................................. 3-32
Reading From LCNTR in a LOOP .................................... 3-36
SIMD Mode and Sequencing ...................................................... 3-36
Conditional Compute Operations .......................................... 3-38
Conditional Branches and Loops ........................................... 3-38
Conditional Data Moves ........................................................ 3-38
Case #1: Complementary Register Pair Data Move ............. 3-39
Example 1: Register-to-Memory Move – PEx Explicit Register
3-39
Example 2: Register Move – PEy Explicit Register .......... 3-40
Example 3: Register-to-Memory Move – PEx Explicit Register
3-40
Example 4: Register-to-Memory Move – PEy Explicit Register
3-41
Case #2: Uncomplimentary-to-Complementary Register Move 3-42
Example: Register Moves – Uncomplimentary-to-Complementary
3-42
Case #3: Complementary-to-Uncomplimentary Register Move 3-43
Example: Register Moves – Complementary-to-Uncomplimentary
3-43

Contents
viii ADSP-2126x SHARC Processor Hardware Reference
Case #4: External Memory or IOP Memory Space Data Move 3-44
Example: Register-to-Memory Moves – External or IOP Memory
Space Data Move ....................................................... 3-44
Case #5: Uncomplimentary Register Data Move ................ 3-45
Conditional DAG Operations ............................................... 3-45
Timer and Sequencing ................................................................ 3-46
Interrupts and Sequencing .......................................................... 3-48
Delayed Interrupt Processing ................................................. 3-52
Sensing Interrupts ................................................................. 3-53
Masking Interrupts ............................................................... 3-54
Latching Interrupts ............................................................... 3-55
Stacking Status During Interrupts .......................................... 3-56
Nesting Interrupts ................................................................. 3-58
Reusing Interrupts ................................................................ 3-60
Interrupting IDLE ................................................................ 3-61
Summary .................................................................................... 3-61
DATA ADDRESS GENERATORS
Setting DAG Modes ..................................................................... 4-4
Circular Buffering Mode ......................................................... 4-5
Broadcast Loading Mode ......................................................... 4-5
Alternate (Secondary) DAG Registers ...................................... 4-6
Bit-Reverse Addressing Mode .................................................. 4-8
Using DAG Status ........................................................................ 4-9

ADSP-2126x SHARC Processor Hardware Reference ix
Contents
DAG Operations ........................................................................... 4-9
Addressing With DAGs ......................................................... 4-10
Data Addressing Stalls ........................................................... 4-12
Addressing Circular Buffers ................................................... 4-12
Modifying DAG Registers ...................................................... 4-17
Addressing in SISD and SIMD Modes ................................... 4-18
DAGs, Registers, and Memory .................................................... 4-19
DAG Register-to-Bus Alignment ............................................ 4-19
DAG Register Transfer Restrictions ........................................ 4-21
DAG Instruction Summary ......................................................... 4-23
MEMORY
Internal Memory ........................................................................... 5-2
DSP Architecture .................................................................... 5-2
Buses ............................................................................................ 5-3
Internal Address and Data Buses .............................................. 5-4
Internal Data Bus Exchange ..................................................... 5-6
ADSP-2126x Memory Map ......................................................... 5-10
Memory Organization and Word Size .................................... 5-12
Placing 32-Bit Words and 48-Bit Words ............................ 5-13
Mixing 32-Bit Words and 48-Bit Words ............................ 5-14
Restrictions on Mixing 32-Bit Words and 48-Bit Words ..... 5-16
Example: Calculating a Starting Address for 32-Bit Addresses 5-17
48-Bit Word Allocation ..................................................... 5-17
Internal Interrupt Vector Table .............................................. 5-18

Contents
x ADSP-2126x SHARC Processor Hardware Reference
Internal Memory Data Width ................................................ 5-18
Secondary Processor Element (PEy) ....................................... 5-19
Broadcast Register Loads ....................................................... 5-20
Illegal I/O Processor Register Access ...................................... 5-21
Unaligned 64-Bit Memory Access .......................................... 5-21
Using Memory Access Status ....................................................... 5-22
Accessing Memory ...................................................................... 5-22
Access Word Size ................................................................... 5-23
Long Word (64-Bit) Accesses ............................................ 5-23
Instruction and Extended-Precision Normal Word Accesses 5-25
Normal Word (32-Bit) Accesses ........................................ 5-26
Short Word (16-Bit) Accesses ............................................ 5-26
Setting Data Access Modes .................................................... 5-27
SYSCTL Register Control Bits .......................................... 5-27
Mode 1 Register Control Bits ............................................ 5-27
Mode 2 Register Control Bits ............................................ 5-28
SISD, SIMD, and Broadcast Load Modes .............................. 5-28
Single- and Dual-Data Accesses ............................................. 5-28
Instruction Examples ........................................................ 5-29
Shadow Write FIFO ................................................................... 5-29
Internal Memory Access Listings ................................................. 5-30
Short Word Addressing of Single-Data in SISD Mode ............ 5-32
Short Word Addressing of Dual-Data in SISD Mode .............. 5-34
Short Word Addressing of Single-Data in SIMD Mode .......... 5-36

ADSP-2126x SHARC Processor Hardware Reference xi
Contents
Short Word Addressing of Dual-Data in SIMD Mode ............ 5-38
32-Bit Normal Word Addressing of Single-Data in SISD Mode 5-40
32-Bit Normal Word Addressing of Dual-Data in SISD Mode 5-42
32-Bit Normal Word Addressing of Single-Data in SIMD Mode 5-44
32-Bit Normal Word Addressing of Dual-Data in SIMD Mode 5-46
Extended-Precision Normal Word Addressing of Single-Data .. 5-48
Extended-Precision Normal Word Addressing of Dual-Data ... 5-50
Long Word Addressing of Single-Data .................................... 5-52
Long Word Addressing of Dual-Data ..................................... 5-54
Broadcast Load Access ........................................................... 5-56
Mixed-Word Width Addressing of Long Word with Short Word 5-65
Mixed-Word Width Addressing of Long Word with Extended Word
5-67
JTAG TEST EMULATION PORT
JTAG Test Access Port ................................................................... 6-1
Boundary Scan .............................................................................. 6-2
Background Telemetry Channel (BTC) .......................................... 6-4
User-Definable Breakpoint Interrupts ............................................ 6-4
Restrictions ............................................................................. 6-5
Cycle Count Functionality (EMUCLK) Register ...................... 6-5
Silicon Revision ID ................................................................. 6-5
JTAG Related Registers ................................................................. 6-5
Instruction Register ................................................................. 6-6
Enhanced Emulation Status (EEMUSTAT) Register ................. 6-8

Contents
xii ADSP-2126x SHARC Processor Hardware Reference
Boundary Register ................................................................... 6-8
Built-In Self-Test Operation (BIST) ........................................ 6-9
EMUIDLE Instruction ........................................................... 6-9
Private Instructions ....................................................................... 6-9
References .................................................................................... 6-9
I/O PROCESSOR
General Procedure for Configuring DMA ...................................... 7-2
IOP/Core Interaction Options ...................................................... 7-3
Interrupt-Driven I/O .............................................................. 7-3
Polling/Status Driven I/O ....................................................... 7-7
DMA Controller Operation .................................................... 7-8
Chaining DMA Processes .................................................. 7-10
Transfer Control Block Chain Loading (TCB) ................... 7-13
Setting Up and Starting the Chain .................................... 7-14
Setting Up and Starting Chained DMA over the SPI ......... 7-14
Inserting a TCB in an Active Chain .................................. 7-16
Setting Up DMA Channel Allocation and Priorities ............... 7-17
Managing DMA Channel Priority ..................................... 7-18
DMA Bus Arbitration ....................................................... 7-19
Setting Up DMA Parameter Registers .......................................... 7-21
DMA Transfer Direction ....................................................... 7-21
Data Buffer Registers ............................................................ 7-23
Port, Buffer, and DMA Control Registers .............................. 7-24
Addressing ............................................................................ 7-26

ADSP-2126x SHARC Processor Hardware Reference xiii
Contents
Setting Up DMA ........................................................................ 7-30
PARALLEL PORT
Parallel Port Pins ........................................................................... 8-3
Alternate Pin Functions ........................................................... 8-4
Parallel Ports as FLAG Pins ................................................. 8-4
Parallel Data Acquisition Port as Address Pins ...................... 8-5
Parallel Port Operation .................................................................. 8-5
Basic Parallel Port External Transaction .................................... 8-5
Reading From an External Device or Memory .......................... 8-6
Writing to an External Device or Memory ................................ 8-7
Transfer Protocol ..................................................................... 8-8
8-Bit Mode ......................................................................... 8-9
16-Bit Mode ....................................................................... 8-9
Comparison of 16-Bit and 8-Bit SRAM Modes ...................... 8-11
Parallel Port Interrupt ................................................................. 8-12
Parallel Port Throughput ............................................................. 8-12
8-Bit Access ........................................................................... 8-14
16-Bit Access ......................................................................... 8-14
Conclusion ............................................................................ 8-15
Parallel Port Registers .................................................................. 8-15
Parallel Port DMA Registers ................................................... 8-16
Parallel Port External Setup Registers ..................................... 8-17

Contents
xiv ADSP-2126x SHARC Processor Hardware Reference
Using the Parallel Port ................................................................ 8-17
DMA Transfers ..................................................................... 8-18
Core Driven Transfers ........................................................... 8-18
Known Duration Accesses ................................................. 8-20
Status Driven Transfers (Polling) ....................................... 8-22
Core-Stall Driven Transfers ............................................... 8-22
Interrupt Driven Accesses ................................................. 8-22
Parallel Port Programming Examples ........................................... 8-23
SERIAL PORTS
Serial Port Signals ......................................................................... 9-5
SPORT Operation Modes ............................................................. 9-9
Standard DSP Serial Mode .................................................... 9-11
Standard DSP Serial Mode Control Bits ............................ 9-11
Clocking Options ............................................................ 9-11
Frame Sync Options ......................................................... 9-12
Data Formatting ............................................................... 9-12
Data Transfers .................................................................. 9-13
Status Information ........................................................... 9-13
Left-Justified Sample Pair Mode ............................................ 9-14
Setting the Internal Serial Clock and Frame Sync Rates ..... 9-15
Left-Justified Sample Pair Mode Control Bits .................... 9-15
Setting Word Length (SLEN) ............................................ 9-15
Enabling SPORT Master Mode (MSTR) ........................... 9-16
Selecting Transmit and Receive Channel Order (FRFS) ..... 9-16

ADSP-2126x SHARC Processor Hardware Reference xv
Contents
Selecting Frame Sync Options (DIFS) ............................... 9-16
Enabling SPORT DMA (SDEN) ....................................... 9-17
Interrupt-Driven Data Transfer Mode ............................ 9-17
DMA-Driven Data Transfer Mode ................................. 9-17
I2S Mode .............................................................................. 9-18
I2S Mode Control Bits ...................................................... 9-20
Setting the Internal Serial Clock and Frame Sync Rates ...... 9-20
I2S Control Bits ................................................................ 9-20
Setting Word Length (SLEN) ............................................ 9-21
Enabling SPORT Master Mode (MSTR) ........................... 9-21
Selecting Transmit and Receive Channel Order (FRFS) ...... 9-21
Selecting Frame Sync Options (DIFS) ............................... 9-22
Enabling SPORT DMA (SDEN) ....................................... 9-22
Interrupt-Driven Data Transfer Mode ............................ 9-23
DMA-Driven Data Transfer Mode ................................. 9-23
Multichannel Operation ........................................................ 9-24
Frame Syncs in Multichannel Mode ................................... 9-26
Active State Multichannel Receive Frame Sync Select ..... 9-27
Multichannel Mode Control Bits ....................................... 9-27
Receive Multichannel Frame Sync Source ....................... 9-29
Active State Transmit Data Valid ................................... 9-29
Multichannel Status Bits ................................................ 9-29
Channel Selection Registers ........................................... 9-30
SPORT Loopback ............................................................. 9-32

Contents
xvi ADSP-2126x SHARC Processor Hardware Reference
Clock Signal Options .................................................................. 9-33
Frame Sync Options ................................................................... 9-34
Framed Versus Unframed Frame Syncs ................................... 9-34
Internal Versus External Frame Syncs ..................................... 9-35
Active Low Versus Active High Frame Syncs .......................... 9-36
Sampling Edge for Data and Frame Syncs .............................. 9-36
Early Versus Late Frame Syncs ............................................... 9-37
Data-Independent Frame Sync .............................................. 9-38
Data Word Formats .................................................................... 9-39
Word Length ........................................................................ 9-39
Endian Format ...................................................................... 9-40
Data Packing and Unpacking ................................................ 9-40
Data Type ........................................................................ 9-41
Companding .................................................................... 9-42
SPORT Control Registers and Data Buffers ................................ 9-44
Register Writes and Effect Latency ......................................... 9-50
Serial Port Control Registers (SPCTLx) ................................. 9-50
Transmit and Receive Data Buffers ........................................ 9-60
Clock and Frame Sync Frequencies (DIV) ............................. 9-62
SPORT Interrupts ................................................................ 9-64
Moving Data Between SPORTS and Internal Memory ................ 9-65
DMA Block Transfers ............................................................ 9-66
Setting Up DMA on SPORT Channels ............................. 9-68

ADSP-2126x SHARC Processor Hardware Reference xvii
Contents
SPORT DMA Parameter Registers ......................................... 9-69
SPORT DMA Chaining .................................................... 9-73
Single Word Transfers ............................................................ 9-73
SPORT Programming Examples .................................................. 9-74
SERIAL PERIPHERAL INTERFACE PORT
Functional Description ............................................................... 10-2
SPI Interface Signals ................................................................... 10-3
SPI Clock Signal (SPICLK) .................................................. 10-4
SPICLK Timing ................................................................ 10-5
SPI Slave Select Outputs (SPIDS0-3) ................................. 10-5
SPI Device Select Signal ........................................................ 10-6
Master Out Slave In (MOSI) ................................................. 10-6
Master In Slave Out (MISO) ................................................. 10-6
SPI General Operations ............................................................... 10-7
SPI Enable ............................................................................ 10-8
Open Drain Mode (OPD) ..................................................... 10-8
Master Mode Operation ........................................................ 10-9
Slave Mode Operation ......................................................... 10-10
Multimaster Conditions ....................................................... 10-11
SPI Data Transfer Operations .................................................... 10-12
Core Transmit and Receive Operations ................................. 10-12
SPI DMA ............................................................................ 10-12
Master Mode DMA Operation ........................................ 10-14
Master Transfer Preparation ......................................... 10-16

Contents
xviii ADSP-2126x SHARC Processor Hardware Reference
Slave Mode DMA Operation .......................................... 10-17
Slave Transfer Preparation ........................................... 10-18
Changing SPI Configuration ........................................... 10-20
Switching From Transmit To Receive DMA ..................... 10-21
Switching From Receive to Transmit DMA ..................... 10-22
DMA Error Interrupts .................................................... 10-24
DMA Chaining .............................................................. 10-25
SPI Transfer Formats ................................................................ 10-26
Beginning and Ending an SPI Transfer ................................ 10-28
SPI Word Lengths .................................................................... 10-29
8-Bit Word Lengths ............................................................ 10-30
16-Bit Word Lengths .......................................................... 10-30
32-Bit Word Lengths .......................................................... 10-31
Packing .............................................................................. 10-31
SPI Interrupts ........................................................................... 10-32
SPI Registers ............................................................................ 10-34
Control and Status Registers ................................................ 10-34
SPI Baud Setup Register (SPIBAUD) .............................. 10-34
Use of DSxEN Bits in SPIFLG
for Multiple Slave SPI Systems ..................................... 10-36
SPI Device Select Input Pin ............................................ 10-37
Buffering and Transmit/Receive Registers ............................ 10-37
SPI Transmit Data Buffer Register (TXSPI) ..................... 10-38
SPI Receive Data Buffer Register (RXSPI) ....................... 10-39

ADSP-2126x SHARC Processor Hardware Reference xix
Contents
DMA Registers .................................................................... 10-39
SPI DMA Internal Index Register (IISPI) ........................ 10-39
SPI DMA Address Modifier Register (IMSPI) .................. 10-39
SPI DMA Word Count Register (CSPI) ........................... 10-40
Error Signals and Flags .............................................................. 10-40
Mode Fault Error (MME) .................................................... 10-40
Transmission Error Bit (TUNF) ........................................... 10-41
Reception Error Bit (ROVF) ................................................ 10-42
Transmit Collision Error Bit (TXCOL) ................................ 10-42
Programming Model ................................................................. 10-42
Master Mode Core Transfers ................................................ 10-43
Slave Mode Core Transfers ................................................... 10-44
Master Mode DMA Transfers ............................................... 10-45
Slave Mode DMA Transfers ................................................. 10-47
Chained DMA Transfers ...................................................... 10-48
Stopping Core Transfers ....................................................... 10-49
Stopping DMA Transfers ..................................................... 10-50
Switching from Transmit To Transmit/Receive DMA ............ 10-50
Switching from Receive to Receive/Transmit DMA ............... 10-52
DMA Error Interrupts ......................................................... 10-53
INPUT DATA PORT
Serial Inputs ............................................................................... 11-3

Contents
xx ADSP-2126x SHARC Processor Hardware Reference
Parallel Data Acquisition Port (PDAP) ........................................ 11-6
Masking ................................................................................ 11-8
Packing Unit ......................................................................... 11-8
Packing Mode 11 .............................................................. 11-9
Packing Mode 10 .............................................................. 11-9
Packing Mode 01 ............................................................ 11-10
Packing Mode 00 ............................................................ 11-10
Clocking Edge Selection ...................................................... 11-11
Hold Input ......................................................................... 11-11
PDAP Strobe ...................................................................... 11-13
FIFO Control and Status .......................................................... 11-14
FIFO to Memory Data Transfer ................................................ 11-15
Interrupt-Driven Transfers ................................................. 11-16
Starting an Interrupt-Driven Transfer .............................. 11-16
Interrupt-Driven Transfer Notes .......................................... 11-18
DMA Transfers ................................................................... 11-18
Starting DMA Transfers .................................................. 11-18
DMA Transfer Notes ...................................................... 11-20
DMA Channel Parameter Registers ...................................... 11-22
IDP (DAI) Interrupt Service Routines for DMAs ................. 11-23
Input Data Port Programming Example .................................... 11-24
DIGITAL AUDIO INTERFACE
Structure of the DAI ................................................................... 12-1
DAI System Design .................................................................... 12-2