Analog Devices ADSP-21261 SHARC Application guide

a
ADSP-2126x SHARC®Processor
Hardware Reference
Includes ADSP-21261, ADSP-21262
ADSP-21266, ADSP-21267
Revision 5.1, April 2013
Part Number
82-002002-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information
© 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-
ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
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accurate and reliable. However, no responsibility is assumed by Analog
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third parties which may result from its use. No license is granted by impli-
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VisualDSP++, and EZ-KIT Lite are registered trademarks of Analog
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All other brand and product names are trademarks or service marks of
their respective owners.

ADSP-2126x SHARC Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual ............................................................. xxxi
Intended Audience ...................................................................... xxxi
Manual Contents ....................................................................... xxxii
What’s New in This Manual ...................................................... xxxiv
Technical Support ..................................................................... xxxiv
Supported Processors .................................................................. xxxv
Product Information .................................................................. xxxv
Analog Devices Web Site ..................................................... xxxvi
EngineerZone ...................................................................... xxxvi
Notation Conventions .............................................................. xxxvii
Register Diagram Conventions ................................................ xxxviii
INTRODUCTION
Design Advantages ........................................................................ 1-1
Architectural Overview ................................................................. 1-4

Contents
iv ADSP-2126x SHARC Processor Hardware Reference
Processor Core ........................................................................ 1-5
Processing Elements ............................................................ 1-5
Program Sequence Control ................................................. 1-6
Processor Internal Buses ...................................................... 1-9
Processor Peripherals ............................................................. 1-10
Dual-Ported Internal Memory (SRAM) ............................. 1-10
I/O Processor ................................................................... 1-11
Digital Audio Interface (DAI) ........................................... 1-13
Development Tools ..................................................................... 1-13
Differences From Previous SHARCs ............................................ 1-14
Processor Core Enhancements ............................................... 1-15
Processor Internal Bus Changes ............................................. 1-15
Memory Organization Enhancements .................................... 1-16
Parallel Port Enhancements ................................................... 1-16
I/O Architecture Enhancements ............................................ 1-16
Instruction Set Enhancements ............................................... 1-16
PROCESSING ELEMENTS
Numeric Formats .......................................................................... 2-3
IEEE Single-precision Floating-point Data Format ................... 2-4
Extended-precision Floating-Point Format ............................... 2-6
Short Word Floating-Point Format .......................................... 2-7
Packing for Floating-Point Data .............................................. 2-7
Fixed-Point Formats ................................................................ 2-9

ADSP-2126x SHARC Processor Hardware Reference v
Contents
Setting Computational Modes ..................................................... 2-12
32-Bit Floating-Point Format (Normal Word) ........................ 2-12
40-Bit Floating-Point Format ................................................. 2-14
16-Bit Floating-Point Format (Short Word) ........................... 2-14
32-Bit Fixed-Point Format ..................................................... 2-15
Rounding Mode .................................................................... 2-15
Using Computational Status ........................................................ 2-16
Arithmetic Logic Unit (ALU) ...................................................... 2-17
ALU Operation ..................................................................... 2-17
ALU Saturation ..................................................................... 2-18
ALU Status Flags ................................................................... 2-19
ALU Instruction Summary .................................................... 2-20
Multiply Accumulator (Multiplier) .............................................. 2-23
Multiplier Operation ............................................................. 2-23
Multiplier Result Register (Fixed-Point) ................................. 2-24
Multiplier Status Flags ........................................................... 2-27
Multiplier Instruction Summary ............................................ 2-28
Barrel Shifter (Shifter) ................................................................. 2-30
Shifter Operation .................................................................. 2-31
Shifter Status Flags ................................................................ 2-35
Shifter Instruction Summary .................................................. 2-36
Data Register File ........................................................................ 2-38
Alternate (Secondary) Data Registers ........................................... 2-40
Multifunction Computations ...................................................... 2-41

Contents
vi ADSP-2126x SHARC Processor Hardware Reference
Secondary Processing Element (PEy) ........................................... 2-45
Dual Compute Units Sets ...................................................... 2-47
Dual Register Files ................................................................ 2-49
Dual Alternate Registers ........................................................ 2-50
SIMD and Status Flags .......................................................... 2-50
SIMD (Computational) Operations ....................................... 2-50
PROGRAM SEQUENCER
Instruction Pipeline ...................................................................... 3-4
Instruction Cache ......................................................................... 3-5
Bus Conflicts .......................................................................... 3-5
Block Conflicts ....................................................................... 3-7
Using the Cache ...................................................................... 3-8
Optimizing Cache Usage ......................................................... 3-9
Branches and Sequencing ............................................................ 3-11
Conditional Branches ............................................................ 3-12
Delayed Branches .................................................................. 3-13
Loop and Status Stacks and Sequencing ....................................... 3-16
Conditional Sequencing .............................................................. 3-17
Core Stalls .................................................................................. 3-21
Execution Stalls ..................................................................... 3-23
DAG Stalls ........................................................................... 3-24
Memory Stalls ....................................................................... 3-24
IOP Register Stalls ................................................................ 3-24
DMA Stalls ........................................................................... 3-24

ADSP-2126x SHARC Processor Hardware Reference vii
Contents
Loops and Sequencing ................................................................. 3-25
Restrictions on Ending Loops ................................................ 3-27
Restrictions on Short Loops ................................................... 3-28
Loop Address Stack ............................................................... 3-31
Loop Counter Stack .............................................................. 3-32
Reading From LCNTR in a LOOP .................................... 3-36
SIMD Mode and Sequencing ...................................................... 3-36
Conditional Compute Operations .......................................... 3-38
Conditional Branches and Loops ........................................... 3-38
Conditional Data Moves ........................................................ 3-38
Case #1: Complementary Register Pair Data Move ............. 3-39
Example 1: Register-to-Memory Move – PEx Explicit Register
3-39
Example 2: Register Move – PEy Explicit Register .......... 3-40
Example 3: Register-to-Memory Move – PEx Explicit Register
3-40
Example 4: Register-to-Memory Move – PEy Explicit Register
3-41
Case #2: Uncomplimentary-to-Complementary Register Move 3-42
Example: Register Moves – Uncomplimentary-to-Complementary
3-42
Case #3: Complementary-to-Uncomplimentary Register Move 3-43
Example: Register Moves – Complementary-to-Uncomplimentary
3-43

Contents
viii ADSP-2126x SHARC Processor Hardware Reference
Case #4: External Memory or IOP Memory Space Data Move 3-44
Example: Register-to-Memory Moves – External or IOP Memory
Space Data Move ....................................................... 3-44
Case #5: Uncomplimentary Register Data Move ................ 3-45
Conditional DAG Operations ............................................... 3-45
Timer and Sequencing ................................................................ 3-46
Interrupts and Sequencing .......................................................... 3-48
Delayed Interrupt Processing ................................................. 3-52
Sensing Interrupts ................................................................. 3-53
Masking Interrupts ............................................................... 3-54
Latching Interrupts ............................................................... 3-55
Stacking Status During Interrupts .......................................... 3-56
Nesting Interrupts ................................................................. 3-58
Reusing Interrupts ................................................................ 3-60
Interrupting IDLE ................................................................ 3-61
Summary .................................................................................... 3-61
DATA ADDRESS GENERATORS
Setting DAG Modes ..................................................................... 4-4
Circular Buffering Mode ......................................................... 4-5
Broadcast Loading Mode ......................................................... 4-5
Alternate (Secondary) DAG Registers ...................................... 4-6
Bit-Reverse Addressing Mode .................................................. 4-8
Using DAG Status ........................................................................ 4-9

ADSP-2126x SHARC Processor Hardware Reference ix
Contents
DAG Operations ........................................................................... 4-9
Addressing With DAGs ......................................................... 4-10
Data Addressing Stalls ........................................................... 4-12
Addressing Circular Buffers ................................................... 4-12
Modifying DAG Registers ...................................................... 4-17
Addressing in SISD and SIMD Modes ................................... 4-18
DAGs, Registers, and Memory .................................................... 4-19
DAG Register-to-Bus Alignment ............................................ 4-19
DAG Register Transfer Restrictions ........................................ 4-21
DAG Instruction Summary ......................................................... 4-23
MEMORY
Internal Memory ........................................................................... 5-2
DSP Architecture .................................................................... 5-2
Buses ............................................................................................ 5-3
Internal Address and Data Buses .............................................. 5-4
Internal Data Bus Exchange ..................................................... 5-6
ADSP-2126x Memory Map ......................................................... 5-10
Memory Organization and Word Size .................................... 5-12
Placing 32-Bit Words and 48-Bit Words ............................ 5-13
Mixing 32-Bit Words and 48-Bit Words ............................ 5-14
Restrictions on Mixing 32-Bit Words and 48-Bit Words ..... 5-16
Example: Calculating a Starting Address for 32-Bit Addresses 5-17
48-Bit Word Allocation ..................................................... 5-17
Internal Interrupt Vector Table .............................................. 5-18

Contents
x ADSP-2126x SHARC Processor Hardware Reference
Internal Memory Data Width ................................................ 5-18
Secondary Processor Element (PEy) ....................................... 5-19
Broadcast Register Loads ....................................................... 5-20
Illegal I/O Processor Register Access ...................................... 5-21
Unaligned 64-Bit Memory Access .......................................... 5-21
Using Memory Access Status ....................................................... 5-22
Accessing Memory ...................................................................... 5-22
Access Word Size ................................................................... 5-23
Long Word (64-Bit) Accesses ............................................ 5-23
Instruction and Extended-Precision Normal Word Accesses 5-25
Normal Word (32-Bit) Accesses ........................................ 5-26
Short Word (16-Bit) Accesses ............................................ 5-26
Setting Data Access Modes .................................................... 5-27
SYSCTL Register Control Bits .......................................... 5-27
Mode 1 Register Control Bits ............................................ 5-27
Mode 2 Register Control Bits ............................................ 5-28
SISD, SIMD, and Broadcast Load Modes .............................. 5-28
Single- and Dual-Data Accesses ............................................. 5-28
Instruction Examples ........................................................ 5-29
Shadow Write FIFO ................................................................... 5-29
Internal Memory Access Listings ................................................. 5-30
Short Word Addressing of Single-Data in SISD Mode ............ 5-32
Short Word Addressing of Dual-Data in SISD Mode .............. 5-34
Short Word Addressing of Single-Data in SIMD Mode .......... 5-36