Analog Devices AD7194 User manual

8-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
AD7194
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
Fast settling filter option
8 differential/16 pseudo differential input channels
RMS noise: 11 nV at 4.7 Hz (gain = 128)
15.5 noise-free bits at 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 4.65 mA
Temperature range: −40°C to +105°C
Package: 32-lead LFCSP
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
PLC/DCS analog input modules
Data acquisition
Strain gage transducers
Pressure measurement
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7194 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
The device can be configured to have eight differential inputs or
sixteen pseudo differential inputs. The on-chip 4.92 MHz clock
can be used as the clock source to the ADC or, alternatively, an
external clock or crystal can be used. The output data rate from
the part can be varied from 4.7 Hz to 4.8 kHz.
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. For applications that
require all conversions to be settled, the AD7194 includes zero
latency.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.65 mA, and it is housed in a 32-lead
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
DVDD DGND REFIN1(+) REFIN1(–)
AIN1/P3
AIN2/P2
A
IN3/P1/REFIN2(+)
A
IN4/P0/REFIN2(–)
AINCOM
AD7194
SERIAL
INTERFACE
AND
CONTROL
LOGIC
REFERENCE
DETECT
TEMP
SENSOR
DOUT/RDY
DIN
SCLK
CS
MCLK1 MCLK2
CLOCK
CIRCUITRY
AVDD AGND
AIN5
AIN16
Σ-Δ
ADC
PGA
MUX
0
8566-001
AVDD
AGND
Figure 1.
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AD7194
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
RMS Noise and Resolution............................................................ 15
Sinc4Chop Disabled................................................................... 15
Sinc3Chop Disabled................................................................... 16
Fast Settling ................................................................................. 17
On-Chip Registers .......................................................................... 18
Communications Register......................................................... 19
Status Register............................................................................. 20
Mode Register ............................................................................. 21
Configuration Register .............................................................. 24
Data Register ............................................................................... 27
ID Register................................................................................... 27
GPOCON Register..................................................................... 27
Offset Register............................................................................. 28
Full-Scale Register ...................................................................... 28
ADC Circuit Information.............................................................. 29
Overview...................................................................................... 29
Analog Input Channel ............................................................... 30
Programmable Gain Array (PGA)........................................... 30
Reference ..................................................................................... 30
Reference Detect......................................................................... 31
Bipolar/Unipolar Configuration .............................................. 31
Data Output Coding .................................................................. 31
Burnout Currents ....................................................................... 31
Digital Interface.......................................................................... 32
Reset ............................................................................................. 36
System Synchronization ............................................................ 36
Enable Parity ............................................................................... 36
Clock ............................................................................................ 36
Temperature Sensor ................................................................... 36
Logic Outputs ............................................................................. 37
Calibration................................................................................... 37
Digital Filter .................................................................................... 39
Sinc4Filter (Chop Disabled) ..................................................... 39
Sinc3Filter (Chop Disabled) ..................................................... 41
Chop Enabled (Sinc4Filter) ...................................................... 43
Chop Enabled (Sinc3Filter) ...................................................... 45
Fast Settling Mode (Sinc4Filter)............................................... 46
Fast Settling Mode (Sinc3Filter)............................................... 48
Fast Settling Mode (Chop Enabled)......................................... 50
Summary of Filter Options ....................................................... 51
Grounding and Layout .................................................................. 52
Applications Information .............................................................. 53
Flowmeter.................................................................................... 53
Outline Dimensions....................................................................... 54
Ordering Guide .......................................................................... 54
REVISION HISTORY
10/09—Revision 0: Initial Version
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AD7194
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SPECIFICATIONS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AVDD, REFINx(−) = AGND,
MCLK = 4.92 MHz, TA= TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments1
ADC
Output Data Rate 4.7 4800 Hz Chop disabled
1.17 1200 Hz Chop enabled, sinc4filter
1.56 1600 Hz Chop enabled, sinc3filter
No Missing Codes224 Bits FS[9:0]3> 1, sinc4filter
24 Bits
FS[9:0]3> 4, sinc3filter
Resolution See the RMS Noise and Resolution section
RMS Noise and Output
Data Rates
See the RMS Noise and Resolution section
Integral Nonlinearity
Gain = 12±2 ±10 ppm of FSR AVDD = 5 V
±2 ±15 ppm of FSR AVDD = 3 V
Gain > 1 ±5 ±30 ppm of FSR AVDD = 5 V
±15 ±30 ppm of FSR AVDD = 3 V
Offset Error4, 5±150/gain µV Chop disabled
±1 µV Chop enabled, AVDD = 5 V
±0.5 µV Chop enabled, AVDD = 3 V
Offset Error Drift vs.
Temperature
±150/gain nV/°C Gain = 1 to 16; chop disabled
±5 nV/°C Gain = 32 to 128; chop disabled
±5 nV/°C Chop enabled
Gain Error4±0.001 % AVDD = 5 V, gain = 1, TA= 25°C (factory
calibration conditions)
−0.4 % Gain = 128, before full-scale calibration
(see Table 27)
±0.003 % Gain > 1, after internal full-scale
calibration, AVDD ≥ 4.75 V
±0.005 % Gain > 1, after internal full-scale
calibration, AVDD < 4.75 V
Gain Drift vs.
Temperature
±1 ppm/°C
Power Supply Rejection 90 dB Gain = 1, VIN = 1 V
95 110 dB Gain > 1, VIN = 1 V/gain
Common-Mode Rejection
@ DC 110 dB Gain = 1, VIN = 1 V
@ DC 105 120 dB Gain > 1, VIN = 1 V/gain
@ 50 Hz, 60 Hz2120 dB 10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
@ 50 Hz2120 dB 50 Hz output data rate, 50 Hz ± 1 Hz
@ 60 Hz2120 dB 60 Hz output data rate, 60 Hz ± 1 Hz
@ 50 Hz2115 dB
Fast settling, FS[9:0]3= 6, average by 16,
50 Hz ± 1 Hz
@ 60 Hz2115 dB
Fast settling, FS[9:0]3= 5, average by 16,
60 Hz ± 1 Hz
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Parameter Min Typ Max Unit Test Conditions/Comments1
Normal Mode Rejection2
Sinc4Filter
Internal Clock
@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
74 dB 50 Hz output data rate, REJ606 = 1,
50 Hz ± 1 Hz, 60 Hz ± 1 Hz
@ 50 Hz 96 dB 50 Hz output data rate, 50 Hz ± 1 Hz
@ 60 Hz 97 dB 60 Hz output data rate, 60 Hz ± 1 Hz
External Clock
@ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
82 dB
50 Hz output data rate, REJ606= 1,
50 Hz ± 1 Hz, 60 Hz ± 1 Hz
@ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz
@ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz
Sinc3Filter
Internal Clock
@ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
60 dB 50 Hz output data rate, REJ606= 1,
50 Hz ± 1 Hz, 60 Hz ± 1 Hz
@ 50 Hz 70 dB 50 Hz output data rate, 50 Hz ± 1 Hz
@ 60 Hz 70 dB 60 Hz output data rate, 60 Hz ± 1 Hz
External Clock
@ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
@ 50 Hz 67 dB 50 Hz output data rate, REJ606= 1,
50 Hz ± 1 Hz, 60 Hz ± 1 Hz
@ 50 Hz 95 dB 50 Hz output data rate, 50 Hz ± 1 Hz
@ 60 Hz 95 dB 60 Hz output data rate, 60 Hz ± 1 Hz
Fast Settling
Internal Clock
@ 50 Hz 26 dB FS[9:0]3= 6, average by 16, 50 Hz ± 0.5 Hz
@ 60 Hz 26 dB FS[9:0]3= 5, average by 16, 60 Hz ± 0.5 Hz
External Clock
@ 50 Hz 40 dB FS[9:0]3= 6, average by 16, 50 Hz ± 0.5 Hz
@ 60 Hz 40 dB FS[9:0]3= 5, average by 16, 60 Hz ± 0.5 Hz
ANALOG INPUTS
Differential Input
Voltage Ranges
±VREF/gain V VREF = REFINx(+) − REFINx(−),
gain = 1 to 128
−(AVDD − 1.25 V)/gain +(AVDD − 1.25 V)/gain V Gain > 1
Absolute AIN Voltage
Limits2
Unbuffered Mode AGND − 0.05 AVDD + 0.05 V
Buffered Mode AGND + 0.25 AVDD − 0.25 V
Analog Input Current
Buffered Mode
Input Current2−2 +2 nA Gain = 1
−3 +3 nA Gain > 1
Input Current Drift ±5 pA/°C
Unbuffered Mode
Input Current ±3.5 µA/V Gain = 1, input current varies with input
voltage
±1 µA/V Gain > 1
Input Current Drift ±0.05 nA/V/°C External clock
±1.6 nA/V/°C Internal clock
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AD7194
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Parameter Min Typ Max Unit Test Conditions/Comments1
REFERENCE INPUT
REFIN Voltage 1 AVDD V REFIN = REFINx(+) − REFINx(−), the
differential input must be limited to
±(AVDD − 1.25 V)/gain when gain > 1
Absolute REFIN Voltage
Limits2
AGND − 0.05 AVDD + 0.05 V
Average Reference Input
Current
4.5 µA/V
Average Reference Input
Current Drift
±0.03 nA/V/°C External clock
±1.3 nA/V/°C Internal clock
Normal Mode Rejection2Same as for
analog inputs
Common-Mode
Rejection
100 dB
Reference Detect Levels 0.3 0.6 V
TEMPERATURE SENSOR
Accuracy ±2 °C Applies after user calibration at 25°C
Sensitivity 2815 Codes/°C Bipolar mode
BURNOUT CURRENTS
AIN Current 500 nA Analog inputs must be buffered and chop
disabled
DIGITAL OUTPUTS (P0 to P3)
Output High Voltage, VOH AVDD − 0.6 V AVDD = 3 V, ISOURCE = 100 A
4 V AVDD = 5 V, ISOURCE = 200 A
Output Low Voltage, VOL 0.4 V AVDD = 3 V, ISINK = 100 A
0.4 V AVDD = 5 V, ISINK = 800 A
Floating-State Leakage
Current2
−100 +100 nA
Floating-State Output
Capacitance
10 pF
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency 4.72 5.12 MHz
Duty Cycle 50:50 %
External Clock/Crystal
Frequency 2.4576 4.9152 5.12 MHz
Input Low Voltage, VINL 0.8 V DVDD = 5 V
0.4 V DVDD = 3 V
Input High Voltage, VINH 2.5 V DVDD = 3 V
3.5 V DVDD = 5 V
Input Current −10 +10 µA
LOGIC INPUTS
Input High Voltage, VINH22 V
Input Low Voltage, VINL20.8 V
Hysteresis20.1 0.25 V
Input Currents −10 +10 µA
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH2DVDD − 0.6 V DVDD = 3 V, ISOURCE = 100 µA
4 V DVDD = 5 V, ISOURCE = 200 µA
Output Low Voltage, VOL20.4 V DVDD = 3 V, ISINK = 100 µA
0.4 V DVDD = 5 V, ISINK = 1.6 mA
Floating-State Leakage
Current
−10 +10 µA
Floating-State Output
Capacitance
10 pF
Data Output Coding Offset binary
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Parameter Min Typ Max Unit Test Conditions/Comments1
SYSTEM CALIBRATION2
Full-Scale Calibration Limit 1.05 × FS V
Zero-Scale Calibration
Limit
−1.05 × FS V
Input Span 0.8 × FS 2.1 × FS V
POWER REQUIREMENTS7
Power Supply Voltage
AVDD − AGND 3 5.25 V
DVDD − DGND 2.7 5.25 V
Power Supply Currents
AIDD Current 0.85 1.1 mA Gain = 1, buffer off
1 1.35 mA Gain = 1, buffer on
2.8 3.6 mA Gain = 8, buffer off
3.2 3.85 mA Gain = 8, buffer on
3.8 4.7 mA Gain = 16 to 128, buffer off
4.3 5.3 mA Gain = 16 to 128, buffer on
DIDD Current 0.35 0.4 mA DVDD = 3 V
0.5 0.6 mA DVDD = 5 V
1.5 mA External crystal used
IDD 3 µA Power-down mode
1Temperature range: −40°C to +105°C.
2Specification is not production tested, but is supported by characterization data at initial product release.
3FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system
full-scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5The analog inputs are configured for differential mode.
6REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous
50 Hz/60 Hz rejection.
7Digital inputs equal to DVDD or DGND.
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AD7194
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TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter Limit at TMIN, TMAX (B Version) Unit Conditions/Comments1, 2
READ AND WRITE OPERATIONS
t3100 ns min SCLK high pulse width
t4100 ns min SCLK low pulse width
READ OPERATION
t10 ns min CS falling edge to DOUT/RDY active time
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t230 ns min SCLK active edge to data valid delay4
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t55, 610 ns min Bus relinquish time after CS inactive edge
80 ns max
t60 ns min SCLK inactive edge to CS inactive edge
t710 ns min SCLK inactive edge to DOUT/RDY high
WRITE OPERATION
t80 ns min CS falling edge to SCLK active edge setup time4
t930 ns min Data valid to SCLK edge setup time
t10 25 ns min Data valid to SCLK edge hold time
t11 0 ns min CS rising edge to SCLK edge hold time
1Sample tested during initial release to ensure compliance. All input signals are specified with tR= tF= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2See Figure 3 and Figure 4.
3These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4The SCLK active edge is the falling edge of SCLK.
5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
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AD7194
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Circuit and Timing Diagrams
I
SINK
(1.6mA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
I
SOURCE
(200µA WITH DV
DD
= 5V,
100µA WITH DV
DD
= 3V)
1.6V
TO
OUTPUT
PIN 50pF
08566-002
Figure 2. Load Circuit for Timing Characterization
t
2
t
3
t
4
t
1
t
6
t
5
t
7
CS (I)
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUT
MSB LSB
08566-003
Figure 3. Read Cycle Timing Diagram
I = INPUT, O = OUTPUT
CS (I)
S
CLK (I)
DIN (I) MSB LSB
t8
t9t10
t11
08566-004
Figure 4. Write Cycle Timing Diagram
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AD7194
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ABSOLUTE MAXIMUM RATINGS
TA= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND −0.3 V to +6.5 V
DVDD to AGND −0.3 V to +6.5 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V
AINx/Digital Input Current 10 mA
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering Reflow 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
32-Lead LFCSP 32.5 32.71 °C/W
ESD CAUTION
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AD7194
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
08566-005
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO AGND.
24 DV
DD
23 AV
DD
22 DGND
21 AGND
20 AIN16
19 AIN15
18 REFIN1(–)
17 REFIN1(+)
1
2
3
4
5
6
7
8
AIN1/P3
AIN2/P2
AIN3/P1/REFIN2(+)
AIN4/P0/REFIN2(–)
AINCOM
AGND
AIN5
AIN6
9
10
11
12 13 14 15 16
AIN7 AIN8 AIN9
AIN10
AIN11
AIN12 AIN13 AIN14
32 31 30 29 28 27 26 25
CS SCLK MCLK2 MCLK1 DIN DOUT/RD
Y
NC SYNC
TOP VIEW
(Not to Scale)
AD7194
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 AIN1/P3 Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set
to 1, the pin functions as a general-purpose output bit referenced between AVDD and AGND.
2 AIN2/P2 Analog Input/Digital Output Pin. This pin can function as an analog input pin. When the GP32EN bit is set
to 1, the pin functions as a general-purpose output bit referenced between AVDD and AGND.
3 AIN3/P1/REFIN2(+)
Analog Input/Digital Output Pin/Positive Reference Input. This pin functions as an analog input pin. When
the GP10EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AVDD and
AGND. When the REFSEL bit in the configuration register is set to 1, this pin functions as REFIN2(+). An
external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between
AVDD and AGND + 1 V.
4 AIN4/P0/REFIN2(−)
Analog Input/Digital Output Pin/Positive Reference Input. This pin functions as an analog input pin. When
the GP10EN bit is set to 1, the pin functions as a general-purpose output bit referenced between AVDD and
AGND. When the REFSEL bit in the configuration register is set to 1, this pin functions as REFIN2(−). An
external reference can be applied between REFIN2(+) and REFIN2(−). This reference input can lie anywhere
between AGND and AVDD − 1 V.
5 AINCOM Analog Input AIN1 to Analog Input AIN16 are referenced to this input when the bit pseudo is set to 1.
6 AGND Analog Ground Reference Point.
7 AIN5 Analog Input Pin.
8 AIN6 Analog Input Pin.
9 AIN7 Analog Input Pin.
10 AIN8 Analog Input Pin.
11 AIN9 Analog Input Pin.
12 AIN10 Analog Input Pin.
13 AIN11 Analog Input Pin.
14 AIN12 Analog Input Pin.
15 AIN13 Analog Input Pin.
16 AIN14 Analog Input Pin.
17 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).
REFIN1(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) −
REFIN1(−)), is AVDD, but the part functions with a reference from 1 V to AVDD.
18 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V.
19 AIN15 Analog Input Pin.
20 AIN16 Analog Input Pin.
21 AGND Analog Ground Reference Point.
22 DGND Digital Ground Reference Point.
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AD7194
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Pin No. Mnemonic Description
23 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V
with AVDD at 5 V or vice versa.
24 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V
with DVDD at 5 V or vice versa.
25 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a
number of AD7194 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor
internally to DVDD.
26 NC This pin should be connected to GND for correct operation.
27 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data
output pin to access the output shift register of the ADC. The output shift register can contain data from
any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low
to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high
before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor,
indicating that valid data is available. With an external serial clock, the data can be read using the
DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the
SCLK falling edge and is valid on the SCLK rising edge.
28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.
29 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between
MCLK1 and MCLK2.
30 MCLK2 Master Clock Signal for the Device. The AD7194 has an internal 4.92 MHz clock. This internal clock can be
made available on the MCLK2 pin. The clock for the AD7194 can also be provided externally in the form of
a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2
pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.
31 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a nonconti-
nuous clock with the information transmitted to or from the ADC in smaller batches of data.
32 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the
ADC in systems with more than one device on the serial bus or as a frame synchronization signal in
communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode
with SCLK, DIN, and DOUT used to interface with the device.
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AD7194
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TYPICAL PERFORMANCE CHARACTERISTICS
0 200 400 600 800 1000
SAMPLE
CODE
8,387,934
8,387,936
8,387,938
8,387,940
8,387,942
8,387,944
8,387,946
8,387,948
8,387,950
8,387,952
08566-006
0
10
20
30
40
50
8,388,830 8,388,860 8,388,890 8,388,920
CODE
OCCURRENCE
08566-009
Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz,
Gain = 128, Chop Disabled, Sinc4Filter)
Figure 9. Noise Distribution Histogram (VREF = AVDD = 5 V,
Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4Filter)
0
50
100
150
200
8,387,9368,387,9388,387,9408,387,9428,387,9448,387,9468,387,9488,387,950
CODE
OCCURRENCE
0
8566-007
8,388,864
8,388,866
8,388,868
8,388,870
8,388,872
8,388,874
8,388,876
8,388,878
8,388,880
0 200 400 600 800 1000
SAMPLE
CODE
08566-010
Figure 7. Noise Distribution Histogram (VREF = AVDD = 5 V,
Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4Filter)
Figure 10. Noise (VREF = AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6,
Average by 16), Gain = 1, Chop Disabled, Sinc4Filter)
0
50
100
150
200
8,388,864 8,388,868 8,388,872 8,388,876 8,388,880
CODE
OCCURRENCE
08566-011
8,388,830
8,388,840
8,388,850
8,388,860
8,388,870
8,388,880
8,388,890
8,388,900
8,388,910
8,388,920
0 200 400 600 800 1000
SAMPLE
CODE
08566-008
Figure 11. Noise Distribution Histogram (VREF = AVDD = 5 V, Output Data Rate =
42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc4Filter)
Figure 8. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz,
Gain = 1, Chop Disabled, Sinc4Filter)
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AD7194
Rev. 0 | Page 13 of 56
5
–2
–1
0
1
2
3
4
–4–3–2–101234
INL (ppm of FSR)
V
IN
(V)
08566-012
Figure 12. INL (Gain = 1)
20
–20
–15
–10
–5
0
5
10
15
–0.03 –0.02 –0.01 0 0.01 0.02 0.03
INL (ppm of FSR)
V
IN
(V)
08566-013
Figure 13. INL (Gain = 128)
170
168
166
164
162
160
156
158
154
–60 –40 –20 0 20 40 60 80 100 120
OFFSET (µV)
TEMPERATURE (°C)
08566-014
Figure 14. Offset vs. Temperature (Gain = 1, Chop Disabled)
08566-067
0
0.1
0.2
0.3
0.4
0.5
0.6
–60 –40 –20 0 20 40 60 80 100 120
TEMPERAUTRE (°C)
OFFSET ERROR (μV)
Figure 15. Offset vs. Temperature (Gain = 128, Chop Disabled)
–60 –40 –20 0 20 40 60 80 100 120
GAIN
TEMPERATURE (°C)
0.999988
0.999990
0.999992
0.999994
0.999996
0.999998
1.000000
1.000002
1.000004
1.000006
1.000008
08566-016
Figure 16. Gain vs. Temperature (Gain = 1)
–60 –40 –20 0 20 40 60 80 100 120
GAIN
TEMPERATURE (°C)
127.988
127.990
127.992
127.994
127.996
127.998
128.000
128.002
128.004
08566-017
Figure 17. Gain vs. Temperature (Gain = 128)
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AD7194
Rev. 0 | Page 14 of 56
08566-068
16
17
18
19
20
22
21
23
1 10 100 1k
OUTPUT DATA RATE (Hz)
NOISE FREE RESOLUTION (Bits)
GAIN = 1
GAIN = 8
GAIN = 16
GAIN = 32
GAIN = 64
GAIN = 128
14
16
18
20
22
24
1 10 100 1k 10k
OUTPUT DATA RATE (Hz)
NOISE FREE RESOLUTION (Bits)
08566-069
GAIN = 1
GAIN = 8
GAIN = 16
GAIN = 32
GAIN = 64
GAIN = 128
Figure 20. Noise-Free Resolution in Fast Settling Mode (VREF = 5 V,
Averaging by 16, Sinc4Filter, Chop Disabled)
Figure 18. Noise-Free Resolution (Sinc4Filter, Chop Disabled, VREF = 5 V)
10
12
14
16
18
20
22
24
1 10 100 1k 10k
OUTPUT DATA RATE (Hz)
NOISE FREE RESOLUTION (Bits)
08566-070
GAIN = 1
GAIN = 8
GAIN = 16
GAIN = 32
GAIN = 64
GAIN = 128
Figure 19. Noise-Free Resolution (Sinc3Filter, Chop Disabled, VREF = 5 V)
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AD7194
Rev. 0 | Page 15 of 56
RMS NOISE AND RESOLUTION
The following tables show the rms noise, peak-to-peak noise,
effective resolution, and noise-free (peak-to-peak) resolution of
the AD7194 for various output data rates and gain settings with
chop disabled for the sinc4and sinc3filters and for fast settling
mode. The numbers given are for the bipolar input range with
an external 5 V reference. These numbers are typical and are
generated with a differential input voltage of 0 V when the ADC
is continuously converting on a single channel. It is important
to note that the effective resolution is calculated using the rms
noise, whereas the peak-to-peak resolution is calculated based
on peak-to-peak noise. The peak-to-peak resolution represents
the resolution for which there is no code flicker. With chop
enabled, the resolution improves by 0.5 bits.
SINC4CHOP DISABLED
Table 6. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word
(Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of
1 8 16 32 64 128
1023 4.7 852.5 370 57 35 18 13 11
640 7.5 533 440 73 41 24 17 13
480 10 400 470 83 45 28 18 16
96 50 80 1100 150 85 52 38 34
80 60 66.7 1200 170 94 56 42 38
32 150 26.7 1800 260 150 86 65 59
16 300 13.3 2500 360 210 130 95 83
5 960 4.17 4500 640 370 230 170 150
2 2400 1.67 7500 1100 600 380 280 240
1 4800 0.83 26,000 3400 1800 940 550 390
Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word
(Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of
1 8 16 32 64 128
1023 4.7 852.5 2200 340 200 120 84 70
640 7.5 533 2700 430 260 150 100 85
480 10 400 3000 480 300 170 120 100
96 50 80 6600 950 540 350 250 210
80 60 66.7 7200 1000 610 370 270 220
32 150 26.7 11,000 1600 970 580 430 370
16 300 13.3 17,000 2400 1400 840 620 530
5 960 4.17 35,000 4800 2500 1500 1100 1000
2 2400 1.67 56,000 7500 4200 2900 1800 1700
1 4800 0.83 175,000 23,000 12,000 7100 3600 2600
Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word
(Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of1
1 8 16 32 64 128
1023 4.7 852.5 24 (22.1) 24 (21.8) 24 (21.6) 24 (21.3) 23.5 (20.8) 22.8 (20.1)
640 7.5 533 24 (21.8) 24 (21.5) 23.9 (21.2) 23.6 (21) 23.1 (20.6) 22.5 (19.8)
480 10 400 24 (21.7) 24 (21.3) 23.7 (21) 23.4 (20.8) 23 (20.3) 22.2 (19.6)
96 50 80 23.1 (20.5) 23 (20.3) 22.8 (20.1) 22.5 (19.8) 22 (19.3) 21.1 (18.5)
80 60 66.7 23 (20.4) 22.9 (20.3) 22.7 (20) 22.4 (19.7) 21.8 (19.1) 21 (18.4)
32 150 26.7 22.4 (19.8) 22.3 (19.6) 22 (19.3) 21.8 (19) 21.2 (18.5) 20.3 (17.7)
16 300 13.3 21.9 (19.2) 21.8 (19) 21.5 (18.8) 21.2 (18.5) 20.7 (17.9) 19.8 (17.2)
5 960 4.17 21.1 (18.4) 21 (18) 20.7 (17.9) 20.4 (17.7) 19.8 (17.1) 19 (16.3)
2 2400 1.67 20.4 (17.6) 20.3 (17.3) 20 (17.2) 19.6 (16.7) 19.1 (16.4) 18.3 (15.5)
1 4800 0.83 18.6 (15.8) 18.5 (15.7) 18.4 (15.7) 18.3 (15.4) 18.1 (15.4) 17.6 (14.9)
1The output peak-to-peak (p-p) resolution is listed in parentheses.
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AD7194
Rev. 0 | Page 16 of 56
SINC3CHOP DISABLED
Table 9. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of
1 8 16 32 64 128
1023 4.7 639.4 380 58 35 20 13 11
640 7.5 400 450 73 41 25 17 14
480 10 300 490 90 47 28 19 16
96 50 60 1100 160 92 54 40 36
80 60 50 1200 170 99 59 43 39
32 150 20 1900 280 160 91 72 63
16 300 10 2700 380 210 130 97 87
5 960 3.13 6400 870 490 280 200 170
2 2400 1.25 115,000 14,000 7000 3600 1800 950
1 4800 0.625 860,000 110,000 54,000 28,000 14,000 7000
Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word (Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of
1 8 16 32 64 128
1023 4.7 639.4 2300 350 220 130 84 70
640 7.5 400 2700 450 270 160 110 88
480 10 300 3100 520 310 180 120 100
96 50 60 7200 990 560 370 260 230
80 60 50 7800 1100 630 390 270 250
32 150 20 13,000 1800 1000 580 480 400
16 300 10 19,000 2500 1400 860 640 560
5 960 3.13 410,000 5700 3200 1800 1300 1100
2 2400 1.25 730,000 93,000 47,000 24,000 12,000 6100
1 4800 0.625 5,700,000 730,000 360,000 180,000 93,000 45,000
Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word (Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of1
1 8 16 32 64 128
1023 4.7 639.4 24 (22.1) 24 (21.8) 24 (21.4) 23.9 (21.2) 23.5 (20.8) 22.8 (20.1)
640 7.5 400 24 (21.8) 24 (21.4) 23.9 (21.1) 23.6 (20.9) 23.1 (20.4) 22.4 (19.8)
480 10 300 24 (21.6) 23.8 (21.2) 23.7 (20.9) 23.4 (20.7) 23 (20.3) 22.2 (19.6)
96 50 60 23.1 (20.4) 22.9 (20.3) 22.7 (20.1) 22.5 (19.7) 21.9 (19.2) 21 (18.4)
80 60 50 23 (20.3) 22.8 (20.1) 22.6 (19.9) 22.3 (19.6) 21.8 (19.1) 20.9 (18.3)
32 150 20 22.3 (19.6) 22.1 (19.4) 21.9 (19.3) 21.7 (19) 21 (18.3) 20.2 (17.6)
16 300 10 21.8 (19) 21.6 (18.9) 21.56 (18.8) 21.2 (18.5) 20.6 (17.9) 19.8 (17.1)
5 960 3.13 20.6 (17.9) 20.5 (17.7) 20.3 (17.6) 20.1 (17.4) 19.6 (16.9) 18.8 (16.1)
2 2400 1.25 16.5 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.7) 16.4 (13.6)
1 4800 0.625 13.5 (10.8) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7) 13.5 (10.7)
1The output peak-to-peak (p-p) resolution is listed in parentheses.
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AD7194
Rev. 0 | Page 17 of 56
FAST SETTLING
Table 12. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word
(Decimal) Average
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of
1 8 16 32 64 128
96 16 2.63 380 410 87 52 33 15 12
30 16 8.4 118.75 700 140 71 43 30 21
6 16 42.10 23.75 1500 270 150 82 56 47
5 16 50.53 19.79 1600 280 160 88 61 52
2 16 126.32 7.92 2700 380 210 130 94 85
1 16 252.63 3.96 3700 540 300 190 140 120
Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate
Filter Word
(Decimal) Average
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of
1 8 16 32 64 128
96 16 2.63 380 2500 450 260 180 100 70
30 16 8.4 118.75 4200 900 470 280 190 130
6 16 42.10 23.75 10,000 1800 950 540 360 300
5 16 50.53 19.79 11,000 1900 1000 580 390 330
2 16 126.32 7.92 16,000 2800 1500 850 580 510
1 16 252.63 3.96 23,000 4500 2000 1200 850 740
Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate
Filter Word
(Decimal) Average
Output Data
Rate (Hz)
Settling
Time (ms)
Gain of1
1 8 16 32 64 128
96 16 2.63 380 24 (21.9) 23.8 (21.4) 23.5 (21.2) 23.2 (20.7) 23.3 (20.6) 22.6 (20.1)
30 16 8.4 118.75 23.8 (21.2) 23.1 (20.4) 23.1 (20.3) 22.8 (20.1) 22.3 (19.6) 21.8 (19.2)
6 16 42.10 23.75 22.7 (19.9) 22.1 (19.4) 22 (19.3) 21.9 (19.1) 21.4 (18.7) 20.7 (18)
5 16 50.53 19.79 22.6 (19.8) 22.1 (19.3) 21.9 (19.3) 21.8 (19) 21.3 (18.6) 20.5 (17.9)
2 16 126.32 7.92 21.8 (19.3) 21.6 (18.8) 21.5 (18.7) 21.2 (18.5) 20.7 (18) 19.8 (17.2)
1 16 252.63 3.96 21.4 (18.7) 21.1 (18.1) 21 (18.3) 20.6 (18) 20.1 (17.5) 19.3 (16.7)
1The output peak-to-peak (p-p) resolution is listed in parentheses.
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AD7194
Rev. 0 | Page 18 of 56
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set,
implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.
Table 15. Register Summary
Register Addr. Dir. Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Communications 00 W 00 0 R/WRegister address CREAD 0 0
Status 00 R 80
RDY ERR NOREF Parity CHD3 CHD2 CHD1 CHD0
Mode 01 R/W 080060 Mode select DAT_STA CLK1 CLK0 AVG1 AVG0
SINC3 0 ENPAR CLK_DIV Single REJ60 FS9 FS8
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)
Configuration 02 R/W 000117 Chop (MSB) 0 0 REFSEL 0 Pseudo 0 TEMP
CH7( CH6 CH5 CH4 CH3 CH2 CH1 CH0
Burn REFDET 0 BUF
U/BG2 G1 G0 (LSB)
Data 03 R 000000 D23 (MSB) D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
ID 04 R X3 X X X X 0 0 1 1
GPOCON 05 R/W 00 0 0 GP32EN GP10EN P3DAT P2DAT P1DAT P0DAT
Offset 06 R/W 800000 OF23 (MSB) OF22 OF21 OF20 OF19 OF18 OF17 OF16
OF15 OF14 OF13 OF12 OF11 OF10 OF9 OF8
OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 (LSB)
Full Scale 07 R/W 5XXXX0 FS23 (MSB) FS22 FS21 FS20 FS19 FS18 FS17 FS16
FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 (LSB)
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AD7194
Rev. 0 | Page 19 of 56
COMMUNICATIONS REGISTER
RS2, RS1, RS0 = 000
The communications register is an 8-bit write-only register. All
communications to the part must start with a write operation to
the communications register. The data written to the communi-
cations register determine whether the next operation is a read
or write operation and in which register this operation occurs. For
read or write operations, when the subsequent read or write oper-
ation to the selected register is complete, the interface returns to
where it expects a write operation to the communications register.
This is the default state of the interface and, on power-up or after
a reset, the ADC is in this default state waiting for a write
operation to the communications register. In situations where the
interface sequence is lost, a write operation of at least 40 serial
clock cycles with DIN high returns the ADC to this default state
by resetting the entire part. Table 16 outlines the bit designations
for the communications register. CR0 through CR7 indicate the
bit location, CR denoting that the bits are in the communications
register. CR7 denotes the first bit of the data stream. The number
in parentheses indicates the power-on/reset default status of
that bit.
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0)
Table 16. Communications Register (CR) Bit Designations
Bit Location Bit Name Description
CR7 WEN Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is
the first bit written, the part does not clock onto subsequent bits in the register; rather, it stays at this bit
location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to
the communications register. Idling the DIN pin high between data transfers minimizes the effects of
spurious SCLK pulses on the serial interface.
CR6 R/W0 in this bit location indicates that the next operation is a write to a specified register.
1 in this bit position indicates that the next operation is a read from the designated register.
CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during
the serial interface communication (see Table 17).
CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read; that is, the contents of the data
register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin
goes low to indicate that a conversion is complete. The communications register does not have to be
written to for subsequent data reads. To enable continuous read, Instruction 01011100 must be written to
the communications register. To disable continuous read, Instruction 01011000 must be written to the
communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors
activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a
reset occurs if 40 consecutive 1s occur on DIN; therefore, hold DIN low until an instruction is written to
the device.
CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation.
Table 17. Register Selection
RS2 RS1 RS0 Register Register Size
0 0 0 Communications register during a write operation 8 bits
0 0 0 Status register during a read operation 8 bits
0 0 1 Mode register 24 bits
0 1 0 Configuration register 24 bits
0 1 1 Data register/data register plus status information 24 bits/32 bits
1 0 0 ID register 8 bits
1 0 1 GPOCON register 8 bits
1 1 0 Offset register 24 bits
1 1 1 Full-scale register 24 bits
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AD7194
Rev. 0 | Page 20 of 56
STATUS REGISTER
RS2, RS1, RS0 = 000; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the
ADC status register, the user must write to the communications
register, select the next operation to be a read operation, and
load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 18 outlines the bit
designations for the status register. SR0 through SR7 indicate the
bit locations, SR denoting that the bits are in the status register.
SR7 denotes the first bit of the data stream. The number in paren-
theses indicates the power-on/reset default status of that bit.
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
RDY(1) ERR(0) NOREF(0) Parity(0) CHD3(0) CHD2(0) CHD1(0) CHD0(0)
Table 18. Status Register (SR) Bit Designations
Bit Location Bit Name Description
SR7 RDY Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set
automatically after the ADC data register is read, or a period of time before the data register is updated,
with a new conversion result to indicate to the user that the conversion data should not be read. It is
also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end
of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the
status register for monitoring the ADC for conversion data.
SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the
result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange,
underrange, or the absence of a reference voltage. This bit is cleared when the result written to the data
register returns to within the allowed analog input range. The ERR bit is also set during calibrations if
the reference source is invalid or if the applied analog input voltages are outside range during system
calibrations.
SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a
voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is
cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled
by setting the REFDET bit in the configuration register to 1.
SR4 Parity Parity check of the data register. If the ENPAR bit in the mode register is set, the parity bit is set if there is
an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data
register. The DAT_STA bit in the mode register should be set when the parity check is used. When the
DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data
register read.
SR3 to SR0 CHD3 to CHD0 These bits indicate which channel corresponds to the data register contents. They do not indicate
which channel is presently being converted, but indicate which channel was selected when the
conversion contained in the data register was generated.
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