Atmel ATSTK94 Operation instructions

1
Testing the ATSTK94
To program any design onto the Starter Kit, first of all you need to program the Config-
urator (AT17XX) with a bitstream file, that in turn downloads the configuration data to
the AT94K Field Programmable System Level Integrated Circuit (FPSLIC™)device
during power up. You are not programming the FPSLIC directly since FPSLIC devices
are SRAM-based (at power down you loose the data).
Setting up the Example Files
In this tutorial all paths are given assuming a default install of c:\SystemDesigner.If
you have installed System Designer™in another drive or directory, remember to
change the path to your actual System Designer directory.
Throughout the tutorial actions that must be performed are marked with bullets.
Filenames, paths and menus are shown in bold. Typed text is in courier.
The following example uses a sample bitstream file supplied with the kit, which per-
forms a board test. It is recommended to perform the board test when you receive the
kit to test both your connections to the board and the board itself:
• Install System Designer from the CD, please refer to the “Installation, Licensing
and Troubleshooting” tutorial available on the Atmel web site, at
http://www.atmel.com/atmel/products/prod319.htm.
• Request and Configure your license, refer to the “Installation, Licensing and
Troubleshooting” tutorial.
• Install CPS from the System Designer CD.
• Copy the test_fpslic.bst file from
c:\SystemDesigner\Examples\at94k\ATSTK94Designs or from
http://www.atmel.com/atmel/products/prod320.htm to c:\training\fpslic\lab1.
SettinguptheHardware
• Connect the ATDH2225 25 Pin Cable Block to your PC parallel port.
• Connect the 10-pin header cable to the ATDH2225.
• Connect the end of the cable with the locating pin on one to the board.
• Set the Program switch to the Prog position.
• Pluginthepower.
•SetthePower switch to the ON position.
• The power LED lights.
ATST94K
Tutorial
Rev. 2449A–FPSLI–01/02

2Testing the ATSTK94
2449A–FPSLI–01/02
Downloading to the
Configurator
• GototheStart menu and choose Programs > Atmel > Atmel CPS 7.0x.Atmel
CPS opens, see Figure 1.
Figure 1. Atmel CPS Window
•Select/P Partition, Program and Verify from an Atmel File from the Procedure
pull-down menu in the CPS window.
• Use the button from the Input File pull-down menu to locate the test_fpslic.bst
file under c:\training\fpslic\lab1.
• Use the button from the Output File pull-down menu to indicate the out.bst file
under c:\training\fpslic\lab1.
•Select1M from the EEPROM Density pull-down menu.
• Use the default options for the rest.
•PressStart Procedure to program the Configurator.
If the utility has not been calibrated on a given PC, the Clock Calibration dialog will
be displayed when the Start Procedure button is clicked, see Figure 2. For best
results, it is highly recommended to allow Clock Calibration to proceed prior to the
execution of the procedure. The clock calibration routine accounts for any variations
in time delay units between different processors.

3
Testing the ATSTK94
2449A–FPSLI–01/02
Figure 2. Clock Calibration Dialog Box
•PressYes. A calibration accuracy dialog box opens.
Low,Medium and High refer to the accuracy of the calibration. A high level of cali-
bration will require more time to complete. Calibration can be performed again or at
a later time by going to the Calibrate menu and selecting Calibrate now.The
out.bst filecanbeoverwritten.
If successful, the results are shown in Figure 3.
Figure 3. CPS Window Results
• After CPS reports successful completion you can switch from Prog. to Run.
Your design starts to run. The Alphanumeric will show a count sequence from 0 to 9
and from A to Z and will then reset to 0. The LED will show the counting up
sequence.

4Testing the ATSTK94
2449A–FPSLI–01/02
If your design does not run immediately you can set JP19 to RESET and use the
RESET button SW12 to force a download from the Configurator to the FPSLIC
device. You can also power-cycle the device.
The Checksum number is the number of data bits in the bitstream file, the checksum
number shown here is for test_fpslic.bst file. This number can be used to check if the
data is corrupted during file transfer.
Hardware
Troubleshooting
Your design can encounter the following errors:
Error message “Expected 1 but found 0”
- No Power to the board
- Prog/ Run in the wrong position
or:
FATAL_ERROR: CMD ack_sense timed out
Double check the orientation of cable connected to evaluation board
Any other failure would be related to the following
• Check to see that the Jumpers and Switches are in default positions, see Table 1.
• The next area to check is the pinlocks. In Figaro, during the parts process, make
sure that you have selected to assign pinlocks. Without performing this step, your
project will not run on the board, since you have not connected the signals to the
correct pins on the board.
• Check to see that the AVR-FPGA Interface has the correct connections.
• Run co-verification on your design
Please refer to the CPS Troubleshooting guide for a complete description. Go to the
Help menu and select Contents > Trouble Shooting.

5
Testing the ATSTK94
2449A–FPSLI–01/02
Table 1. Default for Jumpers and Switches
Jumper/Switch Default Position
JP 1-16 The default position for all the switches and LEDs is with the Jumper set to
the “A” position, which means that the switches and LEDs are connected
to the microcontroller. By setting the jumpers to the “F” position, the
switches and LEDs are connected to FPGA.
JP17 Rev 2 – The jumper is set towards the edge of the board, this connects to
the 4 MHz crystal. Connecting to other side will connect to the 18 MHz
crystal.
Rev3 and beyond – The position of the jumper is changed and it should be
set on the inner side to connect to the 4 MHz crystal. Connecting towards
the outer side of the board will connect to the 18 MHz crystal.
JP18 Has a Jumper Connected
JP19 Set to the RESET Position
JP20 Jumper connects the SER_EN pin of the AT17 device to the PORTE pin 7
of the microcontroller. By connecting this jumper, you can perform 2-wire
serial interface. Default is “Not Connected”
JP21 Jumper Connects CEO/A2 to VCC. Default is “Not Connected”
JP22 Jumper connects the write protect pins of the AT17 device to VCC.Default is
“Not Connected”
JP23 Rev4 and beyond – Jumper connects the write protect pins of the AT17
device to VCC. Default is “Not Connected”
ON/OFF (Sw14) Power Switch. Default Position Off
Run /Prog Switch Set to Prog.

Printed on recycled paper.
© Atmel Corporation 2002.
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2449A–FPSLI–01/02 xM
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