Atmel AVR AT90S2333 User manual

1
Pin Configurations
TQFP Top View PDIP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(INT1) PD3
(T0) PD4
NC
VCC
GND
NC
XTAL1
XTAL2
PC1 (ADC1)
PC0 (ADC0)
NC
AGND
AREF
NC
AVCC
PB5 (SCK)
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
(T1) PD5
(AIN0) PD6 (AIN1) PD7
(ICP) PB0
(OC1) PB1
(SS) PB2
(MOS1) PB3 (MOS0) PB4
PD2 (INT0) PD1 (TXD) PD0 (RDX) RESET PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(T0) PD4
VCC
GND
XTAL1
XTAL2
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP) PB0
PC5 (ADC5)
PC4 (ADC4)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
AGND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI)
PB2 (SS)
PB1 (OC1)
Features
•High-performance and Low-power AVR®8-bit RISC Architecture
– 118 Powerful Instructions - Most Single Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
•Data and Nonvolatile Program Memory
– 2K/4K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128/256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Expanded 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Programmable UART
– 6-channel, 10-bit ADC
– Master/Slave SPI Serial Interface
•Special Microcontroller Features
– Brown-Out Reset Circuit
– Enhanced Power-on Reset Circuit
– Low-Power Idle and Power Down Modes
– External and Internal Interrupt Sources
•Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.4 mA
– Idle Mode: 1.4 mA
– Power Down Mode: <1 µA
•I/O and Packages
– 20 Programmable I/O Lines
– 28-pin PDIP and 32-pin TQFP
•Operating Voltage
– 2.7V - 6.0V (AT90LS2333 and AT90LS4433)
– 4.0V - 6.0V (AT90S2333 and AT90S4433)
•Speed Grades
– 0 - 4 MHz (AT90LS2333 and AT90LS4433)
– 0 - 8 MHz (AT90S2333 and AT90S4433)
Rev. 1042D–04/99
8-bit
Microcontroller
with 2K/4K bytes
In-System
Programmable
Flash
AT90S2333
AT90LS2333
AT90S4433
AT90LS4433
Preliminary

AT90S/LS2333 and AT90S/LS4433
2
Description
The AT90S2333/4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing pow-
erful instructions in a single clock cycle, the AT90S2333/4433 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The AT90S2333/4433 provides the following features: 2K/4K bytes of In-System Programmable Flash, 128/256 bytes
EEPROM, 128 bytes SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible
timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC,
programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue function-
ing. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the
next interrupt or hardware reset.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip Flash program mem-
ory can be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a
powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The AT90S2333/4433 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Table 1. Comparison Table
Device Flash EEPROM SRAM Voltage Range Frequency
AT90S2333 2K 128B 128B 4.0V - 6.0V 0 - 8 MHz
AT90LS2333 2K 128B 128B 2.7V - 6.0V 0 - 4 MHz
AT90S4433 4K 256B 128B 4.0V - 6.0V 0 - 8 MHz
AT90LS4433 4K 256B 128B 2.7V - 6.0V 0 - 4 MHz

AT90S/LS2333 and AT90S/LS4433
3
Block Diagram
Figure 1. The AT90S2333/4433 Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH MCU CONTROL REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTC
DATA REGISTER
PORTB
DATA REGISTER
PORTC
ANALOG MUX ADC
DATA REGISTER
PORTD
PROGRAMMING
LOGIC
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI UART
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PORTC DRIVERS
PORTD DRIVERS
PB0 - PB5
PC0 - PC5
RESET
VCC
AVCC
AGND
AREF
GND
XTAL2
XTAL1
CONTROL
LINES
+
-
ANALOG
COMPARATOR
PD0 - PD7
8-BIT DATA BUS
DATA DIR.
REG. PORTD

AT90S/LS2333 and AT90S/LS4433
4
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
Port B also serves the functions of various special features of the AT90S2333/4433 as listed on page 60.
The port B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port C (PC5..PC0)
Port C is a 6-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the
analog inputs to the A/D Converter.
The port C pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S2333/4433 as listed on page 67.
The port D pins are tristated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
AVCC
This is the supply voltage pin for the A/D Converter. It should be externally connected to VCC via a low-pass filter. See
page 52 for details on operation of the ADC.
AREF
This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2.7V to AVCC must be
applied to this pin.
AGND
If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to
GND.

AT90S/LS2333 and AT90S/LS4433
5
Clock Options
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-
chip oscillator, as shown in Figure 2 and Figure 3. Either a quartz crystal or a ceramic resonator may be used.
External Clock
If the oscillator is to be used as a clock for an external device, the clock signal from XTAL2 may be routed to one HC buffer,
while reducing the load capacitor by 5 pF, as shown in Figure 3. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven as shown in Figure 4.
Figure 2. Oscillator Connections
Figure 3. Using MCU Oscillator as a Clock for an External Device
Figure 4. External Clock Drive Configuration
XTAL1
REDUCE BY 5PF
MAX 1 HC BUFFER
XTAL2
HC

AT90S/LS2333 and AT90S/LS4433
6
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 5 shows the AT90S2333/4433 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
Figure 5. The AT90S2333/4433 AVR RISC Architecture
1K/2K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control Interrupt
Unit
SPI
Unit
8-bit
Timer/Counter
Watchdog
Timer
Analog to Digital
Converter
Analog
Comparator
20
I/O Lines
128/256 x 8
EEPROM
Data Bus 8-bit
AVR AT90S2333/4433 Architecture
Serial
UART
16-bit
Timer/Counter
with PWM
128 x 8
Data
SRAM
Direct Addressing
Indirect Addressing

AT90S/LS2333 and AT90S/LS4433
7
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle.
The program memory is In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 1K/2K word address space is directly accessed. Most AVR instruc-
tions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-
cuted). The 8-bit stack pointer SP is read/write accessible in the I/O space.
The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 6. AT90S2333/4433 Memory Maps
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.
32 Gen. Purpose
Working Registers
64 I/O Registers
Internal SRAM
(128 x 8)
$0000
$001F
$005F
$0060
$00DF
$0020
$000
$3FF/ $7FF
Data MemoryProgram Memory
Program Flash
(1K/2K x 16)

AT90S/LS2333 and AT90S/LS4433
8
General Purpose Register File
Figure 7 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only
exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and
a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the reg-
isters in the register file - R16..R31. The general SBC, SUB, CP, AND, and OR, and all other operations between two
registers or on a single register apply to the entire register file.
As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 loca-
tions of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register in the file.
X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers
for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:
Figure 8. X, Y and Z Registers
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and
decrement (see the descriptions for the different instructions).
70Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
15 0
X - register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y - register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z - register 7 0 7 0
R31 ($1F) R30 ($1E)

AT90S/LS2333 and AT90S/LS4433
9
ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories - arithmetic, logical, and bit-functions.
In-System Programmable Flash Program Memory
The AT90S2333/4433 contains 2K/4K bytes on-chip In-System Programmable Flash memory for program storage. Since
all instructions are 16-or 32-bit words, the Flash is organized as 1K/2K x 16. The Flash memory has an endurance of at
least 1000 write/erase cycles. The AT90S2333/4433 Program Counter (PC) is 10/11 bits wide, thus addressing the
1024/2048 program memory addresses. See page 78 for a detailed description on Flash data downloading. See page 10
for the different program memory addressing modes.
Figure 9. SRAM Organization
SRAM Data Memory
The figure above shows how the AT90S2333/4433 SRAM Memory is organized.
The lower 224 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first 96
locations address the Register File and I/O Memory, and the next 128 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with
Pre-Decrement, and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement mode features a 63 address locations
reach from the base address given by the Y or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y and Z are decremented and incremented.
Register File Data Address Space
R0 $0000
R1 $0001
R2 $0002
……
R29 $001D
R30 $001E
R31 $001F
I/O Registers
$00 $0020
$01 $0021
$02 $0022
……
$3D $005D
$3E $005E
$3F $005F
Internal SRAM
$0060
$0061
…
$00DE
$00DF

AT90S/LS2333 and AT90S/LS4433
10
The 32 general purpose working registers, 64 I/O registers and the 128 bytes of internal data SRAM in the
AT90S2333/4433 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
Program and Data Addressing Modes
The AT90S2333/4433 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Flash
program memory, SRAM, Register File, and I/O data memory. This section describes the different addressing modes sup-
ported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all
figures show the exact location of the addressing bits.
Register Direct, Single Register Rd
Figure 10. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd and Rr
Figure 11. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

AT90S/LS2333 and AT90S/LS4433
11
I/O Direct
Figure 12. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Data Direct
Figure 13. Direct Data Addressing
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register.
Data Indirect with Displacement
Figure 14. Data Indirect with Displacement
Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction
word.
OP Rr/Rd 16
31
15 0
16 LSBs
$0000
$00DF
20 19 Data Space
Data Space $0000
$00DF
Y OR Z - REGISTER
OP an
0
05610
15
15

AT90S/LS2333 and AT90S/LS4433
12
Data Indirect
Figure 15. Data Indirect Addressing
Operand address is the contents of the X, Y, or the Z-register.
Data Indirect with Pre-Decrement
Figure 16. Data Indirect Addressing with Pre-Decrement
The X, Y, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y,
or the Z-register.
Data Indirect with Post-Increment
Figure 17. Data Indirect Addressing with Post-Increment
The X, Y, or the Z-register is incremented after the operation. Operand address is the content of the X, Y, or the Z-register
prior to incrementing.
Data Space $0000
$00DF
X, Y, OR Z - REGISTER
015
Data Space $0000
$00DF
X, Y, OR Z - REGISTER
015
-1
Data Space $0000
$00DF
X, Y, OR Z - REGISTER
015
1

AT90S/LS2333 and AT90S/LS4433
13
Constant Addressing Using the LPM Instruction
Figure 18. Code Memory Constant Addressing
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K/2K), the LSB
selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
Indirect Program Addressing, IJMP and ICALL
Figure 19. Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Z-
register).
Relative Program Addressing, RJMP and RCALL
Figure 20. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.
$3FF/$7FF
$000
PROGRAM MEMORY
$3FF/$7FF
$000
PROGRAM MEMORY
$3FF/$7FF
$000
PROGRAM MEMORY

AT90S/LS2333 and AT90S/LS4433
14
EEPROM Data Memory
The AT90S2333/4433 contains 128/256 bytes of data EEPROM memory. It is organized as a separate data space, in
which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per
location. The access between the EEPROM and the CPU is described on page 44 specifying the EEPROM address regis-
ters, the EEPROM data register, and the EEPROM control register.
For the SPI data downloading, see page 78 for a detailed description. The EEPROM data memory is In-System Program-
mable through the SPI port. Please refer to the “EEPROM Read/Write Access” section on page 38 for a thorough
description on EEPROM access.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal
clock division is used.
Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 21. The Parallel Instruction Fetches and Instruction Executions
Figure 22 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 22. Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 23.
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4

AT90S/LS2333 and AT90S/LS4433
15
Figure 23. On-Chip Data SRAM Access Cycles
I/O Memory
The I/O space definition of the AT90S2333/4433 is shown in the following table:
Table 2. AT90S2333/4433 I/O Space
I/O Address (SRAM Address) Name Function
$3F ($5F) SREG Status REGister
$3D ($5D) SP Stack Pointer
$3B ($5B) GIMSK General Interrupt MaSK register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt MaSK register
$38 ($58) TIFR Timer/Counter Interrupt Flag register
$35 ($55) MCUCR MCU general Control Register
$34 ($54) MCUSR MCU general Status Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$2F ($4F) TCCR1A Timer/Counter1 Control Register A
$2E ($4E) TCCR1B Timer/Counter1 Control Register B
$2D ($4D) TCNT1H Timer/Counter1 High Byte
$2C ($4C) TCNT1L Timer/Counter1 Low Byte
$2B ($4B) OCR1H Timer/Counter1 Output Compare Register High Byte
$2A ($4A) OCR1L Timer/Counter1 Output Compare Register Low Byte
$27 ($47) ICR1H Timer/Counter1 Input Capture Register High Byte
$26 ($46) ICR1L Timer/Counter 1 Input Capture Register Low Byte
$21 ($41) WDTCR Watchdog Timer Control Register
$1E ($3E) EEAR EEPROM Address Register
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
System Clock Ø
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read Write

AT90S/LS2333 and AT90S/LS4433
16
Note: Reserved and unused locations are not shown in the table.
All AT90S2333/4433 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT
instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the
address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of sin-
gle bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details.
When using the I/O specific commands IN, OUT the I/O addresses $00 - $3F must be used. When addressing I/O registers
as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the
SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero when accessed. Reserved I/O memory
addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
$15 ($35) PORTC Data Register, Port C
$14 ($34) DDRC Data Direction Register, Port C
$13 ($33) PINC Input Pins, Port C
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0F ($2F) SPDR SPI I/O Data Register
$0E ($2E) SPSR SPI Status Register
$0D ($2D) SPCR SPI Control Register
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) USR UART Status Register
$0A ($2A) UCR UART Control Register
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR Analog Comparator Control and Status Register
$07 ($27) ADMUX ADC Multiplexer Select Register
$06 ($26) ADCSR ADC Control and Status Register
$05 ($25) ADCH ADC Data Register High
$04 ($24) ADCL ADC Data Register Low
$03 ($23) UBRRHI UART Baud Rate Register High
Table 2. AT90S2333/4433 I/O Space (Continued)
I/O Address (SRAM Address) Name Function

AT90S/LS2333 and AT90S/LS4433
17
Status Register - SREG
The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:
•Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts
are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts.
•Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A
bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
•Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetical operations. See the Instruction Set Description for detailed
information.
•Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-
tion Set Description for detailed information.
•Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
•Bit 2 - N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set Description
for detailed information.
•Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set Description for
detailed information.
•Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set Description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Stack Pointer - SP
The AT90S2333/4433 Stack Pointer is implemented as an 8-bit register in the I/O space location $3D ($5D). As the
AT90S2333/4433 data memory has $0DF locations, 8 bits are used.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed
onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with
subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SP
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0

AT90S/LS2333 and AT90S/LS4433
18
instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
Reset and Interrupt Handling
The AT90S2333/4433 provides 13 different interrupt sources. These interrupts and the separate reset vector, each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0, etc.
The most typical program setup for the Reset and Interrupt Vector Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
$003 rjmp TIM1_CAPT ; Timer1 Capture Handler
$004 rjmp TIM1_COMP ; Timer1 compare Handler
$005 rjmp TIM1_OVF ; Timer1 Overflow Handler
$006 rjmp TIM0_OVF ; Timer0 Overflow Handler
$007 rjmp SPI_STC; ; SPI Transfer Complete Handler
$008 rjmp UART_RXC ; UART RX Complete Handler
$009 rjmp UART_DRE ; UDR Empty Handler
$00a rjmp UART_TXC ; UART TX Complete Handler
$00b rjmp ADC ; ADC Conversion Complete Interrupt Handler
$00c rjmp EE_RDY ; EEPROM Ready Handler
$00d rjmp ANA_COMP ; Analog Comparator Handler
;
Table 3. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET External Pin, Power-On Reset, Brown-Out Reset and Watchdog Reset.
2 $001 INT0 External Interrupt Request 0
3 $002 INT1 External Interrupt Request 1
4 $003 TIMER1 CAPT Timer/Counter1 Capture Event
5 $004 TIMER1 COMP Timer/Counter1 Compare Match
6 $005 TIMER1 OVF Timer/Counter1 Overflow
7 $006 TIMER0 OVF Timer/Counter0 Overflow
8 $007 SPI, STC Serial Transfer Complete
9 $008 UART, RX UART, Rx Complete
10 $009 UART, UDRE UART Data Register Empty
11 $00A UART, TX UART, Tx Complete
12 $00B ADC ADC Conversion Complete
13 $00C EE_RDY EEPROM Ready
14 $00D ANA_COMP Analog Comparator

AT90S/LS2333 and AT90S/LS4433
19
$00e MAIN: ldi r16,low(RAMEND); Main program start
$00f out SP,r16;
$010 <instr> xxx ;
… … … …
Reset Sources
The AT90S2333/4433 has four sources of reset:
• Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
• Brown-Out Reset. The MCU is reset when the supply voltage VCC falls below a certain voltage.
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the pro-
gram never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 24 shows the reset logic. Table 4 and Table 5 define the timing and electrical
parameters of the reset circuitry.
Figure 24. Reset Logic
Note: The Power-On Reset will not work unless the supply voltage has been below Vpot (falling).
Table 4. Reset Characteristics (VCC = 5.0V)
Symbol Parameter Min Typ Max Units
VPOT
Power-On Reset Threshold Voltage,
rising 1.0 1.4 1.8 V
Power-On Reset Threshold Voltage,
falling 0.4 0.6 0.8 V
VRST RESET Pin Threshold Voltage 0.6VCC V
VBOT Brown-Out Reset Threshold Voltage 2.6 (BODLEVEL = 1) 2.7 (BODLEVEL = 1) 2.8 (BODLEVEL = 1) V
3.8 (BODLEVEL = 0) 4.0 (BODLEVEL = 0) 4.2 (BODLEVEL = 0)
MCU Status
Register (MCUSR)
Brown-Out
Reset Circuit
BODEN
BODLEVEL
Delay Counters
CKSEL[2:0]
CK
Full
WDRF
BORF
EXTRF
PORF
DATA BUS

AT90S/LS2333 and AT90S/LS4433
20
Notes: 1. Or external power-on reset.
This table shows the start-up times from reset. From sleep, only the clock counting part of the start-up time is used. The
watchdog oscillator is used for timing the real-time part of the start-up time. The number WDT oscillator cycles used for
each time-out is shown in Table 6.
The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section.
Power-On Reset
A Power-On Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is nominally 2.2V. The
POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up reset, as
well as detect a failure in supply voltage.
The Power-On Reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after VCC rise. The
time-out period of the delay counter is a combination of internal RC oscillator cycles and external oscillator cycles, and it
can be defined by the user through the CKSEL fuses. The eight different selections for the delay period are presented in
Table 5. The RESET signal is activated again, without any delay, when the VCC decreases below detection level.
Figure 25. MCU Start-Up, RESET Tied to VCC.
Table 5. Reset Delay Selections
CKSEL [2:0] Start-Up Time, tTOUT at VCC = 2.7V Start-Up Time, tTOUT at VCC = 5.0V Recommended Usage
000 16 ms + 6 CK 4 ms + 6 CK External Clock, slowly rising power
001 6 CK 6 CK External Clock, BOD enabled(1)
010 256 ms + 16K CK 64 ms + 16K CK Crystal Oscillator
011 16 ms + 16K CK 4 ms + 16K CK Crystal Oscillator, fast rising power
100 16K CK 16K CK Crystal Oscillator, BOD enabled(1)
101 256 ms + 1K CK 64 ms + 1K CK Ceramic Resonator
110 16 ms + 1K CK 4 ms + 1K CK Ceramic Resonator, fast rising power
111 1K CK 1K CK Ceramic Resonator, BOD enabled (1)
Table 6. Number of Watchdog Oscillator Cycles
Time-out Number of cycles
4.0 ms (at Vcc=5.0V) 4K
64 ms (at Vcc=5.0V) 64K
VCC
RESET
TIME-OUT
INTERNAL
RESET
tTOUT
VPOT
VRST