Atmel AT90S8515-8PI User manual

1
Features
•Utilizes the AVR®RISC Architecture
•AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
•Data and Nonvolatile Program Memory
– 4K/8K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 256/512 Bytes of SRAM
– 256/512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
•Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler
Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
•Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
•Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
•Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power Down Mode: <1 µA
•I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-pin PLCC and TQFP
•Operating Voltages
– 2.7 - 6.0V (AT90S4414-4 and AT90S8515-4)
– 4.0 - 6.0V (AT90S4414-8 and AT90S8515-8)
•Speed Grades
– 0 - 4 MHz (AT90S4414-4 and AT90S8515-4)
– 0 - 8 MHz (AT90S4414-8 and AT90S8515-8)
Rev. 0841E–04/99
8-bit
Microcontroller
with 4K/8K
bytes In-System
Programmable
Flash
AT90S4414
AT90S8515
Pin Configurations

AT90S4414/8515
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Description
The AT90S4414/AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By execut-
ing powerful instructions in a single clock cycle, the AT90S4414/8515 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 1. The AT90S4414/8515 Block Diagram

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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The AT90S4414/8515 provides the following features: 4K/8K bytes of In-System Programmable Flash, 256/512 bytes
EEPROM, 256/512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, flexible
timer/counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watch-
dog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes. The Idle Mode stops
the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down
mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt
or hardware reset.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip in-system programma-
ble Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional
nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a
monolithic chip, the Atmel AT90S4414/8515 is a powerful microcontroller that provides a highly flexible and cost effective
solution to many embedded control applications.
The AT90S4414/8515 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Comparison Between AT90S4414 and AT90S8515
The AT90S4414 has 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM and 256 bytes of internal SRAM.
The AT90S8515 has 8K bytes of In-System Programmable Flash, 512 bytes of EEPROM and 512 bytes of internal SRAM.
Table 1 summarizes the different memory sizes for the two devices.
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A
output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are
externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port A serves as Multiplexed Address/Data input/output when using external SRAM.
Table 1. Memory Size Summary
Part Flash EEPROM SRAM
AT90S4414 4K bytes 256 bytes 256 bytes
AT90S8515 8K bytes 512 bytes 512 bytes

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Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S4414/8515 as listed on page 58.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port C also serves as Address output when using external SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S4414/8515 as listed on page 64.
RESET
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses
are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
ICP
ICP is the input pin for the Timer/Counter1 Input Capture function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output CompareB function
ALE
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during
the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device
from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

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Figure 2. Oscillator Connections
Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.
Figure 3. External Clock Drive Configuration
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 4 shows the AT90S4414/8515 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
XTAL2
XTAL1
GND
C2
C1
MAX 1 HC BUFFER
HC

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The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system programmable Flash memory.
With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions
have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.
The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR
architecture are all linear and regular memory maps.
Figure 4. The AT90S4414/8515 AVR RISC Architecture
Data Bus 8-bit
2K/4K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter Status and Test
32 x 8
General
Purpose
Registers
ALU
256/512 x 8
Data
SRAM
Direct Addressing
Indirect Addressing
Control
Registers
Interrupt
Unit
SPI
Unit
Serial
Uart
8-bit
Timer/Counter
16-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog
Comparator
32
I/O Lines
256/512 x 8
EEPROM

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A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address the higher the priority.
Figure 5. Memory Maps
$0000
Data Memory
Program Memory
32 Gen. Purpose
Working Registers $001F
$0020
$005F
$015F/$025F
$0060
$0160/$0260
$FFFF
64 I/O Registers
Internal SRAM
(256/512 x 8)
External SRAM
(0-64K X 8)
Program FLASH
(2K/4K x 16)
$000
$7FF/$FFF

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General Purpose Register File
Figure 6 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6. AVR CPU General Purpose Working Registers
All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a
register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the
registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two
registers or on a single register apply to the entire register file.
As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 loca-
tions of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X,Y and Z registers can be set to index any register in the file.
X-Register, Y-Register And Z-Register
The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers
for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:
Figure 7. X, Y and Z Registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and
decrement (see the descriptions for the different instructions).
70Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
15 0
X - register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y - register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z - register 7 0 7 0
R31 ($1F) R30 ($1E)

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ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories - arithmetic, logical and bit-functions.
In-System Programmable Flash Program Memory
The AT90S4414/8515 contains 4K/8K bytes on-chip In-System Programmable Flash memory for program storage. Since
all instructions are 16-or 32-bit words, the Flash is organized as 2K x 16/4K x 16. The Flash memory has an endurance of
at least 1000 write/erase cycles. The AT90S4414/8515 Program Counter (PC) is 11/12 bits wide, thus addressing the
2048/4096 program memory addresses.
See page 77 for a detailed description on Flash data downloading.
See page 10 for the different program memory addressing modes.
SRAM Data Memory - Internal and External
The following figure shows how the AT90S4414/8515 SRAM Memory is organized:
Figure 8. SRAM Organization
Register File Data Address Space
R0 $0000
R1 $0001
R2 $0002
……
R29 $001D
R30 $001E
R31 $001F
I/O Registers
$00 $0020
$01 $0021
$02 $0022
……
$3D $005D
$3E $005E
$3F $005F
Internal SRAM
$0060
$0061
…
$015E/$025E
$015F/$025F
External SRAM
$0160/$0260
$0161/$0261
…
$FFFE
$FFFF

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The lower 352/608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first
96 locations address the Register File + I/O Memory, and the next 256/512 locations address the internal data SRAM. An
optional external data SRAM can be placed in the same SRAM memory space. This SRAM will occupy the location follow-
ing the internal SRAM and up to as much as 64K - 1, depending on SRAM size.
When the addresses accessing the data memory space exceeds the internal data SRAM locations, the external data
SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data space is
accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM opera-
tion is enabled by setting the SRE bit in the MCUCR register. See page 27 for details.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means
that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external
SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is
pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is used per byte.
This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and
returns will need four clock cycles more than specified in the instruction set manual.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with
Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or
Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O registers, the 256/512 bytes of internal data SRAM, and the 64K bytes of
optional external data SRAM in the AT90S4414/8515 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
Program and Data Addressing Modes
The AT90S4414/8515 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the pro-
gram memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different
addressing modes supported by the
AVR architecture. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single Register RD
Figure 9. Direct Single Register Addressing
The operand is contained in register d (Rd).

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Register Direct, Two Registers Rd and Rr
Figure 10. Direct Register Addressing, two registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
I/O Direct
Figure 11. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

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Data Direct
Figure 12. Direct Data Addressing
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register.
Data Indirect with Displacement
Figure 13. Data Indirect with Displacement
Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction
word.

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Data Indirect
Figure 14. Data Indirect Addressing
Operand address is the contents of the X, Y or the Z-register.
Data Indirect with Pre-decrement
Figure 15. Data Indirect Addressing with Pre-decrement
The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y
or the Z-register.

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Data Indirect with Post-increment
Figure 16. Data Indirect Addressing with Post-increment
The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register
prior to incrementing.
Constant Addressing Using the LPM Instruction
Figure 17. Code Memory Constant Addressing
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 2K/4K), the LSB
selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
$000
$7FF/$FFF
PROGRAM MEMORY
15 1 0
Z-REGISTER

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Indirect Program Addressing, IJMP and ICALL
Figure 18. Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the
Z-register).
Relative Program Addressing, RJMP and RCALL
Figure 19. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
EEPROM Data Memory
The AT90S4414/8515 contains 256/512 bytes of data EEPROM memory. It is organized as a separate data space, in
which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The
access between the EEPROM and the CPU is described on page 39 specifying the EEPROM address registers, the
EEPROM data register, and the EEPROM control register.
For the SPI data downloading, see page 77 for a detailed description.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal
clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
$000
$7FF/$FFF
PROGRAM MEMORY
15 0
Z-REGISTER
$000
$7FF/$FFF
PROGRAM MEMORY
15 0
15 0
12 11
PC
OP k

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Figure 20. The Parallel Instruction Fetches and Instruction Executions
Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 21. Single Cycle ALU Operation
The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.
Figure 22. On-chip Data SRAM Access Cycles
See “Interface to External SRAM” on page 53 for a description of the access to the external SRAM.
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
System Clock Ø
WR
RD
Data
Data
Address Address
T1 T2 T3 T4
Prev. Address
Read Write

AT90S4414/8515
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I/O Memory
The I/O space definition of the AT90S4414/8515 is shown in the following table:
Table 2. AT90S4414/8515 I/O Space
Address Hex Name Function
$3F ($5F) SREG Status Register
$3E ($5E) SPH Stack Pointer High
$3D ($5D) SPL Stack Pointer Low
$3B ($5B) GIMSK General Interrupt Mask register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt Mask register
$38 ($58) TIFR Timer/Counter Interrupt Flag register
$35 ($55) MCUCR MCU general Control Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$2F ($4F) TCCR1A Timer/Counter1 Control Register A
$2E ($4E) TCCR1B Timer/Counter1 Control Register B
$2D ($4D) TCNT1H Timer/Counter1 High Byte
$2C ($4C) TCNT1L Timer/Counter1 Low Byte
$2B ($4B) OCR1AH Timer/Counter1 Output Compare Register A High Byte
$2A ($4A) OCR1AL Timer/Counter1 Output Compare Register A Low Byte
$29 ($49) OCR1BH Timer/Counter1 Output Compare Register B High Byte
$28 ($48) OCR1BL Timer/Counter1 Output Compare Register B Low Byte
$25 ($45) ICR1H T/C 1 Input Capture Register High Byte
$24 ($44) ICR1L T/C 1 Input Capture Register Low Byte
$21 ($41) WDTCR Watchdog Timer Control Register
$1F ($3E) EEARH EEPROM Address Register High Byte (AT90S8515)
$1E ($3E) EEARL EEPROM Address Register Low Byte
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$1B ($3B) PORTA Data Register, Port A
$1A ($3A) DDRA Data Direction Register, Port A
$19 ($39) PINA Input Pins, Port A
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
$15 ($35) PORTC Data Register, Port C
$14 ($34) DDRC Data Direction Register, Port C
$13 ($33) PINC Input Pins, Port C

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Note: Reserved and unused locations are not shown in the table
All AT90S4414/8515 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT
instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the
address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of
single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details.
When using the I/O specific commands IN, OUT the I/O addresses $00 - $3F must be used. When addressing I/O registers
as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the
SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
The I/O and peripherals control registers are explained in the following chapters.
Status Register - SREG
The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:
•Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are
enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts.
•Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit.
A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in
a register in the register file by the BLD instruction.
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0F ($2F) SPDR SPI I/O Data Register
$0E ($2E) SPSR SPI Status Register
$0D ($2D) SPCR SPI Control Register
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) USR UART Status Register
$0A ($2A) UCR UART Control Register
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR Analog Comparator Control and Status Register
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 2. AT90S4414/8515 I/O Space (Continued)
Address Hex Name Function

AT90S4414/8515
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•Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed
information.
•Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-
tion Set Description for detailed information.
•Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
•Bit 2 - N: Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set
Description for detailed information.
•Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description
for detailed information.
•Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Stack Pointer - SP
The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and
$3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed
onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with
subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
Reset and Interrupt Handling
The AT90S4414/8515 provides 12 different interrupt sources. These interrupts and the separate reset vector, each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0 etc.
Bit 151413121110 9 8
$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
00000000

AT90S4414/8515
20
The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
$003 rjmp TIM1_CAPT ; Timer1 Capture Handler
$004 rjmp TIM1_COMPA ; Timer1 CompareA Handler
$005 rjmp TIM1_COMPB ; Timer1 CompareB Handler
$006 rjmp TIM1_OVF ; Timer1 Overflow Handler
$007 rjmp TIM0_OVF ; Timer0 Overflow Handler
$008 rjmp SPI_STC ; SPI Transfer Complete Handler
$009 rjmp UART_RXC ; UART RX Complete Handler
$00a rjmp UART_DRE ; UDR Empty Handler
$00b rjmp UART_TXC ; UART TX Complete Handler
$00c rjmp ANA_COMP ; Analog Comparator Handler
;
$00d MAIN: ldi r16,high(RAMEND); Main program start
$00e out SPH,r16
$00f ldi r16,low(RAMEND)
$010 out SPL,r16
$011 <instr> xxx
… … … …
Table 3. Reset and Interrupt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET External Reset, Power-on Reset and Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 INT1 External Interrupt Request 1
4 $003 TIMER1 CAPT Timer/Counter1 Capture Event
5 $004 TIMER1 COMPA Timer/Counter1 Compare Match A
6 $005 TIMER1 COMPB Timer/Counter1 Compare Match B
7 $006 TIMER1 OVF Timer/Counter1 Overflow
8 $007 TIMER0, OVF Timer/Counter0 Overflow
9 $008 SPI, STC Serial Transfer Complete
10 $009 UART, RX UART, Rx Complete
11 $00A UART, UDRE UART Data Register Empty
12 $00B UART, TX UART, Tx Complete
13 $00C ANA_COMP Analog Comparator