Curtiss-Wright DTI-VME/S User manual

DTI-VME/S
User Manual
Document No. T-T-MU-DTXXVS##-A-0-A2

FOREWORD
The information in this document has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. Curtiss-Wright Controls, Inc. reserves the right to make changes
without notice.
Curtiss-Wright Controls makes no warranty of any kind with regard to this printed material, including, but
not limited to, the implied warranties of merchantability and fitness for a particular purpose.
Copyright 2004 Systran Division of Curtiss-Wright Controls, Inc. All Rights Reserved.
Revised: September 3, 2004
(Previously DTI Doc. No. 88-30003)
Curtiss-Wright Controls, Inc. Embedded Computing
Data Communications
2600 Paramount Place Suite 200
Fairborn, OH 45324 USA
[phone](U.S. only)
[phone]

FCC
This product is intended for use in industrial, laboratory or military environments. This product uses and
emits electromagnetic radiation, which may interfere with other radio and communication devices. The
user may be in violation of FCC regulations if this device is used in other than the intended market
environments.
CE
As a component part of another system, this product has no intrinsic function and is therefore not subject to
European Union CE EMC directive 89/336/EEC.

TABLE OF CONTENTS
1. OVERVIEW...............................................................................................................................................1-1
1.1 Enhanced Intelligence ...............................................................................................................1-1
1.2 Highly Flexible Configuration ..................................................................................................1-1
1.3 Enhanced Bus Connection Capability.......................................................................................1-2
1.4 DTI-VME/S Onboard Dual-Port RAM.....................................................................................1-2
1.5 Remote Terminal Mode ............................................................................................................1-2
1.6 Bus Controller Mode.................................................................................................................1-2
1.7 Bus Monitor Mode....................................................................................................................1-3
1.8 Interrupt Handling.....................................................................................................................1-3
1.9 Theory of Operation..................................................................................................................1-3
1.10 Specifications..........................................................................................................................1-4
1.11 Quality Assurance...................................................................................................................1-5
1.12 Technical Support ...................................................................................................................1-5
1.13 Ordering Process.....................................................................................................................1-6
2. GETTING STARTED ................................................................................................................................2-1
2.1 Step 1. Unpacking and Examining the Board...........................................................................2-1
2.2 Step 2. Selecting The I/O Base Address...................................................................................2-2
2.3 Step 3. Installing The Board.....................................................................................................2-2
2.4 Step 4. Interconnection to DTI-VME/S Boards or RTs............................................................2-3
2.4.1 Pin 1 Command Strobe (Output)...........................................................................2-3
2.4.2 Pin 2 Subsystem Fail (Input) .................................................................................2-3
2.4.3 Pin 3 External Override (Input).............................................................................2-3
2.4.4 Pin 4 Ground .........................................................................................................2-3
2.5 Step 5. Connecting To The MIL-STD-1553 P2 Backplane......................................................2-3
2.6 Step 6. Setting The Configuration Registers ............................................................................2-4
2.6.1 Register 25: Bus Connection Relay Control...........................................................2-4
2.6.2 Register 26: Memory Size/Start Address/Bank Select ...........................................2-6
2.6.3 Register 27: Standard Address Select....................................................................2-8
2.6.4 Register 28: Extended Address Select...................................................................2-8
2.6.5 Register 29: Interrupt Level and Vector Width Selection......................................2-9
2.6.6 Register 30: Standard Priority Interrupt Vector...................................................2-10
2.6.7 Register 31: High Priority Interrupt Vector.........................................................2-10
2.7 Step 7. Basic Commands For The BC, RT and BM...............................................................2-11
2.7.1 BC Operational Sequence with Interrupts ............................................................2-11
2.7.2 RT Operational Sequence with Interrupts ............................................................2-11
2.7.3 BM Operational Sequence with Interrupts ...........................................................2-13
3. REGISTERS...............................................................................................................................................3-1
3.1 Control Register 00 ...................................................................................................................3-3
3.2 Status Register 01 (Read Only)...............................................................................................3-5
3.3 Current Command Block Instruction Address (BC) Subaddress Response Block
Address (RT) and Next Message Record Block Register (BM) 02................................................3-6
3.4 Polling Compare Register 03 ....................................................................................................3-6
3.5 Bit Word Register 04 ................................................................................................................3-7
3.6 Current Command Register 05 (Read Only) ...........................................................................3-7
3.7 Interrupt Queue Pointer Register 06..........................................................................................3-8
3.8 High Priority Interrupt Enable Register 07 ..............................................................................3-8
3.9 High Priority Interrupt Status/Reset Register 08.......................................................................3-9
3.10 Standard Priority Interrupt Enable Register 09 .....................................................................3-10
3.11 Remote Terminal Address Register 10.................................................................................3-10
3.12 BIT Start Register 11 (Write Only)......................................................................................3-11
3.13 Reset Command Register 12 (Write Only)............................................................................3-11
3.14 Reset Timer Register 13 (Write Only) ................................................................................3-12
3.15 Bus Monitor Control Register 14 .........................................................................................3-12
3.16 Register 15 Reserved............................................................................................................3-12
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TABLE OF CONTENTS
3.17 Bus Monitor Terminal Address Select (RT 0 - 15) 16 ..........................................................3-12
3.18 Bus Monitor Terminal Address Select (RT 16 - 31) 17 .......................................................3-13
3.19 Master Reset Register 18 .....................................................................................................3-13
3.20 Interrupt Counter Read/Clear Register 19.............................................................................3-14
3.21 Autodecrement Interrupt Counter Register 20 ......................................................................3-14
3.22 Registers 21 Through 24 Reserved .....................................................................................3-15
3.23 Bus Connection Relay Control 25........................................................................................3-15
3.24 Memory Size/Start Address/Bank Select 26 ........................................................................3-16
3.25 Standard Address Select 27..................................................................................................3-17
3.26 Extended Address Select 28..................................................................................................3-17
3.27 Interrupt Level And Vector Width Selection 29...................................................................3-18
3.28 Standard Priority Interrupt Vector 30...................................................................................3-19
3.29 High Priority Interrupt Vector 31.........................................................................................3-19
4. INTERRUPTS ............................................................................................................................................4-1
4.1 Standard and High Priority Interrupts .......................................................................................4-1
4.2 Interrupt Level ..........................................................................................................................4-2
4.2.1 Standard Priority Interrupt Level............................................................................4-2
4.2.2 High Priority Interrupt Level..................................................................................4-2
4.3 Interrupt Vectors .......................................................................................................................4-2
4.4 Interrupt Queue .........................................................................................................................4-3
4.5 Operational Interrupt Registers .................................................................................................4-4
4.5.1 Interrupt Queue Pointer Register 06.......................................................................4-4
4.5.2 High Priority Interrupt Enable Register 07.............................................................4-4
4.5.3 High Priority Interrupt Status/Reset Register 08 ....................................................4-5
4.5.4 Standard Priority Interrupt Enable Register 09.......................................................4-5
4.5.5 Interrupt Counter Read/Clear Register 19 ..............................................................4-6
4.5.6 Autodecrement Interrupt Counter Register 20........................................................4-6
5. BUS CONTROLLER MODE OF OPERATION .......................................................................................5-1
5.1 Bus Controller Structure ...........................................................................................................5-2
5.1.1 Head Pointer...........................................................................................................5-2
5.1.2 Control Word .........................................................................................................5-2
5.1.3 Command Word One .............................................................................................5-4
5.1.4 Command Word Two.............................................................................................5-4
5.1.5 Data Pointer............................................................................................................5-4
5.1.6 Status Word Two....................................................................................................5-4
5.1.7 Status Word Two....................................................................................................5-4
5.1.8 Tail Pointer.............................................................................................................5-4
5.2 Mode Code/Broadcast Commands............................................................................................5-5
5.2.1 Mode Command With Data Word (Transmit)........................................................5-5
5.2.2 Mode Command Without Data Word (Transmit)...................................................5-5
5.2.3 Mode Command With Data Word (Receive) .........................................................5-5
5.2.4 Mode Command With Data Word (Broadcast) ......................................................5-6
5.2.5 Mode Command Without Data Word (Broadcast) .................................................5-6
5.2.6 BC-to-RT Transfer (Broadcast)..............................................................................5-6
5.2.7 RT-to-RT Transfer (Broadcast)..............................................................................5-6
6. REMOTE TERMINAL MODE OF OPERATION ....................................................................................6-1
6.1 RT Subaddress Response Block Structure ................................................................................6-1
6.1.1 Control Word .........................................................................................................6-2
6.1.2 Message Status Pointer...........................................................................................6-3
6.1.3 Data List Pointer.....................................................................................................6-4
6.2 RT Subaddress Response Block Operation...............................................................................6-4
6.3 RT Mode Code Response Block ...............................................................................................6-5
6.3.1 Control Word .........................................................................................................6-6
6.3.2 Message Status Pointer...........................................................................................6-7
6.3.3 Data List Pointer.....................................................................................................6-8
6.4 RT Registers..............................................................................................................................6-8
6.4.1 Control Register (00).............................................................................................6-8
6.4.2 RT Address Register (10)......................................................................................6-9
7. BUS MONITOR MODE OF OPERATION...............................................................................................7-1
7.1 Bus Monitor Message Blocks ...................................................................................................7-1
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TABLE OF CONTENTS
7.1.1 Control/Status Word...............................................................................................7-2
7.1.2 Command Word One .............................................................................................7-2
7.1.3 Command Word Two.............................................................................................7-2
7.1.4 Data Pointer............................................................................................................7-3
7.1.5 Status Word One ....................................................................................................7-3
7.1.6 Status Word Two....................................................................................................7-3
7.1.7 Tail Pointer.............................................................................................................7-3
7.2 Initializing Data Buffers............................................................................................................7-3
7.3 Loading Bus Monitor Registers ................................................................................................7-3
7.3.1 Bus Monitor Control Register (14).........................................................................7-3
7.3.2 Bus Monitor Terminal Address Select Registers (16 and 17).................................7-3
7.3.3 Interrupt Queue Pointer Register (06) ....................................................................7-4
7.3.4 Next Message Record Block Register (02) ............................................................7-4
7.3.5 Control Register (00)..............................................................................................7-4
7.3.6 High Priority Interrupt Register (07) and Standard Interrupt Register (09)……...7-4
7.3.7 Reset Timer Register (13) ......................................................................................7-4
7.3.8 Remote Terminal Address Register (10) ................................................................7-4
7.4 Collecting Data .........................................................................................................................7-4
7.5 Post-Run Processing .................................................................................................................7-4
8. INDEX...........................................................................................................................................................1
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Copyright 2004 iv DTI-VME/S

1.OVERVIEW
The DTI-VME/S is an intelligent interface between a VME host and a MIL-STD 1553B data
bus. Designed for high performance environments with multiple host applications, the DTI-
VME/S enables the VME host to operate in real time as a MIL-STD 1553B Bus Controller
(BC, Remote Terminal (RT) or Bus Monitor (BM).
The VME host processor and DTI-VME/S communicate via a flexible, programmable
interrupt structure, internal registers, and a definable dual-port RAM. A wide range of
software programmable registers deliver the features and capabilities that provide flexibility
and ease of use for complete MIL-STD 1553B system control, emulation, analysis and data
reporting.
The DTI-VME/S is available in both single and dual channel configurations. The dual
channel option allows a second independent MIL-STD 1553B channel interface on a single
VME board.
1.1 Enhanced Intelligence
The high performance architecture of the DTI-VME/S allows distributed processing
solutions: BC-to-RT, RT-to-BC and RT-to-RT instructions, mode code, broadcast mode and
broadcast. For applications requiring a high degree of host processing, the following
functions may be incorporated without host intervention:
• Interrupt Lists
• Multiple Message Processing
• Automatic Polling
• Variable Memory Space Allocation
• Selectable Data Storage
• Indexing
This architecture is also effective when multiple DTI-VME/Ss are controlled by the same
VME host. Environments requiring multiple boards under single-host control include:
• Interfaces to multiple MIL-STD 1553B data buses.
• Emulation of multiple data buses.
1.2 Highly Flexible Configuration
To meet a wide range of systems requirements, the DTI-VME/S allows the user to define the
size of the dual-port RAM (16K, 32K, 48K, or 64K words) and the starting address of the
memory block. With the DTI-VME/S, the user can enable and disable up to four channels by
specifying a different starting address for each board.
The unique interface features provide the flexibility for changing system load requirements
and also provide the options for effective deployment of multiple DTI-VME/Ss within the
same VME host.
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OVERVIEW
1.3 Enhanced Bus Connection Capability
Internal and external termination, transformer or direct coupling, and connected or isolated
buses are supported by the DTI-VME/S. Bus connection is enabled via a software-accessible
control register (Bus Connection Relay Control Register).
1.4 DTI-VME/S Onboard Dual-Port RAM
The DTI-VME/S provides up to 64K words of dual-port RAM for maximum processing
throughput. The highly flexible RAM area allows you to alter the size of the RAM to
enhance data handling, alter the configuration to meet specific requirements and change the
starting location of the dual-port RAM to provide more effective application compatibility.
These options are enabled via Configuration Registers 26, 27 and 28. (See Getting Started
for details.)
The dual-port RAM is accessible directly from the VME bus or from the DTI-VME/S. All
accesses to the dual-port RAM must be in 16-bit word transfers.
1.5 Remote Terminal Mode
The RT mode provides the capability of emulating an RT, with up to 31 data subaddresses
and one or two mode subaddresses. (Subaddress 31 is selectable.) The DTI-VME/S responds
to bus instructions in real-time, easily handling the traffic of a 100 percent loaded bus.
Using the 64K-word dual-port RAM, the DTI-VME/S receives, stores, time tags and counts
over 2,000 32-data word transfers. Bus messages are transmitted and received without host
intervention. As each valid bus message is received, an RT index counts the number if
storage buffers. If the buffers for a particular subaddress are full, only the last message buffer
is overwritten.
Other RT features include:
• Generating an interrupt when addressed
• Providing a 64 microsecond resolution time tag for each stored message
• Detecting message errors
• Enabling specific subaddress/mode codes
1.6 Bus Controller Mode
The BC mode provides the capability of defining, storing and implementing multiple lists of
bus instructions. Controlled by the application, Crutiss-Wright’s inter-message timing allows
the BC to emulate the instruction set and bus command timing without host intervention.
The instructions allow the specification of an inter-message timer to delay the
implementation of the subsequent instructions.
The DTI-VME/S addresses up to 32 RTs, with up to 32 subaddresses each. Each Command
Block instruction, size of the instruction and method of implementation is definable.
The DTI-VME/S BC is also capable of:
• Monitoring data during RT-to-RT transfers.
• Controlling the bus retry option;, which allows the BC to re-send bus instructions on
the same or opposite bus up to four times.
• Polling RT status.
Copyright 2004 1-2 DTI-VME/S

OVERVIEW
• Setting the inter-message timer.
• Initiating mode broadcast or broadcast mode commands.
• Detecting protocol and bus errors;
• Implementing RT 31; as a broadcast RT; or a normal RT.
1.7 Bus Monitor Mode
The BM mode monitors one, any combination or up to 32 RTs. Software programmable
registers determine the number and address of the RT to monitor. (See the Registers section
of this manual.) Using the registers and command structures, the DTI-VME/S processes a
series of monitored messages without host intervention. The BM also detects response time
out, long and short word count, bit count, Manchester II and parity errors.
1.8 Interrupt Handling
The DTI-VME/S defines MIL-STD 1553B events as a high priority interrupt, standard
priority interrupt or no interrupt. High priority interrupts are recorded in registers and are
typically handled upon occurrence. (See the Registers section of this manual.)
Standard priority interrupts are queued and handled via application requirements. The host
can periodically or continuously monitor the number of standard priority interrupts queued.
The standard priority interrupt queue is initialized by the host and consists of a first-in/first-
out queue of enabled interrupt events. The standard priority interrupt queue holds up to 255
packets (or entries) in contiguous or non-contiguous memory. (See the Interrupts section of
this manual.)
1.9 Theory of Operation
Interface Memory
1553
Control
Processor 1553
VME
Backplane
DTI-VME/S
Figure 1-1. DTI-VME/S Theory of Operation
The DTI-VME/S interface mechanism is responsible for two key functions of DTI-VME/S
board operation. The interface orders the access to the onboard dual-port RAM by
implementing the VME interface logic and is responsible for arbitration of memory between
the onboard processor and the VME host. The interface also allows the VME host to
program the Operational Registers on the processor and also contains the Configuration
Registers.
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OVERVIEW
The onboard processor provides the interface to the MIL-STD-1553 bus by emulating a BC,
RT or BM. This processor also contains the Operational Registers.
The 1553 logic contains the transceiver, transformers, and relays. The relays isolate or
connect the 1553 bus, select transformer or direct coupled connection to the bus or
terminates the bus.
1.10 Specifications
Table 1-1 provides a list of specifications for the DTI-VME/S.
Specifications
Memory: 64K words of dual-port RAM
Word size: 16 bits
Communication: MIL-STD 1553B protocol dual redundant bus
Interface to bus: Transformer or direct coupling
Voltage: + 5.0V +/- 5%, +12.0V + 5%, -12.0V + 5%
Current Drain: 2.3 amperes (maximum - single channel) 3.3
amperes(maximum - dual channel)
Temperature range:
Operating:
Storage:
0 to 70 degrees Celsius
-55 to 125 degrees Celsius
Relative humidity: 10% to 90%, non-condensing
Processor clock speed: 12 megahertz (MHz)
DTI-VME/S board size: 6.299 inches by 9.187 inches
160 mm by 233.35 mm
Minimum Inter-Message Gap
Time (BC mode)
15-22µs
Minimum Inter-Message Gap
Time (RT mode)
4 µs
Minimum Inter-Message Gap
Time (BM mode)
4 µs
Table 1-1 DTI-VME/S Specifications
Copyright 2004 1-4 DTI-VME/S

OVERVIEW
1.11 Quality Assurance
Curtiss-Wright Controls’ policy is to provide our customers with the highest quality products
and services. In addition to the physical product, the company provides documentation, sales
and marketing support, hardware and software technical support, and timely product
delivery. Our quality commitment begins with product concept, and continues after receipt
of the purchased product.
Curtiss-Wright Controls’ Quality System conforms to the ISO 9001 international standard
for quality systems. ISO 9001 is the model for quality assurance in design, development,
production, installation, and servicing. The ISO 9001 standard addresses all 20 clauses of the
ISO quality system, and is the most comprehensive of the conformance standards.
Our Quality System addresses the following basic objectives:
• Achieve, maintain, and continually improve the quality of our products through
established design, test, and production procedures.
• Improve the quality of our operations to meet the needs of our customers, suppliers,
and other stakeholders.
• Provide our employees with the tools and overall work environment to fulfill,
maintain, and improve product and service quality.
• Ensure our customer and other stakeholders that only the highest quality product or
service will be delivered.
The British Standards Institution (BSI), the world’s largest and most respected
standardization authority, assessed Curtiss-Wright Controls’ Quality System. BSI’s Quality
Assurance division certified we meet or exceed all applicable international standards, and
issued Certificate of Registration, number FM 31468, on May 16, 1995. The scope of
Curtiss-Wright Controls’ registration is: “Design, manufacture and service of high
technology hardware and software computer communications products.” The registration is
maintained under BSI QA’s bi-annual quality audit program.
Customer feedback is integral to our quality and reliability program. We encourage
customers to contact us with questions, suggestions, or comments regarding any of our
products or services. We guarantee professional and quick responses to your questions,
comments, or problems.
1.12 Technical Support
Technical documentation is provided with all of our products. This documentation describes
the technology, its performance characteristics, and includes some typical applications. It
also includes comprehensive support information, designed to answer any technical
questions that might arise concerning the use of this product. We also publish and distribute
technical briefs and application notes that cover a wide assortment of topics. Although we try
to tailor the applications to real scenarios, not all possible circumstances are covered.
Although we have attempted to make this document comprehensive, you may have specific
problems or issues this document does not satisfactorily cover. Our goal is to offer a
combination of products and services that provide complete, easy-to-use solutions for your
application.
Copyright 2004 1-5 DTI-VME/S

OVERVIEW
If you have any technical or non-technical questions or comments, contact us. Hours of
operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time.
• Phone: [phone] or [phone]
• E-mail: [email protected]
• Fax: [phone]
• World Wide Web address: www.systran.com
1.13 Ordering Process
To learn more about Curtiss-Wright Controls’ products or to place an order, please use the
following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern
Standard/Daylight Time.
• Phone: [phone] or [phone]
• E-mail: [email protected]
• World Wide Web address: www.systran.com
Copyright 2004 1-6 DTI-VME/S

2.GETTING STARTED
2.1 Step 1. Unpacking and Examining the Board
Remove the hardware board from the packing box (Figure 2-1).
NOTE: The board is shipped in a protective anti-static bag. Do not remove the board from
the protective bag until grounded.
Once grounded, remove the board from the protective bag and place the board on the bag or
any electrostatically-controlled surface.
RSW3 RSW2 RSW1
SYSTRAN Corporation
JP2
Figure 2-1. DTI-VME/S Board
Examine the board. If the board appears to be damaged, contact Curtiss-Wright Controls
immediately.
Copyright 2004 2-1 DTI-VME/S

GETTING STARTED
2.2 Step 2. Selecting The I/O Base Address
Use Rotary Switches RS1, RS2 and RS3, located on the front panel, to select the I/O base
address. RS1 represents the most significant digit. For example, if RS1 = 6, RS2 = A, and
Figure 2-2. Example I/O Addre
RS3 = 0, the I/O base address is 6A0H (Figure 2-2).
ss Switch Settings
2.3 Step 3. Installing The Board
sed slots between
mper to the
0
F
E
1
2
4
5
6
7
8
9
A
B
C
D
3
0
F
E
1
2
4
5
6
7
8
9
A
B
C
D
3
0
F
E
1
2
4
5
6
7
8
9
A
B
C
D
3
RSW3 RSW2 RSW2
0A6
RSW1 RSW2
RSW3
6A 0
Caution: Install the DTI-VME/S with power off.
1. Locate an available slot in the host computer.
2. Jumper the daisy-chained signal IACKIN*-IACKOUT* on all unu
board is inserted in Slot 2 shown in Figure 2-3, the IACK ju
Empty
Slot
Slot 1 Slot 2 Slot 3
DTI-VME
Empty
Slot
IACK
Jumper
Installed
IACK
Jumper
Installed
Inserted
in Slot 2
the CPU and the DTI-VME/S, enabling the interrupt signal to be properly passed
from the host. Remove the IACK jumper from the slot before inserting the DTI-
VME/S.
Example
If the
right of Slot 2 must be removed. If Slot 1 and Slot 3 are empty, the IACK jumpers
must be installed.
Figure 2-3. IACK Jumpers
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GETTING STARTED
3. Jumper 2, located in the lower left corner of the board (Figure 2-1), enables the Bus
Grant Signals. Insert this jumper to pass the Bus-Grant signal through each slot.
Note: Bus Grant Signals (BGX) do not affect DTI-VME/S operation.
.The position of the bus grant jumper is not relevant for the DTI-VME/S
. Seat the DTI-VME/S card into the chosen slot and push firmly on the insert/ejector
four-pin,
een an RT and the
4
handles at both ends of the front panel. Lock the board into place by screwing in the
lock downs on both ends of the front panel.
2.4 Step 4. Interconnection to DTI-VME/S Boards or RTs
Two optional external ports, located on the DTI-VME/S front panel, each contain a
male-type MTA miniature connector (Figure 2-4). This connector provides the options of:
• Connecting multiple DTI-VME/Ss within one VME host.
• Connecting the DTI-VME/S to an RT (for interaction betw
DTI-VME/S).
CHANNEL 1
EXT 1
CHANNEL 2
EXT 2
Pin 1 - Output
Pin 2 - Input
Pin 4 - Ground
Pin 3 - Input
Pin 1 - Output
Pin 2 - Input
Pin 4 - Ground
Pin 3 - Input
P6 P5B
A
B
A
B
INV
IMP
BUS
ERR
SYSTRAN Corporation
51 52 53
Figure 2-4. The DTI-VME/S External Ports
he TTL level signals for the external port follow:
2.4.1 Pin 1 Command Strobe (Output)
ving a valid 1553B command and deactivates the
2.4.2 Pin 2 Subsystem Fail (Input)
stem Fail Bit in Register 01 to be set. An interrupt can
2.4.3 Pin 3 External Override (Input)
and strobe. Pin 3 can also be used for multi-
The
T
The DTI-VME/S activates Pin 1 after recei
pin after servicing the command.
When Pin 2 is set, it causes the Subsy
then be enabled, notifying the host. Pin 2 detects a test hardware failure, such as a failure of
the 1553B test equipment.
Pin 3 is used for Input from the RT comm
redundant applications. Upon receiving the Pin 3 signal, all current activity is aborted.
pin may be connected to the RT command strobe Output of an adjacent DTI-VME/S when
used.
Copyright 2004 2-3 DTI-VME/S

GETTING STARTED
2.4.4 Pin 4 Ground
Pin 4 can be used for grounding connections.
2.5 Step 5. Connecting To The MIL-STD-1553 P2 Backplane
The DTI-VME/S is available with the optional P2 backplane 1553 bus connections.
Backplane connections are a factory configured option and do not exist on standard front
panel connection boards. Boards that utilize the backplane connection option do not have
the front panel mini twinax-triax connectors. Table 2-1 provides P2 connector wiring.
Channel 1
Bus A+ P2 pin A5
Bus A- P2 pin C5
Bus B+ P2 pin A10
Bus B- P2 pin C10
Channel 2
Bus A+ P2 pin A6
Bus A- P2 pin C6
Bus B+ P2 pin A9
Bus B- P2 pin C9
Table 2-1. MIL-STD-1553 P2 Backplane Connections
Shielded connections use the following P2 connector ground pins:
B2
B12
B22
B31
2.6 Step 6. Setting The Configuration Registers
The operational programmable registers replace hardware programmable switches and
jumpers. The I/O base address is the only hardware-programmable option the user must
select. (See Step 2.)
The bits in the programmable registers are set to their default values when the system is
powered up or a system hardware reset is performed. The software reset performed by
reading Register 18 does not affect the register settings. Existing configurations are
maintained when a software reset is performed.
The configuration registers must be programmed to meet the user system requirements
before the DTI-VME/S is operational. The operation of these registers is described in the
following sections. This information, combined with the definitions in the Registers section,
provides the information required to write low-level software drivers for a VME host
computer.
The register numbers are relative to the base register address of the board. For the optional
dual channel board, the register set of the second channel is offset by 32 (0x20) from the
Copyright 2004 2-4 DTI-VME/S

GETTING STARTED
base register address of the first channel. The base register address of the first channel is
selected by setting switches RS1, RS2 and RS3. (See Step 2.)
NOTE: For a dual channel board, the configuration registers for both channels must be
programmed to operate correctly. Programming only the configuration registers of one
channel on a dual channel board may cause unpredictable results.
2.6.1 Register 25: Bus Connection Relay Control
Three bits in this register control relays that isolate the DTI-VME/S from the 1553 bus for
self-test, connect an internal termination resistor to the DTI-VME/S and select a direct or
transformer coupled connection to the bus. These selections are typically configured once
for a particular test setup. An additional bit in this register allows the machine controlling
the bit test pattern to output data continuously for diagnostic purposes.
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOP T/D
CPL
INTRM ISO
BUS
X X X X X X X X X X X X 1/0 1/0 1/0 1/0
Reserved
Bits 15-4 Reserved.
Bit 3 LOOP - Single/Continuous Loop Test.
This bit determines operation of a function that is controlled by writing to Register 18.
When a 1 is written to Bit 0 position of Register 18, a built-in test state machine pattern
generator sends a 1553 bus encoded message. The selection of one of two messages,
whether Bus A or B is used, and transmitter enabling is also done using bits in Register 18.
If this bit is set to 0, the test pattern is generated once for each write to Register 18. If this
bit is set to 1, one write to Register 18 enables a continuous output of the test pattern on the
bus at a very high rate. This output rate is useful for technician troubleshooting and is not
typically used in normal operations.
0 = Single test pattern output.
1 = Continuous looping test pattern output.
0 = Default.
Bit 2 T/D CPL - Transformer/Direct Coupling.
This relay can connect the DTI-VME/S to the 1553 bus in a direct or transformer coupled
configuration. Use direct coupling if the distance between the DTI-VME/S and the 1553 bus
measures 12 inches or less. Use transformer coupling if the distance between the DTI-
VME/S and the 1553 bus exceeds 12 inches, but not 20 feet. Direct coupling is applied
during the isolated internal self-test at powerup. After the self-test concludes, the bit is set
according to UUT connection requirements. The selected connection applies to Buses A and
B.
0 = Transformer coupling selected.
1 = Direct coupling selected.
1 = Default.
Bit 1 INTRM - Internal Termination.
Copyright 2004 2-5 DTI-VME/S

GETTING STARTED
This relay connects a termination resistor, required when using the direct coupling. The
resistor is applied during the isolated internal self-test at powerup to provide a test load.
After the self-test concludes, the bit is set per UUT connection requirements. The selected
connection applies to Buses A and B.
0 = No termination connected.
1 = Internal termination connected.
1 = Default.
Bit 0 ISOBUS - Isolate Bus.
This relay can isolate the DTI-VME/S from the 1553 bus. To isolate the DTI-VME/S from
the 1553 bus, set the bit to 1 (the default value). When the bit is set to 0, the DTI-VME/S is
connected to the 1553 bus. This relay is typically used only for powerup self-test of the
DTI-VME/S board and doesn’t require disconnecting the board from any UUT. After a
successful powerup self-test, the bit is usually set to 0. The selected connection applies to
both Buses A and B.
0 = Connected to 1553 bus.
1 = Isolated from 1553 bus.
1 = Default.
NOTE: For the DTI-VME/S to operate on a 1553 bus, this value must be changed to 0.
2.6.2 Register 26: Memory Size/Start Address/Bank Select
The least significant six bits of this register are used to select the dual-port RAM size, offset
the start address of the selected amount of dual-port RAM, and select the bank of onboard
RAM to be used for dual-port operation. The DTI-VME/S can address 64K words of
memory; therefore, this is the maximum size of space that can be allotted in the VME
memory address space. However, the user has the option of selecting smaller dual-port
memory sizes. Since the VME address structure is set up for byte addresses, the dual-port
RAM in the VME address space is 32 KB, 64 KB, or 128 KB.
NOTE: All accesses to the operational registers, the configuration registers or the dual-
port RAM from the VME host must be word transfers. Byte transfers does not cause bus
errors, but does cause unpredictable results.
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS
ERR
X X X X X X X X X X X X 1/0 1/0 1/0 1/0
RAM
SIZE
MEMORY
BANKING
RAM
ADDRESS
OFFSET
Reserved
Registers 27 and 28 are used to select the base memory address on 128 KB module
boundaries. The dual-port RAM size and start address bits of Register 26 are used to select
decoding locations for smaller increments of memory within the 128 KB space. Selecting
other address locations for smaller increments of memory is useful when several boards with
Copyright 2004 2-6 DTI-VME/S