Cypress Semiconductor MoBL CY62126EV30 User manual

MoBL®,CY62126EV30
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05486 Rev. *E Revised January 5, 2009
Features
■High speed: 45 ns
■Temperature ranges
❐Industrial: –40°C to +85°C
❐Automotive: –40°C to +125°C
■Wide voltage range: 2.2V to 3.6V
■Pin compatible with CY62126DV30
■Ultra low standby power
❐Typical standby current: 1 μA
❐Maximum standby current: 4 μA
■Ultra low active power
❐Typical active current: 1.3 mA at f = 1 MHz
■Easy memory expansion with CE and OE features
■Automatic power down when deselected
■CMOS for optimum speed and power
■Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits[1]. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (IO0through IO15) are placed in a high impedance
state when:
■Deselected (CE HIGH)
■Outputs are disabled (OE HIGH)
■Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0through IO7) is written into the location
specified on the address pins (A0through A15). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8through IO15)
is written into the location specified on the address pins (A0
through A15).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Logic Block Diagram
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Document #: 38-05486 Rev. *E Page 2 of 13
Pin Configurations
Figure 1. 44-Ball VFBGA (Top View) Figure 2. 44-Pin TSOP II (Top View)[2]
Table 1. Product Portfolio
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (μA)
f = 1 MHz f = fmax
Min Typ[3] Max Typ[3] Max Typ[3] Max Typ[3] Max
CY62126EV30LL Industrial 2.2 3.0 3.6 45 1.3 2 11 16 1 4
CY62126EV30LL Automotive 2.2 3.0 3.6 55 1.3 4 11 35 1 30
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Document #: 38-05486 Rev. *E Page 3 of 13
Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground
Potential................................. –0.3V to 3.6V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State[4, 5] ................–0.3V to 3.6V (VCCmax + 0.3V)
DC Input Voltage[4, 5] ...............−0.3V to 3.6V (VCCmax + 0.3V)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62126EV30LL Industrial –40°C to +85°C 2.2V to
3.6V
Automotive –40°C to +125°C
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions 45 ns (Industrial) 55 ns (Automotive) Unit
Min Typ[1] Max Min Typ[1] Max
VOH Output HIGH Voltage IOH = –0.1 mA 2.0 2.0 V
IOH = –1.0 mA, VCC >2.70V 2.4 2.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.4 0.4 V
IOL = 2.1mA, VCC >2.70V 0.4 0.4 V
VIH Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3 1.8 VCC + 0.3 V
VCC = 2.7V to 3.6V 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW
Voltage VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V
VCC = 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V
IIX Input Leakage Current GND < VI< VCC –1 +1 –4 +4 μA
IOZ Output Leakage
Current GND < VO <VCC, Output Disabled –1 +1 –4 +4 μA
ICC VCC Operating Supply
Current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
11 16 11 35 mA
f = 1 MHz 1.3 2.0 1.3 4.0
ISB1 Automatic CE Power
down Current
—CMOS Inputs
CE > VCC − 0.2V,
VIN >VCC – 0.2V, VIN <0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
14 135μA
ISB2 [7] Automatic CE Power
down Current
—CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
14 130μA
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT Output Capacitance 10 pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 μs ramp time from 0 to Vcc(min) and 200 μs wait time after Vcc stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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Document #: 38-05486 Rev. *E Page 4 of 13
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions VFBGA
Package
TSOP II
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
two-layer printed circuit board
58.85 28.2 °C/W
ΘJC Thermal Resistance
(Junction to Case)
17.01 3.4 °C/W
Figure 3. AC Test Loads and Waveforms
Parameters 2.2V - 2.7V 2.7V - 3.6V Unit
R1 16600 1103 Ohms
R2 15400 1554 Ohms
RTH 8000 645 Ohms
VTH 1.2 1.75 Volts
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ[1] Max Unit
VDR VCC for Data Retention 1.5 V
ICCDR[7] Data Retention Current VCC= VDR, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Industrial 3 μA
Automotive 30 μA
tCDR[8] Chip Deselect to Data
Retention Time 0ns
tR[9] Operation Recovery Time tRC ns
Figure 4. Data Retention Waveform
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT VTH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
VCC(min)
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC
CE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 μs.
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Document #: 38-05486 Rev. *E Page 5 of 13
Switching Characteristics
Over the Operating Range [10, 11]
Parameter Description 45 ns (Industrial) 55 ns (Automotive) Unit
Min Max Min Max
Read Cycle
tRC Read Cycle Time 45 55 ns
tAA Address to Data Valid 45 55 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 45 55 ns
tDOE OE LOW to Data Valid 22 25 ns
tLZOE OE LOW to Low Z [12] 55 ns
tHZOE OE HIGH to High Z [12, 13] 18 20 ns
tLZCE CE LOW to Low Z [12] 10 10 ns
tHZCE CE HIGH to High Z [12, 13] 18 20 ns
tPU CE LOW to Power Up 0 0 ns
tPD CE HIGH to Power Down 45 55 ns
tDBE BHE / BLE LOW to Data Valid 22 25 ns
tLZBE BHE / BLE LOW to Low Z [12] 55 ns
tHZBE BHE / BLE HIGH to High Z [12, 13] 18 20 ns
Write Cycle [14]
tWC Write Cycle Time 45 55 ns
tSCE CE LOW to Write End 35 40 ns
tAW Address Setup to Write End 35 40 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup to Write Start 0 0 ns
tPWE WE Pulse Width 35 40 ns
tBW BHE / BLE Pulse Width 35 40 ns
tSD Data Setup to Write End 25 25 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z [12, 13] 18 20 ns
tLZWE WE HIGH to Low Z [12] 10 10 ns
Notes
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
12. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of
these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
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Document #: 38-05486 Rev. *E Page 6 of 13
Switching Waveforms
Figure 5. Read Cycle No. 1(Address transition controlled)[15, 16]
Figure 6. Read Cycle No. 2 (OE controlled)[16, 17]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGHIMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
15. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE and BHE, BLE transition LOW.
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Document #: 38-05486 Rev. *E Page 7 of 13
Figure 7. Write Cycle No. 1 (WE controlled)[14, 18, 19]
Figure 8. Write Cycle No. 2 (CE controlled)[14, 18, 19]
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tWC
tHZOE
DATAIN
NOTE 20
tBW
tSCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 20
Notes
18. Data IO is high impedance if OE = VIH.
19. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
20. During this period, the IOs are in output state. Do not apply input signals.
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Document #: 38-05486 Rev. *E Page 8 of 13
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [19]
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)[19]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
tBW
NOTE 20
CE
ADDRESS
WE
DATA IO
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 20
DATA IO
ADDRESS
CE
WE
BHE/BLE
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Document #: 38-05486 Rev. *E Page 9 of 13
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power Down Standby (ISB)
L X X H H High Z Output Disabled Active (ICC)
LHLLLDataOut(IO
0–IO15) Read Active (ICC)
LHLHLDataOut(IO
0–IO7);
IO8–IO15 in High Z
Read Active (ICC)
LHLLHDataOut(IO
8–IO15);
IO0–IO7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (IO0–IO15) Write Active (ICC)
L L X H L Data In (IO0–IO7);
IO8–IO15 in High Z
Write Active (ICC)
L L X L H Data In (IO8–IO15);
IO0–IO7 in High Z
Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating Range
45 CY62126EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial
CY62126EV30LL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free)
55 CY62126EV30LL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Automotive
CY62126EV30LL-55ZSXE 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of other parts.
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Document #: 38-05486 Rev. *E Page 10 of 13
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150)
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
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Document #: 38-05486 Rev. *E Page 11 of 13
Figure 12. 44-Pin TSOP II (51-85087)
Package Diagrams (continued)
51-85087-*A
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Document #: 38-05486 Rev. *E Page 12 of 13
Document History Page
Document Title: MoBL®CY62126EV30, 1-Mbit (64K x 16) Static RAM
Document Number: 38-05486
Rev. ECN No. Submission
Date
Orig. of
Change Description of Change
** 202760 See ECN AJU New data sheet
*A 300835 See ECN SYT Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA Package
and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins, respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35- and
45-ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns speed
bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins respec-
tively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed bins
respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip can
be deselected by either disabling the chip enable signals or by disabling both BHE
and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B 461631 See ECN NXR Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Changed ISB1,ISB2 (max) from 1 μA to 4 μA
Changed ISB1,ISB2 (Typ) from 0.5 μA to 1 μA
Changed ICCDR (max) from 1.5 μA to 3 μA
Changed the AC Test load Capacitance value from 50 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tLZBE from 6 to 5 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information table.
*C 925501 See ECN VKN Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
*D 1045260 See ECN VKN Added Automotive information
Updated Ordering Information table
*E 2631771 01/07/09 NXR/PYRS Changed CE condition from X to L in Truth table for Output Disable mode
Updated template
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Document #: 38-05486 Rev. *E Revised January 5, 2009 Page 13 of 13
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
MoBL®, CY62126EV30
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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