Cypress Semiconductor CY7C130 User manual

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document #: 38-06002 Rev. *E Revised December 09, 2008
Features
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■ 1K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: I
CC
= 110 mA (maximum)
■ Fully asynchronous operation
■ Automatic power down
■ Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
■ BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
■ INT flag for port-to-port communication
■ Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
■ Pb-free packages available
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140
[1]
and CY7C141
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi-
processor designs.
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen-
dently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
R/W
L
BUSY
L
CE
L
OE
L
A
9L
A
0L
A
0R
A
9R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
BUSY
R
INT
L
INT
R
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
CONTROL
I/O CONTROL
I/O
MEMORY
ARRAY ADDRESS
DECODER
ADDRESS
DECODER
[2]
[3] [3]
Logic Block Diagram
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 2 of 19
Pin Configurations
Figure 1. Pin Diagram - DIP (Top View)
Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View)
13
14
15
16
17
18
19
20
21
22
23 26
27
28
32
31
30
29
33
36
35
34
24 25
GND
1
2
3
4
5
6
7
8
9
10
11 38
39
40
44
43
42
41
45
48
47
46
12 37
R/W
L
CE
L
BUSY
L
INT
L
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
CE
R
R/W
R
BUSY
R
INT
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
V
CC
7C130
7C140
1
VCC
OE
R
A
0R
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
4L 5L 6L 7L
0R 1R 2R 3R 4R 5R 6R
NC
GND
OE
BUSY
INT
A
NC
R/W
CE R/W
BUSY
INT
NC
0L
L
L
L
L
L
CER
R
R R
7C131
7C141
46
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
1415 16 17 18 19 20 21 22 23 24 25 26
52 5150 49 48 47 45 44 43 42 41 40
VCC OE
BUSY
INT
A
NC
R/W
CE R/W
BUSY
INT
NC
0L
L
L
L
L
L
CER
R
R R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
4L 5L 6L 7L
0R 1R 2R 3R 4R 5R 6R
NC
GND
7C131
7C141
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 3 of 19
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
–A
11/12L
A
0R
–A
11/12R
Address
I/O
0L
–I/O
15/17L
I/O
0R
–I/O
15/17R
Data Bus Input/Output
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
V
CC
Power
GND Ground
Selection Guide
Parameter 7C131-15
[4]
7C131A-15
7C141-15 7C131-25
[4]
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55 Unit
Maximum Access Time 15 25 30 35 45 55 ns
Maximum Operating
Current Com’l/Ind 190 170 170 120 120 110 mA
Maximum Standby
Current Com’l/Ind 75 65 65 45 45 35 mA
Shaded areas contain preliminary information.
Note
4. 15 and 25 ns version available only in PLCC/PQFP packages.
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 4 of 19
Maximum Ratings
[5]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150
° C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)............................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–3.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0 ° C to +70 ° C 5V ± 10%
Industrial –40 ° C to +85 ° C 5V ± 10%
Military
[6]
–55 ° C to +125 ° C 5V ± 10%
Electrical Characteristics Over the Operating Range
[7]
Parameter Description Test Conditions
7C131-15
[4]
7C131A-15
7C141-15
7C130-30
[4]
7C130A-30
7C131-25,30
7C140-30
7C141-25,30
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
7C130-55
7C131-55
7C140-55
7C141-55 Unit
Min Max Min Max Min Max Min Max
V
OH
Output HIGH Voltage V
CC
= Min, I
OH
= –4.0 mA 2.4 2.4 2.4 2.4 V
V
OL
Output LOW Voltage I
OL
= 4.0 mA 0.4 0.4 0.4 0.4 V
I
OL
= 16.0 mA
[8]
0.5 0.5 0.5 0.5
V
IH
Input HIGH Voltage 2.2 2.2 2.2 2.2 V
V
IL
Input LOW Voltage 0.8 0.8 0.8 0.8 V
I
IX
Input Leakage Current GND < V
I
< V
CC
–5 +5 –5 +5 –5 +5 –5 +5 μA
I
OZ
Output Leakage
Current GND < V
O
<V
CC
,
Output Disabled –5 +5 –5 +5 –5 +5 –5 +5 μA
I
OS
Output Short
Circuit Current
[9, 10]
V
CC
= Max,
V
OUT
= GND –350 –350 –350 –350 mA
I
CC
V
CC
Operating
Supply Current CE = V
IL
,
Outputs Open, f = f
MAX[11]
Com’l 190 170 120 110 mA
I
SB1
Standby Current
Both Ports, TTL Inputs CE
L
and CE
R
> V
IH
,
f = f
MAX[11]
Com’l 75 65 45 35 mA
I
SB2
Standby Current
One Port,
TTL Inputs
CE
L
or CE
R
> V
IH
,
Active Port Outputs Open
f = f
MAX[11]
Com’l 135 115 90 75 mA
I
SB3
Standby Current
Both Ports,
CMOS Inputs
BothPortsCE
L
and CE
R
>
V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
Com’l 15 15 15 15 mA
I
SB4
Standby Current
One Port,
CMOS Inputs
One Port CE
L
or
CE
R
>V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V,
ActivePortOutputsOpen,f=
f
MAX[11]
Com’l 125 105 85 70 mA
Shaded areas contain preliminary information.
Notes
5. The voltage on any input or I/O pin cannot exceed the power pin during power up.
6. T
A
is the “instant on” case temperature
7. See the last page of this specification for Group A subgroup testing information.
8. BUSYand INT pins only.
9. Duration of the short circuit should not exceed 30 seconds.
10.This parameter is guaranteed but not tested.
11. At f = f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
RC
and using AC Test Waveforms input levels of GND to 3V.
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 5 of 19
Capacitance
[10]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V 15 pF
C
OUT
Output Capacitance 10 pF
Figure 4. AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 893Ω
R2
347Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND 90% 90%
10%
≤5ns ≤5ns
5V
OUTPUT
R1 893Ω
R2
347Ω
5pF
INCLUDING
JIGAND
SCOPE
(a) (b)
OUTPUT 1.40V
Equivalent to: THÉVENIN EQUIVALENT
5V
281Ω
30
pF
BUSY
OR
INT
BUSY Output Load
(CY7C130/CY7C131 ONLY)
10%
ALL INPUT PULSES
250Ω
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 6 of 19
Switching Characteristics Over the Operating Range
[7, 12]
Parameter Description
7C131-15
[4]
7C131A-15
7C141-15
7C130-25
[4]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30 Unit
Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 15 25 30 ns
t
AA
Address to Data Valid
[13]
15 25 30 ns
t
OHA
Data Hold from Address Change 000ns
t
ACE
CE LOW to Data Valid
[13]
15 25 30 ns
t
DOE
OE LOW to Data Valid
[13]
10 15 20 ns
t
LZOE
OE LOW to Low Z
[10, 14, 15]
333ns
t
HZOE
OE HIGH to High Z
[10, 14, 15]
10 15 15 ns
t
LZCE
CE LOW to Low Z
[10, 14, 15]
355ns
t
HZCE
CE HIGH to High Z
[10, 14, 15]
10 15 15 ns
t
PU
CE LOW to Power Up
[10]
000ns
t
PD
CE HIGH to Power Down
[10]
15 25 25 ns
Write Cycle
[16]
t
WC
Write Cycle Time 15 25 30 ns
t
SCE
CE LOW to Write End 12 20 25 ns
t
AW
Address Setup to Write End 12 20 25 ns
t
HA
Address Hold from Write End 222ns
t
SA
Address Setup to Write Start 000ns
t
PWE
R/WPulse Width 12 15 25 ns
t
SD
Data Setup to Write End 10 15 15 ns
t
HD
Data Hold from Write End 000ns
t
HZWE
R/WLOW to High Z
[15]
10 15 15 ns
t
LZWE
R/WHIGH to Low Z
[15]
000ns
Shaded areas contain preliminary information.
Notes
12.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30 pF load capacitance.
13.AC Test Conditions use V
OH
= 1.6V and V
OL
= 1.4V.
14.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
15.t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part(b) of AC Test Loads.Transition is measured ±500 mV from steady state voltage.
16.The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 7 of 19
Busy/Interrupt Timing
t
BLA
BUSY LOW from Address Match 15 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch
[17]
15 20 20 ns
t
BLC
BUSY LOW from CE LOW 15 20 20 ns
t
BHC
BUSY HIGH from CE HIGH
[17]
15 20 20 ns
t
PS
Port Set Up for Priority 555ns
t
WB[18]
R/WLOW after BUSY LOW 000ns
t
WH
R/WHIGH after BUSY HIGH 13 20 30 ns
t
BDD
BUSY HIGH to Valid Data 15 25 30 ns
t
DDD
Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns
t
WDD
Write Pulse to Data Delay Note 19 Note 19 Note 19 ns
Interrupt Timing
t
WINS
R/Wto INTERRUPT Set Time 15 25 25 ns
t
EINS
CE to INTERRUPT Set Time 15 25 25 ns
t
INS
Address to INTERRUPT Set Time 15 25 25 ns
t
OINR
OE to INTERRUPT Reset Time
[17]
15 25 25 ns
t
EINR
CE to INTERRUPT Reset Time
[17]
15 25 25 ns
t
INR
Address to INTERRUPT Reset Time
[17]
15 25 25 ns
Shaded areas contain preliminary information.
Switching Characteristics Over the Operating Range
[7, 12]
(continued)
Parameter Description
7C131-15
[4]
7C131A-15
7C141-15
7C130-25
[4]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30 Unit
Min Max Min Max Min Max
Notes
17.These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
18.CY7C140/CY7C141 only.
19.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 8 of 19
Switching Characteristics Over the Operating Range
[7,12]
Parameter Description
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55 Unit
Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 35 45 55 ns
t
AA
Address to Data Valid
[13]
35 45 55 ns
t
OHA
Data Hold from Address Change 0 0 0 ns
t
ACE
CE LOW to Data Valid
[13]
35 45 55 ns
t
DOE
OE LOW to Data Valid
[13]
20 25 25 ns
t
LZOE
OE LOW to Low Z
[10, 14, 15]
333ns
t
HZOE
OE HIGH to High Z
[10, 14, 15]
20 20 25 ns
t
LZCE
CE LOW to Low Z
[10, 14, 15]
555ns
t
HZCE
CE HIGH to High Z
[10, 14, 15]
20 20 25 ns
t
PU
CE LOW to Power Up
[10]
000ns
t
PD
CE HIGH to Power Down
[10]
35 35 35 ns
Write Cycle
[16]
t
WC
Write Cycle Time 35 45 55 ns
t
SCE
CE LOW to Write End 30 35 40 ns
t
AW
Address Setup to Write End 30 35 40 ns
t
HA
Address Hold from Write End 2 2 2 ns
t
SA
Address Setup to Write Start 0 0 0 ns
t
PWE
R/WPulse Width 25 30 30 ns
t
SD
Data Setup to Write End 15 20 20 ns
t
HD
Data Hold from Write End 0 0 0 ns
t
HZWE
R/WLOW to High Z
[15]
20 20 25 ns
t
LZWE
R/WHIGH to Low Z
[15]
000ns
Busy/Interrupt Timing
t
BLA
BUSY LOW from Address Match 20 25 30 ns
t
BHA
BUSY HIGH from Address Mismatch
[17]
20 25 30 ns
t
BLC
BUSY LOW from CE LOW 20 25 30 ns
t
BHC
BUSY HIGH from CE HIGH
[17]
20 25 30 ns
t
PS
Port Set Up for Priority 5 5 5 ns
t
WB[18]
R/W LOW after BUSY LOW 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH 30 35 35 ns
t
BDD
BUSY HIGH to Valid Data 35 45 45 ns
t
DDD
Write Data Valid to Read Data Valid Note 19 Note 19 Note19 ns
t
WDD
Write Pulse to Data Delay Note 19 Note19 Note19 ns
Interrupt Timing
t
WINS
R/Wto INTERRUPT SetTime 25 35 45 ns
t
EINS
CE to INTERRUPT Set Time 25 35 45 ns
t
INS
Address to INTERRUPTSetTime 25 35 45 ns
t
OINR
OE to INTERRUPT Reset Time
[17]
25 35 45 ns
t
EINR
CE to INTERRUPT Reset Time
[17]
25 35 45 ns
t
INR
Address to INTERRUPTReset Time
[17]
25 35 45 ns
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 9 of 19
Switching Waveforms
Figure 5. Read Cycle No. 1
[20, 21]
Figure 6. Read Cycle No. 2
[20, 22]
Figure 7. Read Cycle No. 3
[21]
Notes
20.R/W is HIGH for read cycle.
21.Device is continuously selected, CE= V
IL
and OE = V
IL
.
22.Address valid prior to or coincident with CEtransition LOW.
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATAVALID
DATA OUT
ADDRESS
Either Port Address Access
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
Either Port CE/OE Access
t
BHA
t
BDD
VALID
t
DDD
t
WDD
ADDRESS MATCH
ADDRESS MATCH
R/W
R
ADDRESS
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
t
PS
t
BLA
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
t
PWE
VALID
t
HD
[+] Feedback

CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 10of 19
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
[16, 23]
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
[17, 24]
Switching Waveforms (continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
CE
R/W
ADDRESS
t
HZOE
OE
D
OUT
DATA
IN
Either Port
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
DATAVALID
t
LZWE
ADDRESS
CE
R/W
DATA
OUT
DATA
IN
Notes
23.IfOEis LOW during a R/W controlled write cycle, the writepulsewidthmust be the larger of t
PWE
or t
HZWE
+t
SD
toallowthe dataI/O pins toenterhighimpedance
and for data to be placed on the bus for the required t
SD
.
24.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
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