Cypress Semiconductor CY7C09089V User manual

CY7C09079V/89V/99V
CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06043 Rev. *C Revised December 10, 2008
Features
■True Dual-Ported memory cells which enable simultaneous
access of the same memory location
■6 Flow-Through and Pipelined devices
■32K x 8/9 organizations (CY7C09079V/179V)
■64K x 8/9 organizations (CY7C09089V/189V)
■128K x 8/9 organizations (CY7C09099V/199V)
■3 Modes
■Flow-Through
■Pipelined
■Burst
■Pipelined output mode on both ports enables fast 100 MHz
operation
■0.35-micron CMOS for optimum speed and power
■High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)
■3.3V low operating power
■Active= 115 mA (typical)
■Standby= 10 μA (typical)
■Fully synchronous interface for easier operation
■Burst counters increment addresses internally
■Shorten cycle times
■Minimize bus noise
■Supported in Flow-Through and Pipelined modes
■Dual Chip Enables for easy depth expansion
■Automatic power down
■Commercial and Industrial temperature ranges
■Available in 100-pin TQFP
■Pb-free packages available
Notes
1. See page 6 for Load Conditions.
2. I/O0–I/O7for x8 devices, I/O0–I/O8for x9 devices.
3. A0–A14 for 32K, A0–A15 for 64K, and A0–A16 for 128K devices.
Logic Block Diagram
R/WL
CE0L
CE1L
OEL
FT/PipeL
I/O0L–I/O7/8L
Control
A0–A14/15/16L
CLKL
ADSL
CNTENL
CNTRSTL
R/WR
1
0
0/1
CE0R
CE1R
OER
10/1 0
FT/PipeR
I/O0R–I/O7/8R
I/O
Control
A0–A14/15/16R
CLKR
ADSR
CNTENR
CNTRSTR
1
0
0/1
1
0/1 0
I/O
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
8/9 8/9
[2] [2]
[3] [3]
15/16/17 15/16/17
CY7C0907 9V/89V/99V
CY7C0917 9V/89V/99V
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 2 of 21
Functional Description
The CY7C09079V/89V/99V and CY7C09179V/89V/99V are
high speed synchronous CMOS 32K, 64K, and 128K x 8/9
dual-port static RAMs. Two ports are provided, permitting
independent, simultaneous access for reads and writes to any
location in memory.[4] Registers on control, address, and data
lines enable minimal setup and hold times. In pipelined output
mode, data is registered for decreased cycle time. Clock to data
valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be
used to bypass the pipelined output register to eliminate access
latency. In flow-through mode, data is available tCD1 = 18 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to enable the shortest possible cycle times.
A HIGH on CE0or LOW on CE1for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0LOW and CE1HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW-to-HIGH transition of
that port’s clock signal. This reads/writes one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and loops
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
Figure 1. 100-Pin TQFP (Top View) - CY7C09099V (128K x 8), CY7C09089V (64K x 8),CY7C09079V (32K x 8)
Notes
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. This pin is NC for CY7C09079V.
6. This pin is NC for CY7C09079V and CY7C09089V.
7. For CY7C09079V and CY7C09089V, pin #23 connected to VCC is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin
compatible with an IDT 5V x16 flow-through device.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
A15R
A12R
A14R
GND
NC
NC
CE0R
A13R
A11R
NC
NC
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
A16R
58
57
56
55
54
53
52
51
NC
NC
A7L
A8L
A9L
A10L
A15L
A12L
A14L
VCC
NC
NC
CE0L
A13L
A11L
NC
NC
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
A16L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NC NC A6L A5L A4L A3L CLKL A1L CNTENL GND ADSR A0R A1R A0L A2L CLKR CNTENR A2R A3R A4R A5R A6R NC NC ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC NC NC
I/O7R I/O6R I/O5R
I/01R
I/O3R I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L I/O1L I/O3L I/O4L I/O5L I/O6L I/O7L
NC
GND
I/O0R
3332313029282726
[5] [5]
[6]
[6]
[7]
[7]
[+] Feedback

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 3 of 21
Pin Configurations (continued
Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9)
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
A15R
A12R
A14R
GND
NC
NC
CE0R
A13R
A11R
NC
NC
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
A16R
58
57
56
55
54
53
52
51
NC
NC
A7L
A8L
A9L
A10L
A15L
A12L
A14L
VCC
NC
NC
CE0L
A13L
A11L
NC
NC
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
A16L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NC NC A6L A5L A4L A3L CLKL A1L CNTENL GND GND CNTENR A0R A0L A2L ADSR CLKR A1R A2R A3R A4R A5R A6R NC ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC NC
I/O8R I/O7R I/O6R I/O5R
I/01R
I/O3R I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L I/O1L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L
GND
I/O0R
3332313029282726
[8] [8]
[9][9]
[+] Feedback

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 4 of 21
Notes
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V
Selection Guide
Description CY7C09079V/89V/99V
CY7C09179V/89V/99V-6[1] CY7C09079V/89V/99V CY7C09179V/89V/99V-7[1]
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-9
CY7C09079V/89V/99V
CY7C09179V/89V/99V
-12
fMAX2 (MHz)
(Pipelined)
100 83 67 50
Max. Access Time
(ns) (Clock to Data,
Pipelined)
6.5 7.5 9 12
Typical Operating
Current ICC (mA)
175 155 135 115
Typical Standby
Current for ISB1
(mA) (Both Ports
TTL Level)
25 25 20 20
Typical Standby
Current for ISB3
(μA) (Both Ports
CMOS Level)
10 μA 10 μA10μA 10 μA
Pin Definitions
Left Port Right Port Description
A0L–A16L A0R–A16R Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
ADSLADSRAddress Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads
the burst counter with the address present on the address pins.
CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0AND CE1must be asserted
to their active states (CE0≤VIL and CE1≥ VIH).
CLKLCLKRClock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are
asserted LOW.
CNTRSTLCNTRSTRCounter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7for x8 devices; I/O0–I/O8for x9 devices).
OELOEROutput Enable Input. This signal must be asserted LOW to enable the I/O data pins during
read operations.
R/WLR/WRRead/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPELFT/PIPERFlow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND Ground Input.
NC No Connect.
VCC Power Input.
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 5 of 21
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[10]
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ........................... –0.5V to VCC+0.5V
DC Input Voltage ..................................... –0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature VCC
Commercial 0°C to +70°C 3.3V ±300 mV
Industrial[11] –40°C to +85°C 3.3V ±300 mV
Notes
10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
11. Industrial parts are available in CY7C09099V and CY7C09199V only.
12. CELand CERare internal signals. To select either the left or right port, both CE0AND CE1must be asserted to their active states (CE0≤VIL and CE1≥ VIH).
Electrical Characteristics Over the Operating Range
Parameter Description
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Unit
-6[1] -7[1] -9 -12
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOH Output HIGH Voltage (VCC = Min. IOH =
–4.0 mA)
2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage (VCC = Min. IOH =
+4.0 mA)
0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IOZ Output Leakage Current –10 10 –10 10 –10 10 –10 10 μA
ICC Operating Current
(VCC
= Max. IOUT = 0 mA)
Outputs Disabled
Commercial. 175 320 155 275 135 225 115 205 mA
Industrial[11] 275 390 185 295 mA
ISB1 Standby Current (Both
Ports TTL Level)[12] CEL
& CER≥VIH, f = fMAX
Commercial. 25 95 25 85 20 65 20 50 mA
Industrial[11] 85 120 35 75 mA
ISB2 Standby Current (One
Port TTL Level)[12] CEL|
CER≥VIH, f = fMAX
Commercial. 115 175 105 165 95 150 85 140 mA
Industrial[11] 165 210 105 160 mA
ISB3 Standby Current (Both
Ports CMOS Level)[12]
CEL& CER≥VCC – 0.2V,
f = 0
Commercial. 10 250 10 250 10 250 10 250 μA
Industrial[11] 10 250 10 250 μA
ISB4 Standby Current (One
Port CMOS Level)[12]
CEL| CER≥VIH, f = fMAX
Commercial 105 135 95 125 85 115 75 100 mA
Industrial[11] 125 170 95 125 mA
Capacitance
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 3.3V
10 pF
COUT Output Capacitance 10 pF
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 6 of 21
Figure 4. AC Test Loads (Applicable to -6 and -7 only)[13]
Figure 5. Load Derating Curve
Figure 3. AC Test Loads
(a) Normal Load (Load 1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
RTH = 250Ω
(Used for tCKLZ, tOLZ, & tOHZ
including scope and jig)
V
TH
=1.4V
OUTPUT
C
(a) Load 1 (-6 and -7 only)
R = 50 Ω
Z
0
= 50 Ω
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUT PULSES
≤≤
0.00
0.1 0
0.20
0.30
0.40
0.50
0.60
1 0 1 5 20 25 30 35
Capacitance (pF)
Δ
(ns) for all -7 access times
Note
13. Test Conditions: C = 10 pF.
[+] Feedback

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 7 of 21
Notes
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
Switching Characteristics Over the Operating Range
Parameter Description
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Unit
-6[1] -7[1] -9 -12
Min Max Min Max Min Max Min Max
fMAX1 fMax Flow-Through 53 45 40 33 MHz
fMAX2 fMax Pipelined 100 83 67 50 MHz
tCYC1 Clock Cycle Time - Flow-Through 19 22 25 30 ns
tCYC2 Clock Cycle Time - Pipelined 10 12 15 20 ns
tCH1 Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns
tCL1 Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns
tCH2 Clock HIGH Time - Pipelined 4 5 6 8 ns
tCL2 Clock LOW Time - Pipelined 4 5 6 8 ns
tRClock Rise Time 3 3 3 3 ns
tFClock Fall Time 3 3 3 3 ns
tSA Address Set-Up Time 3.5 4 4 4 ns
tHA Address Hold Time 0 0 1 1 ns
tSC Chip Enable Set-Up Time 3.5 4 4 4 ns
tHC Chip Enable Hold Time 0 0 1 1 ns
tSW R/W Set-Up Time 3.5 4 4 4 ns
tHW R/W Hold Time 0 0 1 1 ns
tSD Input Data Set-Up Time 3.5 4 4 4 ns
tHD Input Data Hold Time 0 0 1 1 ns
tSAD ADS Set-Up Time 3.5 4 4 4 ns
tHAD ADS Hold Time 0 0 1 1 ns
tSCN CNTEN Set-Up Time 3.5 4.5 5 5 ns
tHCN CNTEN Hold Time 0 0 1 1 ns
tSRST CNTRST Set-Up Time 3.5 4 4 4 ns
tHRST CNTRST Hold Time 0 0 1 1 ns
tOE Output Enable to Data Valid 8 9 10 12 ns
tOLZ[14, 15] OE to Low Z 2 2 2 2 ns
tOHZ[14, 15] OE to High Z 1 7 1 7 1 7 1 7 ns
tCD1 Clock to Data Valid - Flow-Through 15 18 20 25 ns
tCD2 Clock to Data Valid - Pipelined 6.5 7.5 912 ns
tDC Data Output Hold After Clock HIGH 2 2 2 2 ns
tCKHZ[14, 15] Clock HIGH to Output High Z 2 9 2 9 2 9 2 9 ns
tCKLZ[14, 15] Clock HIGH to Output Low Z 2 2 2 2 ns
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns
tCCS Clock to Clock Set-Up Time 9 10 15 15 ns
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 8 of 21
Switching Waveforms (continued)
Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19]
Notes
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS = VIL, CNTEN and CNTRST = VIH.
18. The output is disabled (high-impedance state) by CE0=VIH or CE1= VIL following the next rising edge of the clock.
19. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference
only.
tCH1 tCL1
tCYC1
tSC tHC
tDC
tOHZ
tOE
tSC tHC
tSW tHW
tSA tHA
tCD1 tCKHZ
tDC
tOLZ
tCKLZ
AnAn+1 An+2 An+3
QnQn+1 Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
[+] Feedback

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 9 of 21
Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19]
Figure 8. Bank Select Pipelined Read[20, 21]
-
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
D3
D1
D0
D2
A0A1A2A3A4A5
D4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLKL
ADDRESS(B1)
CE0(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE0(B2)
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CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 10 of 21
Figure 9. Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25]
Notes
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1)
= ADDRESS(B2).
21. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE0and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
24. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
25. It tCCS ≤maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
tSA tHA
tSW tHW
tSD tHD
MATCH
VALID
tCCS
tSW tHW
tDC
tCWDD
tCD1
MATCH
tSA tHA
MATCH
NO
MATCH
NO
VALID VALID
tDC
tCD1
CLKL
R/WL
ADDRESSL
DATAINL
ADDRESSR
DATAOUTR
CLKR
R/WR
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