Epson RTC-9701JE Instructions for use

MQ362-03
Application Manual
Real Time Clock Module
RTC-9701JE
Model Product Number
RTC-9701JE Q4197017x000100

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RTC - 9701 JE
Contents
1. OVERVIEW ...................................................................................................1
2. BLOCK DIAGRAM.........................................................................................1
3. TERMINAL DESCRIPTION ...........................................................................2
3.1. TERMINAL CONNECTIONS ........................................................................................................ 2
3.2. PIN FUNCTIONS ...................................................................................................................... 2
4. ABSOLUTE MAXIMUM RATINGS.................................................................3
5. RECOMMENDED OPERATING CONDITIONS.............................................3
6. FREQUENCY CHARACTERISTICS..............................................................3
7. DC ELECTRICAL CHARACTERISTICS........................................................3
8. AC ELECTRICAL CHARACTERISTICS ........................................................4
9. VOLTAGE DETECTION CHARACTERISTICS..............................................5
9.1. VEX VOLTAGE DETECTION CHARACTERISTICS........................................................................... 5
9.2. VLF VOLTAGE DETECTION CHARACTERISTICS ........................................................................... 5
10. EEPROM MEMORY CHARACTERISTICS..................................................6
11. REGISTER TABLE......................................................................................7
11.1. REGISTER TABLE ................................................................................................................... 7
11.2. DESCRIPTION OF RTC FUNCTIONS (ADDRESSES BETWEEN 0 AND 7) ........................................ 8
11.3. ALARM FUNCTIONS (/AIRQ)................................................................................................... 9
11.4. TIMER FUNCTION (/TIRQ).................................................................................................... 12
11.5. CONTROL REGISTER / FLAG REGISTER.................................................................................. 13
12. READ / WRITE DATA................................................................................14
12.1. SERIAL DATA TRANSFER METHOD ......................................................................................... 14
12.2. READING/WRITING IN RTC MODE......................................................................................... 15
12.3. READ / WRITE EEPROM MEMORY ...................................................................................... 16
13. EXTERNAL CONNECTION EXAMPLES...................................................17
14. EXTERNAL DIAGRAM / MARKING LAYOUT............................................18
14.1. EXTERNAL DIAGRAM............................................................................................................ 18
14.2. MARKING LAYOUT................................................................................................................ 18
15. REFERENCE DATA..................................................................................19
16. APPLICATION NOTES..............................................................................20

RTC - 9701 JE
MQ - 362 - 03
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Serial RTC Module with Alarm and Timer Function
RTC - 9701JE
•Built-in 32.768 kHz crystal oscillator with frequency adjusted
•Alarm interrupt function for day of the week, day, hour, and minute
•Interval timer interrupt function
•Voltage decrease alarm function
•Time update alarm function
•Automatic adjustment for leap year
•Voltage detection function
•Nonvolatile 4 kbit (256×16 bit) memory
•Main power supply (VDD) 2.7 V ∼3.6 V
•Backup power supply (VDD2) 1.8 V ∼5.5 V
•Low current consumption at 0.8 µA / 3 V (Typ.)
•Available as small package (JE : VSOJ-20 pin)
1. Overview
This module is a high precision RTC module with serial interface in 4 lines form (or 3 lines form). It has a built-in 32.768
kHz crystal oscillator.
The system IC in the package has a variety of built-in functions such as high precision clock circuitry, crystal oscillator,
32.768 kHz output, nonvolatile memory, voltage detection circuitry, alarm and timer.
2. Block diagram
INTERRUPTS
CONTROLLER
A
LARM
REGISTER
OSC
/ TIRQ
BUS
INTERFACE
CIRCUIT
CLK
32.768 kHz
CONTROL
REGISTER
DIVIDER CLOCK
Control Line
C E
FOUT
CONTROLLER
FOUT
D I
TIMER
REGISTER
FOE
and
CALENDAR
/ AIRQ
D O
RTC - 9701
VDD2
VEX
VLF
EEPROM
256 ×16 bit
Vi Vo
VDD
GND

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3. Terminal description
3.1. Terminal connections RTC - 9701 JE
1. VDD2 20. N.C.
2. VEX 19. N.C.
3. FOE 18. N.C.
4. /AIRQ 17. N.C.
5. /TIRQ 16. N.C.
6. CE 15. N.C.
7. CLK 14. N.C.
8. DI 13. GND
9. DO 12. GND
10. VDD
# 1
#10
#20
#11 11. FOUT
VSOJ - 20 pin
3.2.Pin functions
Pin name Pin
number
∗1
I / O Functions
∗2
VDD2
1
−
RTC power (backup power). This pin is connected to the plus side of the power.
(Always supply the power irrespective of action situation to this terminal.)
∗2
VEX
2
Input
External voltage detection input pin. If external voltage decreases blow VEX,EXF
bit became “1” .
Note: This function acts only when VDD2 is supplied the power.
FOE 3
Input
This is an input pin to control FOUT output.
When the FOE pin is at the“H” level, the FOUT pin goes into the output state; when
it is at the “L” level, the FOUT pin becomes Low.
/AIRQ 4 Input This is the open drain output pin for alarm and time update interrupts.
/TIRQ 5
Output
This is the open drain output pin for timer interrupt.
C E 6
Input
This is a chip enabled input pin with the built-in pull-down resistor.
When the CE pin is at the “H” level, access to this RTC becomes possible.
When the CE pin is at the “L” level, the DO pin is at the high impedance level, and the
CLK and DI pins would not accept input.
CLK 7
Output
This is the shift clock input pin for serial data transfer.
In the write mode, it takes in data from the DI pin using the CLK signal rise edge. In
the read mode, it outputs data from the DO pin using the fall edge.
DI 8 Output Serial data input pin
DO 9 Input Serial data output pin
∗2
VDD
10
Output
Main power. This pin is connected to the plus side of the power.
FOUT 11
−
This pin outputs the reference clock signal at 32.768 kHz (CMOS output).
Depending on the level of the FOE input pin, output from the FOUT pin can be
prohibited.
GND This pin is connected to the minus side (ground) of the power.
N.C. 14 −22 −
This pin is not connected to the IC chip. All the N.C. pins are connected collectively
with the inside frame.
Connect this pin to OPEN, GND, or VDD.
*1 ) I: CMOS INPUT, O: CMOS OUTPUT, AIN: Analog INPUT, O.D.: Open Drain Output
*2 ) Be sure to connect a filter capacitor of at least 0.1 µF near VDD−GND, VDD2−GND and VEX−GND.

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4. Absolute maximum ratings GND=0 V
Item Symbol Condition Rating Unit
Power voltage VDD, VDD2 VDD−GND, VDD2−GND −0.3 to +6.0 V
VIN Input pin GND−0.3 to VDD+0.3 V
Input voltage VAIN VEX pin GND−0.3 to +6.0
Output voltage VOUT /AIRQ, /TIRQ, FOUT, DO pins GND−0.3 to VDD+0.3 V
Storage temperature TSTG Stored bare product after unpacking −55 to +125 °C
5. Recommended operating conditions GND=0 V
Item Symbol Condition Rating Unit
Operating power voltage VDD VDD pin 2.7 to 3.6 V
RTC power voltage VDD2 VDD2 pin 1.8 to 5.5 V
Analog power voltage VEX VEX pin 1.4 to 5.5 V
Operating temperature TOPR No condensation -40 to +85 °C
6. Frequency characteristics GND=0 V
Item Symbol Condition Rating Unit
Frequency accuracy /
Clock accuracy ∆f / fo Ta= +25 °C
VDD2=3.0 V 5 ±23 (∗1) ×10−6
Frequency voltage
characteristics f / V Ta= +25 °C
VDD=1.8 V to 5.5 V ±2 Max. ×10−6/ V
Frequency temperature
characteristics Top Ta= −10 °C to +70 °C
VDD= 3.0 V ; reference at +25 °C+10 / −120 ×10−6
Oscillation start up time tSTA Ta= +25 °C
VDD=3.0 V 3 Max. s
Aging fa
Ta= +25 °C
VDD=3.0 V ; first year ±5 Max. ×10−6/ year
∗1 ) Equivalent to 1 minute of monthly deviation (excluding offset).
7. DC Electrical characteristics
*If not specifically indicated, VDD=2.7 V to 3.6 V, VDD2=1.8 V to 5.5 V,
GND=0 V, Ta= −40 °C to +85 °C
Item Symbol Condition Min. Typ. Max. Unit
IDD1 VDD=3.0 V,
FOUT; output OFF 0.2 3.0
VDD current
consumption IDD2 VDD=3.0 V, CL=0 pF,
FOUT; 32.768 kHz output ON 1.0 3.5
µA
IBK1 VDD2=3.0 V,
FOUT; output OFF 0.8 1.0
VDD2 current
consumption IBK2 VDD2=3.0 V, CL=0 pF,
FOUT; 32.768 kHz output ON 0.8 1.0
µA
"H" input voltage VIH CE, CLK, DI, FOE pin 0.8VDD VDD V
"L" input voltage VIL CE, CLK, DI, FOE pin 0 0.2VDD V
VOH1 FOUT pin IOH = −1 mA VDD−0.4 VDD
"H" Output
voltage VOH2 DO pin IOH = −1 mA VDD−0.4 VDD V
VOL1 FOUT pin IOL = 1 mA GND GND+0.4
VOL2 DO pin IOL = 1 mA GND GND+0.4
"L" Output
voltage VOL3 /AIRQ, /TIRQ pin IOL = 2 mA GND GND+0.4 V
Input resistor RDWN CE, FOE pin VIN = VDD or GND 75 600 kΩ
Input leakage
current ILK CE, CLK, DI, FOE pin VOUT = VDD or GND −0.5 0.5
µA
Output leakage
current IOZ DO, /AIRQ, /TIRQ, FOUT pin VIN = VDD or GND −0.5 0.5
µA

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8. AC Electrical characteristics
*If not specifically indicated, VDD=2.7 V to 3.6 V, VDD2=1.8 V to 5.5 V,
GND=0 V, Ta= −40 °C to +85 °C
Item Symbol Condition Min. Typ. Max. Unit
CLK clock cycle tCLK Vth = 50% VDD 500 ns
CLK H pulse width tWH Vth = 50% VDD 230 ns
CLK L pulse width tWL Vth = 50% VDD 230 ns
CE setup time tCS 110 ns
CE hold time tCH 170 ns
Write data setup time tDS 150 ns
Write data hold time tDH 150 ns
Read data delay time tRD CL= 65 pF ±10 pF 240 ns
DO output switching time tZR CL= 65 pF ±10 pF 170 ns
DO output disable time tRZ CL= 65 pF ±10 pF
RL= 10 k 240 ns
Ready setup time tRDY 65 ns
CLK rise and fall time tRF 20 % ∼80 % of VDD 30 ns
Carry Busy ∗1tcarry X’tal = 32.768 kHz 7.8125 ms
FOUT Duty tw / t Vth = 50% VDD
VDD = 3.0V 40 50 60 %
*1 ) Since “writing to EEPROM: twnv” and “performing carry action: tcarry” are OR output, maximum of 17.8125ms Busy signal
output.
Read & Write Timing
With exception of data transfer at initial power supply and at voltage decrease of VDD2, hold the carry operation when
transfering data, so that the DO pin will output the Busy signal (0:Busy / 1:Ready) right after communication starts
(CE=HIGH). If it’s at the Ready state, communication is permitted. If it’s at the Busy state, either the clock is being
updated or the EEPROM Memory is being written. In this case, wait until it becomes Ready, or stop communication
(CE=LOW) once to restart some time after. By any chance a data is transferred when it is at the Busy state, that data is
not guranteed to be safe. The Busy signal becomes Hi-z at the timing when the initial rise edge of the clock occurs.
CE
CLK
DI
DO
DO
DI
Read
Write
tCS
tZR
Busy Ready
Busy Ready
tRDY tRZ
VOH
VOL m3 m2 a0 d7
m3∗1m2 a0
tDS tDH
Hi-z
Hi-z
tZR
tRD
d7∗1d6 d5
d6 d5
d0
d0
tRZ
tRF tRF
80%
20%
tCLK
tWL tWH
Vth
tCH tCR∗2
∗1) The address width and the data width in the RTC mode differs for those in the EEPROM Memory mode.
∗2) If the Busy/Ready signal is ignored, make sure to reserve 16 ms at least once every second.
∗3) Latch data at the positive edge. (Data is output at the Negative Edge of clock signal.)
∗4) Since the registers are undefined at initial power supply as well as after voltage decrease of VDD2, the Ready signal
may not output. After power supply, reserve more than 20ms, and then check the Busy / Ready signal. If the Ready
signal is not output in more than 17.8125 ms, access by ignoring the Busy signal and initialize all the registers.

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9. Voltage detection characteristics
9.1. VEX voltage detection characteristics *If not specifically indicated, VDD=2.7 V to 3.6 V,
VDD2=1.8 V to 5.5 V,GND=0 V, Ta= −40 °C to +85 °C
Item Signal Condition Min. Typ. Max. Unit
Current consumption IDDVEX VEX = 3.0 V 10 20 40 µA
Operation voltage for detection
circuitry VEX VEX pin 2.3 2.5 2.7 V
Hysteresis voltage VHYS 70 120 170 mV
Low active voltage VACT IOL = 1 mA , VOL = 0.4 V 1.4 V
* Be sure to connect a filter capacitor of at least 0.1 µF near VEX−GND.
9.2. VLF voltage detection characteristics
*If not specifically indicated, VDD=2.7 V to 3.6 V,
VDD2=1.8 V to 5.5 V,GND=0 V, Ta= −40 °C to +85 °C
Item Signal Condition Min. Typ. Max. Unit
Current consumption IDDVLF VLF constant enable 3 10 30 µA
Operation voltage for detection
circuitry VLF VDD2 pin 1.4 1.8 2.2 V

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10. EEPROM Memory characteristics
* If not specifically indicated,GND=0 V, VDD=2.7 V to 3.6
V, VDD2=1.8 V to 5.5 V, Ta=-40 °C to +85 °C
Item Symbol Condition Min. Typ. Max. Unit
Memory configuration 4 kbit ( 256 ×16 bit ) −
Program/Erase cycle 105times
Current consumption IDD3 Write to EEPROM 1 3 mA
Access time tWNV 5 10 ms
VDD = 3.0 V ±0.3 V 1000 ns
CLK clock cycle tECLK VDD = 3.3 V ±0.3 V 900 ns
CLK H pulse width tEWH 430 ns
CLK L pulse width tEWL 430 ns
CE setup time tECS 110 ns
CE hold time tECH 150 ns
Write data setup time tEDS 150 ns
Write data hold time tEDH 160 ns
Read data delay time tERD CL= 65 pF ±10 pF 240 ns
DO output switching time tEZR CL= 65 pF ±10 pF 170 ns
DO output disable time tERZ CL= 65 pF ±10 pF
RL= 10 k 240 ns
Ready setup time tERDY 65 ns
Input rise and fall time tEr,tEf 20 % to 80 % of VDD 30 ns
* Power for the EEPROMMemoryis supplied from VDD. In order to turn the power OFF after writing, make sure to save
tWNV before turning the power OFF.
EEPROM Memory Timing ( Post Write Check )
CE
Read
Write
DI
DO
DI
DO
Hi-z
m2 a0
dF dE d0
VIH
VIH
VIL
VIL
VIH VIH
VIL
tEr tEf
VIL VIL VIH
tEWL tEWH
tECLK
VIL
VIH
tECH VIL
VIH VIL
tEZR
tECS
CLK
VOH
VOL
tEZR
Busy Ready
tERDY m3
tEDS t
EDH
VIH
VIL
tERZ
m3 m2 a0 dF dE d0
Hi-z
Busy Ready
VIL
VIH
tEZR
tERD
VOL
VOH
tERZ
tWNV tERZ
VOL
VOH
Busy Ready

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11. Register table
11.1. Register table
11.1.1. RTC register table (when the RTC mode is set)
Add
ress Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W Comments
0 SEC ∗1
¡S40 S20 S10 S8 S4 S2 S1 R/W BCD
notation
1 MIN ¡M40 M20 M10 M8 M4 M2 M1 R/W BCD
notation
2 HOUR ¡¡H20 H10 H8 H4 H2 H1 R/W BCD
notation
3 WEEK ¡W6 W5 W4 W3 W2 W1 W0 R/W
2n notation
4 DAY ¡¡D20 D10 D8 D4 D2 D1 R/W BCD
notation
5 MONTH ¡¡¡C10 C8 C4 C2 C1 R/W BCD
notation
6 YEAR Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 R/W BCD
notation
7 ∗2
Y100 0 0 1 0 0 0 0 0 R
20 is fixed
(BCD)
8 MINAlarm AE MA40 MA20 MA10 MA8 MA4 MA2 MA1 R/W BCD
notation
9 HOUR Alarm AE ¡HA20 HA10 HA8 HA4 HA2 HA1 R/W BCD
notation
WEEK Alarm WA6 WA5 WA4 WA3 WA2 WA1 WA0 WADA=0
A DAY Alarm AE ¡DA20 DA10 DA8 DA4 DA2 DA1 R/W WADA=1
B ∗3
Reserved Reserved R/W
Prohibition R/W Prohibition
C Interval
Timer TDUTY CT6 CT5 CT4 CT3 CT2 CT1 CT0 R/W −
D Extension
Reg. ∗4
TEST WADA UDUTY USEL ¡¡TSEL1 TSEL0 R/W −
E ∗5
Flag Reg. VLF2 ¡UF TF AF EXF VLF ¡R/W −
F Control Reg. ¡¡UIE TIE AIE EXIE VLIE ¡R/W −
Note1. 1. At the initial power supply, the values of the registers are not fixed, so please initialize them before use.
While initializing, do not set impossible data for date and time; otherwise there is no guarantee that the
clock will operate properly.
Note2. ∗1.“0” is read where “¡” is marked. When writing data, use “0”.
∗2. Since these are read-only bits, write is not permitted.
∗3. The Resreved register used by EPSON for testing. Setting does not do.
∗4. The TEST bit is used by EPSON for testing. Be sure to set it to "0" before use.
∗5. The flag bit will cleared with “0”. ( “0” can not be replace to “1”.)
11.1.2. EEPROM Memory table (When EEPROM Memory mode is set.)
Data
Segment Address dF dE dD dC dB dA d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Comments
0 00
•
•
•User Memory 4 kbit
( 256 ×16 bit )
FF