Epson RX8804CE Instructions for use

ETM59E-05
Preliminary
Application Manual
Real Time Clock Module
RX8804CE

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ETM59E Revision History
Rev No.
Date
Page
Description
ETM59E-01
16.Apr.2018
Release
02
18.Apr.2018
4
Updated Pull-up Resistor value.
35
Updated mention of tCD.
40
EVIN connects to VDD of 32kHz-TCXO.
03
27.Apr.2018
5
Note of Timing chart.
I2C bus time out is 1second(Max,) from 2seconds,
4
Peak Current consumption (2)
50µA(Typ.) from 55µA(Typ.)
10
8.2.5. Extension register
The default value was updated.
11
8.2.6. Flag register
The default value was updated.
41
9.1.2. Marking layout
Frequency stability Mark and Lot Mark was updated.
04
14.Jun.2018
16
40
5) RESET bit
it explained detailed function of RESET.
8.15. Figure of 32 kHz-TCXO was updated.
SCL and SDA connects to GND.
05
18.Sep.2020
1
Feature and Overview was updated.
6
Table 6 Average Current consumption was added.
10
Figure 6 Intertnal clock distribution diagram was added.
17
8.3. SOUT Function
Optimization of explanation.
Corrected of program example.
19
8.4. EVIN Interrupt and Time Stamp Function
Optimization of explanation.
Program example was added.
39
8.12. Flow Chart was Optimized
43
9.1.1. External dimensions Note was added, *1
45
11. Figures and 12.Tables are added.

RX8804CE
ETM59E-05
Table of Contents
1. Overview................................................................................................................................................... 1
2. Block Diagram.......................................................................................................................................... 1
3. Terminal Description................................................................................................................................ 2
3.1. Terminal Connections............................................................................................................................................ 2
3.2. Pin Functions......................................................................................................................................................... 2
4. Absolute Maximum Ratings ..................................................................................................................... 3
5. Recommended Operating Conditions...................................................................................................... 3
6. Frequency Characteristics ....................................................................................................................... 3
7. Electrical Characteristics.......................................................................................................................... 4
7.1. DC Characteristics................................................................................................................................................. 4
7.2. AC Characteristics................................................................................................................................................. 5
7.3. Reference Characteristics ..................................................................................................................................... 6
7.3.1 Temperature Compensation and Consumption Current.............................................................................. 6
7.3.2 IDD vs TC Characteristics for Reference. .................................................................................................... 6
7.3.3 Reference Characteristic of I2C-Bus Active Current.................................................................................... 6
8. Use Methods............................................................................................................................................ 7
8.1. Description of Registers......................................................................................................................................... 7
8.1.1. Write / Read and Bank Select.................................................................................................................... 7
8.1.2. Register Table (Basic time and calendar register) ..................................................................................... 7
8.1.3. Register Table (Time stamp, EVIN, SOUT, Timer) .................................................................................... 8
8.1.4. Quick Reference ........................................................................................................................................ 8
8.1.5 Initial Value of Registers.............................................................................................................................. 8
8.2.1. Clock Counter (SEC - YEAR)..................................................................................................................... 9
8.2.2. Alarm Registers........................................................................................................................................ 10
8.2.3. Wakeup Timer Control Registers............................................................................................................. 11
8.2.4. Control Registers, Flag Registers ............................................................................................................ 11
8.2.5. SOUT Control Register ............................................................................................................................ 13
8.2.6. Time Stamp Data Event Controller Register ............................................................................................ 14
8.3. SOUT Function.................................................................................................................................................... 17
8.3.1. 2 Kinds of SOUT Function........................................................................................................................ 17
8.3.2. SOUT Function Program ex.1.................................................................................................................. 17
8.3.3. SOUT Function Program ex.2.................................................................................................................. 18
8.4. EVIN Interrupt and Time Stamp Function............................................................................................................ 19
8.4.1. Time Stamp Program ex. ......................................................................................................................... 19
8.4.2. Timing Chart of EVIN Time Stamping. ..................................................................................................... 20
8.4.3. /INT pin Operation when an Interrupt Occurs........................................................................................... 20
8.5. Alarm Interrupt Function...................................................................................................................................... 21
8.5.1. Alarm Interrupt Function........................................................................................................................... 21
8.5.2. Alarm Interrupt Function Register ............................................................................................................ 21
8.5.3. Examples of Alarm Settings..................................................................................................................... 22
8.5.4. Alarm Interrupt Timing Chart.................................................................................................................... 23
8.5.5. /INT pin Operation when an Interrupt Occurs........................................................................................... 24
8.6. Wakeup Timer Interrupt Function ........................................................................................................................ 24
8.6.1. Wakeup Timer Interrupt Function............................................................................................................. 24
8.6.2. Wakeup Timer Interruption Registers....................................................................................................... 24
8.6.3. Wakeup Timer Start Timing...................................................................................................................... 26
8.3.4. Wakeup Timer Interrupt Interval (example).............................................................................................. 27
8.3.5. Wakeup Timer Interrupt Timing Chart...................................................................................................... 27
8.7. Time Update Interrupt Function........................................................................................................................... 29
8.7.1. Time Update Interrupt Function................................................................................................................ 29
8.7.2. Related Registers for Time Update Interrupt Functions........................................................................... 29
8.7.3. Time Update Interrupt Function Timing Chart.......................................................................................... 30
8.8. Temperature Compensation Function. ................................................................................................................ 31
8.8.1. Temperature Compensation Function...................................................................................................... 31
8.8.2. Related Registers for Temperature Compensation Function ................................................................... 31
8.9. Reading / Writing Data via the I2C-Bus Interface................................................................................................. 32
8.9.1. Overview of I2C-Bus................................................................................................................................. 32
8.9.2. System Configuration............................................................................................................................... 32
8.9.3. Starting and Stopping I2C-Bus Communications...................................................................................... 33
8.9.4. Data Transfers and Acknowledge Responses during I2C-Bus Communications...................................... 34
8.9.5. Slave Address.......................................................................................................................................... 35
8.9.6. I2C-Bus Protocol....................................................................................................................................... 36
8.10. Backup and Recovery........................................................................................................................................ 37
8.11. About Access at the Time of Backup Return and Initial Power Supply.............................................................. 38
8.12. Flow Chart ......................................................................................................................................................... 39
8.13. Connection with Typical Microcontroller ............................................................................................................ 42

RX8804CE
ETM59E-05
8.14. When Used as a Clock Source (32 kHz-TCXO) ................................................................................................ 42
9. External Dimensions / Marking Layout................................................................................................... 43
9.1. RX8804CE .......................................................................................................................................................... 43
9.1.1. External Dimensions ................................................................................................................................ 43
9.1.2. Marking Layout......................................................................................................................................... 43
10.Application Notes .................................................................................................................................. 44
11.Figures................................................................................................................................................... 45
12.Tables.................................................................................................................................................... 45

RX8804CE
Page - 1 ETM59E-05
I2C-Bus Interface Real-time Clock Module
RX8804CE
1. Overview
This module is an I2C-Bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO.
In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter
function, this module provides an abundance of other functions including an alarm function, wakeup timer function,
time update interrupt function, 32.768 kHz output function, Time stamp function with EVIN-pin trigger,
and. Programmable output function to SOUT-pin of interrupt Flags or self monitoring Flags.
The devices in this module are fabricated via a CMOS process for low current consumption, which enables long-
term battery back-up.
2. Block Diagram
Figure 1 Block Diagram
•Built-in 32.768 kHz DTCXO
•Interface Type
: I2C-Bus (Up to 400 kHz)
•Low current consumption at backup
: 350 nA / 3.0 V Typ.
•Wide time-keeping voltage range
: 1.5 V to 5.5 V
•Wide interface voltage range
: 1.6 V to 5.5 V
• SOUT can output self monitoring status, voltage down etc.
: SOUT can output programmed H / L level also.
•Time stamp function of Seconds from Year
: One time recorded by trigger of EVIN.
•EVIN is equipped for time stamp trigger
: It has connectable pull up resistor
•Alarm interrupt function
: Combination of Day, Date, Hour, Minute, and AE bit
•Wakeup timer interrupt function
: Auto repeated 244.14 µs to 32 years
•Time update interrupt function
: Every second or every minute
•Temperature compensated 32.768 kHz or other output
: Available output enable control
•Auto correction of leap years
: Writing of "60 seconds" is available for Leap Second
adjustment
The I2C-Bus is a trademark of NXP Semiconductors
INTERRUPTS
CONTROLLER
ALARM REGISTER
/INT
BUS
INTERFACE
CIRCUIT
( 32.768 kHz )
CONTROL
REGISTER
DIVIDER
CLOCK
POWER
CONTROLLER
and
SDA
VDD
SCL
CALENDR
TIMER REGISTER
DTCXO
CONTROLLER
FOUT
FOUT
FOE
CONTROLLER
SOUT
SOUT
CONTROLLER
EVENT DETECTION
EVIN
CAPTURE
BUFFER
VDD
SYSTEM
CONTROLLER

RX8804CE
Page - 2 ETM59E-05
3. Terminal Description
3.1. Terminal Connections
RX8804CE
1.
FOE
10.
/INT
2.
VDD
9.
GND
3.
EVIN
8.
T2
4.
FOUT
7.
SDA
5.
SCL
6.
SOUT
Figure 2 Pin Layout
3.2. Pin Functions
Table 1 Pin Functions
Signal
name
I/O
Function
SDA
I/O
This pin's signal is used for input and output of address, data, and ACK bits, synchronized
with the serial clock used for I2C-Bus communications
Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable
pull-up resistance relative to the signal line capacity
SCL
Input
This is the serial clock input pin for I2C-Bus communications.
FOUT
Output
This is the CMOS output pin with output control provided via the FOE pin.
When FOE = ”H” (high level), this pin outputs a 32.768 kHz signal. (depend on FSEL bit)
When output is stopped, the FOUT pin = Hi-Z (high impedance)
FOE
Input
This is an input pin used to control the output mode of the FOUT pin
When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the
FOUT pin is stopped
/INT
Output
This pin is used to output alarm signals, timer signals, time update signals, and other
signals. This pin is an open drain pin
EVIN
Input
Trigger input terminal for time stamps. Pull-up resistor selectable by register setting
SOUT
Output
SOUT is push-pull for the inside state output
SOUT outputs state of a specified flag bit or programmed logical 1 or 0
VDD
−
This pin is connected to a positive power supply
GND
−
This pin is connected to a ground
T2
−
Use only for testing in the factory
(Do not connect externally)
Note: Be sure to connect a bypass capacitor rated at least 0.1 µF between VDD and GND.

RX8804CE
Page - 3 ETM59E-05
4. Absolute Maximum Ratings
Table 2 Absolute Maximum Rating
5. Recommended Operating Conditions
Table 3 Recommended Operating Conditions
GND = 0 V
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating supply voltage
VACC
Between VDD and GND
1.6
3.0
5.5
V
Temp. compensation voltage
VTEM
−
1.5
3.0
5.5
V
Clock supply voltage
VCLK
−
1.5
3.0
5.5
V
Operating temperature
Ta
No condensation
−40
+25
+105
C
* To apply Min. value of VACC and VCLK, the VDD needs to be supplied with more than 1.5 V at least for the oscillation to
stabilize (oscillation start time tSTA).
* The Min. value of VCLK is the Min. voltage required to retain the time counting function. it is however necessary to maintain
VTEM till the oscillation of the oscillator has stabilized (oscillation start time tSTA).
* The temperature compensation stops working below Min. value of VTEM.
6. Frequency Characteristics
Table 4 Frequency Characteristics
GND = 0 V
Item
Symbol
Condition
Rating
Unit
Frequency stability
f/f
XA
Ta = 0 to +50 C, VDD = 3.0 V
Ta = -40 to +85 C, VDD = 3.0 V
Ta = -85 to +105 C, VDD = 3.0 V
1.9 *1
3.4 *2
8.0 *3
10-6
XB
Ta = 0 to +50 C, VDD = 3.0 V
Ta = -40 to +85 C, VDD = 3.0 V
Ta = -85 to +105 C, VDD = 3.0 V
3.8 *4
5.0 *5
8.0 *3
Frequency/voltage
characteristics
f/V
Ta= +25 C, VDD=1.5 V to 5.5 V
1.0 Max.
10-6 / V
FOUT Symmetry
SYM
50% VDD level,
+25 C, VDD = 1.5 V to 5.5 V
50 10
%
Oscillation start time
tSTA
Ta = +25 C, VDD = 1.5 V 5.5 V
Ta = -40 to +85 C, VDD = 1.6 V to 5.5 V
1.0 Max.
3.0 Max.
s
Aging
fa
Ta = +25 C, VDD = 3.0 V, first year
3 Max.
10-6 / year
Reflow
fref
260 C Max. 2 times
3 Max.*6
10-6
*1 5 s error per a month.
*2 9 s error per a month.
*3 21 s error per a month.
*4 10 s error per a month.
*5 13.2 s error per a month.
GND = 0 V
Item
Symbol
Condition
Rating
Unit
Supply voltage
VDD
Between VDD and GND
−0.3 to +6.5
V
Input voltage (1)
VIN1
FOE, SCL, SDA, EVIN pins
GND −0.3 to +6.5
V
Input voltage (2)
VIN2
EVIN pin
GND −0.3 to VDD +0.3
V
Output voltage (1)
VOUT1
FOUT and SOUT pins
GND −0.3 to VDD +0.3
V
Output voltage (2)
VOUT2
SDA and /INT pins
GND −0.3 to +6.5
V
Storage temperature
TSTG
When stored separately,
without packaging
−55 to +125
C

RX8804CE
Page - 4 ETM59E-05
*6 The result that it was measured at 25

C, 24 hours after processing of reflow soldering.
7. Electrical Characteristics
7.1. DC Characteristics
Table 5 DC Characteristics
*Unless otherwise specified, GND = 0 V, VDD = 1.5 V to 5.5 V, Ta = −40 C to +105 C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Average Current consumption (1)
IDD1
fSCL = 0 Hz, /INT = Hi-Z,
FOUT is stopped
Temp compensation interval 2.0 s
VDD = 5 V
0.40
1.6
µA
Average Current consumption (2)
IDD2
VDD = 3 V
0.35
1.5
Average Current consumption (3)
IDD3
fSCL = 0 Hz, /INT = Hi-Z,
FOUT outputs 32 kHz, CL = 0 pF
Temp compensation interval 2.0 s
VDD = 5 V
1.1
3.1
Average Current consumption (4)
IDD4
VDD = 3 V
1.0
3.0
Average Current consumption (5)
IDD5
fSCL = 0 Hz, /INT = Hi-Z,
FOUT outputs 32 kHz, CL = 30 pF
Temp compensation interval 2.0 s
VDD = 5 V
6.1
8.1
Average Current consumption (6)
IDD6
VDD = 3 V
4.0
6.0
Average Current consumption (7)
IDD7
fSCL = 0 Hz, /INT = Hi-Z,
FOUT is stopped
Temp compensation is stopped.
VDD = 5 V
0.38
1.55
Average Current consumption (8)
IDD8
VDD = 3 V
0.33
1.45
Peak Current consumption (1)
IDD9
fSCL = 0 Hz, /INT = VDD,
FOUT is stopped
Temp compensation ON (peak)
VDD = 5 V
55
100
Peak Current consumption (2)
IDD10
VDD = 3 V
50
95
High-level input voltage
VIH1
SCL, SDA, FOE
0.8  VDD
5.5
V
VIH2
EVIN
0.8  VDD
VDD
Low-level input voltage
VIL
SCL, SDA, FOE, EVIN
GND −0.3
0.2 VDD
High-level output voltage
VOH1
FOUT, SOUT
VDD = 5 V, IOH = −1 mA
4.5
5.0
VOH2
VDD = 3 V, IOH = −1 mA
2.2
3.0
VOH3
VDD = 3 V, IOH = −100 µA
2.9
3.0
Low-level output voltage
VOL1
FOUT, SOUT
VDD = 5 V, IOL = 1 mA
GND
GND + 0.5
VOL2
VDD = 3 V, IOL = 1 mA
GND
GND + 0.8
VOL3
VDD = 3 V, IOL = 100 µA
GND
GND + 0.1
VOL4
/INT
VDD = 5 V, IOL = 1 mA
GND
GND + 0.25
VOL5
VDD = 3 V, IOL = 1 mA
GND
GND + 0.4
VOL6
SDA
VDD 2 V, IOL = 3 mA
GND
GND + 0.4
Input leakage current
ILK
INPUT pins, VIN = VDD or GND
−0.5
0.5
µA
Output leakage current
IOZ
Output pins, output voltage = VDD or GND
−0.5
0.5
Pull-up Resistor
REVIN
EVIN
125
500
2000
kΩ
Detection voltage of VDET
VDET
VDD
1.41
1.45
1.49
V
Detection voltage of VLF
VLOW
VDD
0.9
1.0
1.2

RX8804CE
Page - 5 ETM59E-05
7.2. AC Characteristics
Table 6 AC Characteristics
* Unless otherwise specified, GND = 0 V , VDD = 1.6 V to 5.5 V , Ta = −40 C to +105 C
Item
Symbol
Condition
SCL = 100 kHz
Standard Mode
SCL = 400 kHz
Fast Mode
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL
−
−
100
−
400
kHz
Start condition setup time
tSU;STA
−
4.7
−
0.6
−
µs
Start condition hold time
tHD;STA
−
4.0
−
0.6
−
µs
Data setup time
tSU;DAT
−
250
−
100
−
ns
Data hold time
tHD;DAT
−
0
−
0
−
ns
Stop condition setup time
tSU;STO
−
4.0
−
0.6
−
µs
Bus idle time between
start condition and stop condition
tBUF
−
4.7
−
1.3
−
µs
Time when SCL = ”L”
tLOW
−
4.7
−
1.3
−
µs
Time when SCL = “H”
tHIGH
−
4.0
−
0.6
−
µs
Rise time for SCL and SDA
tr
−
−
1.0
−
0.3
µs
Fall time for SCL and SDA
tf
−
−
0.3
−
0.3
µs
Allowable spike time on bus
tSP
−
−
50
−
50
ns
Timing chart
tHD ; DAT
tSU ; DAT
tHD ; STA
tLOW
tHIGH
1 / fSCL
tr
tf
tSU ; STA
SDA
SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACK
(A)
Protocol
tBUF
tSU ; STO
STOP
CONDITION
(P)
START
CONDITION
(S)
(P)
(A)
tHD ; STA
tSU ; STA
(S)
BIT 0
LSB
(R/W)
(S)
tSP
Figure 3 I2C-Bus Timing Chart
Note
1. As for the communication time of I2C-Bus, completion of less than 1 second is recommended.
If such communication requires 1 second (Max.) or longer, the I2C-Bus interface is reset by the internal bus timeout
function. When bus-time-out occur, SDA is released to Hi-Z input mode.
2. But readout data of a clock is stable anytime, and there isn’t contradiction. And it does not occur
that data of a clock delay even if access time is prolonged.

RX8804CE
Page - 6 ETM59E-05
7.3. Reference Characteristics
7.3.1 Temperature Compensation and Consumption Current
The current consumption of RX8804CE increases at a timing of a temperature compensation.
As for this peak current consumption, it occurs in about 0.7ms.
IDD1, IDD2 is the average current consumption at temperature compensation in 2 seconds cycle.
Figure 4 Temperature compensation current
7.3.2 IDD vs TC Characteristics for Reference
Table 7 Average Current consumption IDD1, IDD2
Temp. compensation interval
TC Unit s
IDD1 Typ. (VDD = 5.0 V)
Unit µA
IDD2 Typ. (VDD = 3.0 V)
Unit µA
0.5
0.46
0.40
2
0.38
0.35
10
0.38
0.33
30
0.38
0.33
7.3.3 Reference characteristic of I2C-Bus active current.
Figure 5 I2C-Bus Current consumption
0.7 ms Temp. compensation ON (peak)
IDD9,10
Temp Compensation interval (2.0 s)
IDD7,8
IDD1,2
Temp Compensation OFF
Average

RX8804CE
Page - 7 ETM59E-05
8. Use Methods
8.1. Description of Registers
8.1.1. Write / Read and Bank Select
Address 00h to 0Fh: Basic time and calendar register. It compatible with RX8803 and RX8900
Address 10h to 1Fh: Extension register
Access to more than address 20h is possible, but there is some control register for quality inspection.
Address is incremented automatically in lower 4 bits address.
Upper 4bits address are fixed. (00, ..., 0E, 0F, 00, 01), (10, ..., 1E, 1F, 10, 11)
Table 8 Register Division (00h ~ 0Fh)
Basic register
Time stamp register
Access is prohibited
Address (8bit)
0Fh from 00h
1Fh from 10h
FFh from 20h
8.1.2. Register Table (Basic time and calendar register)
Table 9 Register Table (00h ~ 0Fh)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Init
Write
00
SEC

40
20
10
8
4
2
1

01
MIN

40
20
10
8
4
2
1

02
HOUR


20
10
8
4
2
1

03
WEEK

6
5
4
3
2
1
0

04
DAY


20
10
8
4
2
1

05
MONTH



10
8
4
2
1

06
YEAR
80
40
20
10
8
4
2
1

07
RAM
•
•
•
•
•
•
•
•

08
MIN Alarm
AE
40
20
10
8
4
2
1

09
HOUR Alarm
AE
•
20
10
8
4
2
1

0A
WEEK Alarm
AE
6
5
4
3
2
1
0

DAY Alarm
•
20
10
8
4
2
1
0B
Timer Counter 0
128
64
32
16
8
4
2
1

0C
Timer Counter 1
32768
16384
8132
4096
2048
1024
512
256

0D
Control1
TEST
WADA
USEL
TE
FSEL1
FSEL0
TSEL1
TSEL0
02h

0E
Flag Register


UF
TF
AF

VLF
VDET
00h
*
0F
Control2
CSEL1
CSEL0
UIE
TIE
AIE


RESET
40h

Writing is avoided. Read value is 0, always. •It can read and write. is available. −avoid.
“Init” shows value of after power-on Reset. Unit is Hex.
*Note Refer to Flag Registers
Note
After the initial power-up (from 0 V) or in case the VLF bit returns “1” , make sure to initialize all registers, before
using the RTC.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
time data is incorrect.
-
Only a 0 can be written to the UF, TF, AF, VLF, VDET and EF bit.
The EVMON bit is read only bit.
-
Any bit marked with “”should be used with a value of “0” after initialization.
-
Any bit marked with “•” is a RAM bit that can be used to read or write any data.
-
The TEST bit is used by the manufacturer for testing. Be sure to set “0” for this bit when writing.
-
If an alarm function is not used, registers 08h-0Ah can be used as RAM. (AIE: “0”)
-
Reading register value of address 0Bh-0Ch and 1Fh is pre-set data.
If a timer function is not used, register of 0Bh-0Ch and 1Fh can be used as RAM. (TE, TIE: “0”)

RX8804CE
Page - 8 ETM59E-05
8.1.3. Register Table (Time stamp, EVIN, SOUT, Timer)
Table 10 Register Table (10h ~ 1Fh)
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Init
Write
10
Time stamp SEC

40
20
10
8
4
2
1
00h
−
11
Time stamp MIN

40
20
10
8
4
2
1
00h
−
12
Time stamp HOUR


20
10
8
4
2
1
00h
−
13
Time stamp WEEK

6
5
4
3
2
1
0
00h
−
14
Time stamp DAY


20
10
8
4
2
1
00h
−
15
Time stamp MONTH
TSVLF
TSVDET

10
8
4
2
1
00h
−
16
Time stamp YEAR
80
40
20
10
8
4
2
1
00h
−
17
EVIN set
ECP
EHL
EPU
RCE
EIE

ET1
ET0
00h

18
EVIN det
EF



EVMON



00h

19
SOUT set1
SOE7
SOE6
SOE5
SOE4
SOE3
SOE2
SOE1
SOE0
00h

1A
SOUT set2
DCE
DC


SRV
FS2
FS1
FS0
00h

1B
Timer set
TSTP
TRES






00h

1C
Timer0
128
64
32
16
8
4
2
1
00h
−
1D
Timer1
32768
16384
8192
4096
2048
1024
512
256
00h
−
1E
Timer2
8388608
4194304
2097152
1048576
524288
262144
131072
65536
00h
−
1F
Timer counter 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536
00h

Writing is avoided. Read value is 0, always. •It can read and write. is available. −avoid.
“Init” shows value of after power-on Reset. Unit is Hex.
8.1.4. Quick Reference
Table 11 Quick Reference
Update interrupt timing
Default
USEL = 0
Once per seconds

USEL = 1
Once per minutes
Output Frequency selection
FSEL1, FSEL0 = 00
32.768 kHz

FSEL1, FSEL0 = 01
1024 Hz
FSEL1, FSEL0 = 10
1 Hz
FSEL1, FSEL0 = 11
32.768 kHz
Timer source clock selection
TSEL1, TSEL0 = 00
4096 Hz
TSEL1, TSEL0 = 01
64 Hz
TSEL1, TSEL0 = 10
Every second update

TSEL1, TSEL0 = 11
Every minute update
Temperature compensation selection
CSEL1, CSEL0 = 00
0.5 s
CSEL1, CSEL0 = 01
2.0 s

CSEL1, CSEL0 = 10
10 s
CSEL1, CSEL0 = 11
30 s
8.1.5 Initial Value of Registers
Table 12 Registers Initial Value
Registers’ Initial value after power on reset
Initial Value
Register
1
TSEL1, VLF, VDET, CSEL0
0
TEST, WADA, USEL, TE, FSEL1, FSEL0, TSEL0, UF, TF, AF, EF, CSEL1, UIE, TIE, AIE, RESET,
TSVLF, TSVDET, ECP, EHL, EPU, RCE, EIE, ET1, ET0, EVMON, SOE0 ~ SOE7, DCE, DC, SRV,
FS0 ~ FS2, TRES, TSTP, All bits of address1Ch,1Dh,1Eh and 1Fh
All other register values are undefined, so be sure to perform a reset before using the module.

RX8804CE
Page - 9 ETM59E-05
8.2. Details of Registers
8.2.1. Clock Counter (SEC - YEAR)
•The data format is BCD format. For example, when the “seconds” register value is “0101 1001” it indicates 59 seconds.
24hours system is available.
Table 13 Clock, Calendar Register
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00
SEC

40
20
10
8
4
2
1
01
MIN

40
20
10
8
4
2
1
02
HOUR


20
10
8
4
2
1
03
WEEK

6
5
4
3
2
1
0
04
DAY


20
10
8
4
2
1
05
MONTH



10
8
4
2
1
06
YEAR
80
40
20
10
8
4
2
1
1) SEC register
This second register counts from “00”to “01”, “02”, and up to 59 seconds, after 59 it starts again from 00 second.
When written any data to SEC register, less than a SEC counter (512 Hz from 2 Hz) is cleared to zero.
Thus, the time accuracy becomes 0 s to 30.5 s. * (refer to Figure 6)
If highly precise time synchronization is needed, RESET bit setting to 1 is most suitable operation.
When 60 seconds were written to SEC register, it returns to 00 second in next update. This special update is the
same as plus-adjustment of Leap second. This behavior is useful in the adjustments of Leap second.
*Note Several data writing into SEC register might cumulative time delay.
2) MIN register
This minute register counts from “00”to “01”, “02”, and up to 59 minutes, after 59 it starts again from 00 minute.
3) HOUR register
This 24 hours register counts from “00”hour to “01”, “02”, “23”, ”00”, ”01”. “o”indicates write-protected bits. Zero is
always read from these bits.
4) WEEK register
This WEEK register consists of 7bit shift registers.
The data values are counted as follows: Day 01h → Day 02h → Day 04h → Day 08h → Day 10h → Day
20h → Day 40h → Day 01h → Day 02h
The correspondence between days and count values is shown below.
Table 14 WEEK Register
WEEK
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Day of week
Data h
Write / Read
0
0
0
0
0
0
0
1
Sunday
01h
0
0
0
0
0
0
1
0
Monday
02h
0
0
0
0
0
1
0
0
Tuesday
04h
0
0
0
0
1
0
0
0
Wednesday
08h
0
0
0
1
0
0
0
0
Thursday
10h
0
0
1
0
0
0
0
0
Friday
20h
0
1
0
0
0
0
0
0
Saturday
40h
Write prohibit
Do NOT set “1” more than one day at the same time.
Also, note with caution that any setting other than the
seven shown above should not be made as it may
interfere with normal operation.
−
−
5) DAY Register
The updating of DAY register varies according to the month setting.
A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96).
In February of a leap year, the counter counts dates from “01”, “02”, “03”, to “28”, “29”, “01”.
Table 15 DAY Register
DAY
Month
Date update pattern
Write / Read
1, 3, 5, 7, 8, 10, or 12
01, 02, 03 30, 31, 01 
4, 6, 9, or 11
01, 02, 03 30, 01, 02 
February in common year
01, 02, 03 28, 01, 02 
February in leap year
01, 02, 03 28, 29, 01 

RX8804CE
Page - 10 ETM59E-05
3) MONTH register
This MONTH register counts from 01 (January), 02 (February), and up to 12 (December), then starts again
since 01 (January).
4) YEAR register
This YEAR register counts from 00, 01, 02 and up to 99, then starts again since 00.
Any year multiple of four (04, 08, 12, 88, 92, 96, etc.) works as a leap year.
< Definition of leap years >
Leap year: year divisible by 4, year divisible by 400
Ex. 2000, 2004, 2008, 2012, 2096, 2400, 2800
Common year: year indivisible by 4, year divisible by 100
Ex. 2001, 2002, 2003, 2005, 2099, 2100, 2200, 2300, 2500
Figure 6 Internal clock distribution diagram
8.2.2. Alarm Registers
Table 16 Alarm registers
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
08
MIN Alarm
AE
40
20
10
8
4
2
1
09
HOUR Alarm
AE
•
20
10
8
4
2
1
0A
WEEK Alarm
AE
6
5
4
3
2
1
0
DAY Alarm
•
20
10
8
4
2
1
0D
Control1
TEST
WADA
USEL
TE
FSEL1
FSEL0
TSEL1
TSEL0
0E
Flag Register


UF
TF
AF

VLF
VDET
0F
Control2
CSEL1
CSEL0
UIE
TIE
AIE


RESET
The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date,
day, hour, and minute values
When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin goes to
low level and “1”is set to the AF bit to report that an alarm interruption has occurred
Please refer to Alarm Interrupt Function
Sec counter
Min counter
Hour counter
Day counter
Month counter
Year counter
Week
counter
32.768 kHz
crystal
C1 C2 C3 C4,,, Cn
Capacitors Array Selection
Parabolic Compensation
Temperature Sensor
Temp. Sense period selection
0.5 sec, 2 sec, 10 sec, 30 sec
32.768 kHz
1/2 divider chain 16384 Hz, 8192 Hz,,, 1024Hz, 2Hz,
4Hz
1Hz
FOUT
selector
FOUT
Reset
3kinds of reset are available
1.RESET bit is set to 1.
2.SEC register(00h) is reset to 0.
3.Power on Reset

RX8804CE
Page - 11 ETM59E-05
8.2.3. Wakeup Timer Control Registers
Table 17 Wakeup Timer Control Registers
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
Write
0B
Timer Counter 0
128
64
32
16
8
4
2
1


0C
Timer Counter 1
32768
16384
8192
4096
2048
1024
512
256


1B
Timer set
TSTP
TRES








1C
Timer0
128
64
32
16
8
4
2
1

1D
Timer1
32768
16384
8192
4096
2048
1024
512
256

1E
Timer2
8388608
4194304
2097152
1048576
524288
262144
131072
65536

1F
Timer Counter 2
8388608
4194304
2097152
1048576
524288
262144
131072
65536


These registers are used to set the preset countdown value for the wakeup timer interrupt function.
The TE, TF, TIE, and TSEL0 / 1 bits are also used to set the wakeup timer interrupt function.
When the value in the above wakeup timer control register just changes from 01h to 00h, the /INT pin goes
to low level and “1”is set to the TF bit to report that a wakeup timer interrupt event has occurred.
Please refer to Wakeup timer Control function
8.2.4. Control Registers, Flag Registers
Table 18 Control Register, Flag Register
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0D
Control1
TEST
WADA
USEL
TE
FSEL1
FSEL0
TSEL1
TSEL0
(Default)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(0)
0E
Flag register


UF
TF
AF

VLF
VDET
(Default)
(0)
(0)
(0)
(0)
(0)
(0)
(1)
(1)
0F
Control2
CSEL1
CSEL0
UIE
TIE
AIE


RESET
(Default)
(0)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
•The default value is loaded after powering up from 0 V, automatically.
•TEST must be always cleared by a zero.
•This register is used to specify the target for the alarm function or time update interrupt function and to
select or set operations such as wakeup timer operations.
1) TEST bit
This is the manufacturer's test bit. Its value should always be “0”.
Be careful to avoid writing “1”to this bit when writing to other bits.
Table 19 Test bit
TEST
Data
Description
Write
0
TEST bit is cleared to 0
1
Setting prohibited (manufacturer's test bit)
Read
0
TEST bit has been cleared to 0
1
TEST bit has been set to 1. Please reset to 0
2) VLF (Voltage Low Flag) bit
This flag bit indicates the history of clock operations due to low voltage.
Its value change from “0” to “1” indicates a possibility of data loss or time data error, and all the data of registers
should be initialized.
Once this flag bit's value is “1”, its value is retained until a “0” is written to it.
After powering up from 0 V, make sure to set this bit's value to “1”.
Please refer to 8.10. Backup and Recovery.
Table 20 VLF bit
VLF
Data
Description
Write
0
The VLF bit is cleared to 0 to prepare for the next status detection
1
VLF data remains even it was 0 or 1. To retain the data, please write 1
Read
0
No supply voltage drops occurred
1
Low voltage has been detected, so data loss might have occurred, and time
information might be wrong
All registers should be initialized

RX8804CE
Page - 12 ETM59E-05
3) VDET (Voltage Detection Flag) bit
This flag bit indicates the history of the voltage for temperature compensation circuit.
Its value changes from “0” to “1” indicates that the temperature compensation function has stopped operation due
to a supply voltage drop. Once this flag bit's value is 1, its value is retained until a 0 is written to it.
After powering up from 0 V, make sure to set this bit's value to “1”. Please confirm table in 8.11. Backup and
Recovery.
Table 21 VDET bit
VDET
Data
Description
Write
0
The VDET bit is cleared to 0 to prepare for the next low voltage detection
1
VDET data remains even it was 0 or 1. To retain the data, please write 1
Read
0
Temperature compensation is normal
1
Temperature compensation has been stopped
4) RESET bit
When highly precise synchronization of both time, timer is necessary, use RESET.
Table 22 RESET bit
RESET
Data
Description
Write
0
Writing 0 is invalid
1
Writing 1 resets 16384 Hz ~2 Hz of 32.768 kHz counter (Refer to Figure 6)
Read
0
The read value of RESET is 0, always
writes 0, it is invalid
1
writes 1, it executes reset of count-down-chain from 32.768kHz
The detailed function of RESET.
For example.
S is start condition. P is stop condition.
[ Write access to RESET-bit.]
S---Slave address(w)---ACK1---0Fh---ACK2---01h---ACK3---P.
RESET executes and it keeps between P from ACK3.
After P, RESET bit clears automatically.
reset area of circuit are the count-down-chain of 2 Hz from 16 kHz, are cleared.
As for next update timing of a Seconds counter from RESET.
That range is 1000 ms-30.5 s from just 1000 ms.
RESET affects time update interruption, alarm, FOUT and timer.
But it doesn't affect 32 kHz output.
Note:
RESET is released by the reception of a START or RE-START condition before receiving a STOP condition.
The Single write access is recommended for precise RESET.
Unnecessary use of RESET will be the cause of delay error of time.
5) USEL (Update Interrupt Select) bit
This bit is used to define if the RTC should output a “second update”or “minute update”interrupt, allowing to
synchronize external clocks with the time registers of the RTC.
Please refer to 8.6. Time Update Interrupt Function
6) TSEL0, 1 (Timer Select 0, 1) bits
The combination of these two bits is used to set the countdown period (source clock) for the wakeup timer
interrupt function (four settings can be made).
Please refer to 8.3. Wakeup Timer Function

RX8804CE
Page - 13 ETM59E-05
7) FSEL0, 1 (FOUT frequency Select 0, 1) bits
The combination of these two bits is used to set the FOUT frequency.
Note: All frequencies are temperature compensated!
Table 23 FSEL bit
FSEL0,1
FSEL1
(bit 3)
FSEL0
(bit 2)
FOUT frequency
Write / Read
0
0
32.768 kHz Output Default
0
1
1024 Hz Output
1
0
1 Hz Output
1
1
32.768 kHz Output
8) CSEL0, 1 (Compensation interval Select 0, 1) bits
The combination of these two bits is used to set the temperature compensation interval.
Please refer to 8.9. Temperature Compensation Function
9) AF (Alarm Flag) bit
If set to “0” beforehand, this flag bit's value changes from “0” to “1” when an alarm interrupt event has occurred.
Once this flag bit's value is “1”, its value is retained until a “0” is written to it.
Please refer to 8.5. Alarm Interrupt Function.
10) TF (Timer Flag) bit
If set to “0” beforehand, this flag bit's value changes from “0” to “1” when a wakeup timer interrupt event has
occurred. Once this flag bit's value is “1”, its value is retained until a “0” is written to it.
Please refer to 8.6. Wakeup Timer Interrupt Function.
11) UF (Update Flag) bit
If set to “0” beforehand, this flag bit's value changes from “0” to “1” when a time update interrupt event has
occurred. Once this flag bit's value is “1”, its value is retained until a “0” is written to it.
Please refer to 8.7. Time Update Interrupt Function.
12) AIE, TIE, UIE (Alarm, Wakeup Timer, Update Interrupt Enable) bit
In case of Alarm or Wakeup Timer or Update occurs AIE, TIE, UIE bit controls /INT output.
When a “1” is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) .
When a “0” is written to this bit, no interrupt signal is generated.
Please refer to each function.
Table 24 AIE, TIE, UIE bit
Function
condition
Flag
/INT interrupt control
Alarm
Alarm time hit
AF
AIE
Wakeup Timer
Timer Count down to 0
TF
TIE
Update
Minute or Second update
UF
UIE
8.2.5. SOUT Control Register
Table 25 SOUT Control Register
Address
Function
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Read
Write
19
SOUT set1
SOE7
SOE6
SOE5
SOE4
SOE3
SOE2
SOE1
SOE0


1A
SOUT set0
DCE
DC


SRV
FS2
FS1
FS0


1) SOUT set1 register (19h)
By setting 69h =01101001b into SOUT set1 SOUT function becomes activated.
Other data than 69h makes SOUT function non active. Then SOUT becomes Hi-Z.
2) DCE bit ((Direct Control Enable), DC bit (Direct Control)
In case of DCE=1, DC bit Value is outputted at SOUT.
In case of DCE=0, register value Flag value is outputted at SOUT.

RX8804CE
Page - 14 ETM59E-05
Table 26 DCE, DC bit
DCE
DC
SOUT output
0
0
Flag value decided by SRV, FS2, FS1, FS0
0
1
1
0
SOUT = Low, SRV bit is ignored
1
1
SOUT = High, SRV bit is ignored
3) SRV bit (SOUT Reverse)
SOUT output reverse.
Each Flag register is high active. In case of SRV = 1, IT becomes low active.
Table 27 SRV bit
SRV
SOUT Output
0
Flag Value
1
Inverse value of Flag Value
4) FS0,1,2 bit
Flag selection bits. SOUT set1 should be active.
Table 28 FS bit
DCE
FS2
FS1
FS0
Selected Flag
SOUT
SRV = 1
SRV = 0
0
0
0
0
TF
Inversion of TF
TF
0
0
0
1
AF
Inversion of AF
AF
0
0
1
0
UF
Inversion of UF
UF
0
1
1
1
EF
Inversion of EF
EF
0
1
0
0
VDET
Inversion of VDET
VDET
0
1
0
1
VLF
Inversion of VLF
VLF
0
Other value than
above combination
----
Low
1
----
----
DC
Selected Flag register value by FS2,1, 0 is outputted at SOUT.
Output data is inversed by SRV bit.
Other FS2, 1, 0 combination makes SOUT low.
By this function RTC module inner status ex. VLF is outputted to external controller device.
8.2.6. Time Stamp Data Event Controller Register
Table 29 Time Stamp Data Event Control
Address
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Read
Write
10
Time stamp SEC

40
20
10
8
4
2
1

−
11
Time stamp MIN

40
20
10
8
4
2
1

−
12
Time stamp HOUR


20
10
8
4
2
1

−
13
Time stamp WEEK

6
5
4
3
2
1
0

−
14
Time stamp DAY


20
10
8
4
2
1

−
15
Time stamp MONTH
TSVLF
TSVDET

10
8
4
2
1

−
16
Time stamp YEAR
80
40
20
10
8
4
2
1

−
17
EVIN set
ECP
EHL
EPU
RCE
EIE

ET1
ET0


18
EVIN det
EF



EVMON





is available. −is not available.

RX8804CE
Page - 15 ETM59E-05
1) Time stamp SEC ~ YEAR
In case of trigger input detection from EVIN terminal, Clock and calendar data are recorded in Time
stamp SEC ~ YEAR.
2) TSVLF, TSVDET bit (Time stamp VLF, Time stamp VDET)
In case of trigger input detection from EVIN terminal, VLF bit is recorded to TSVLF, VDET bit to TSVDET.
3) ECP bit (Event capture Enable)
ECP enables Time Stamp function.
Table 30 ECP bit
ECP
Data
Function
Write / Read
0
Time stamp is disabled
1
Time stamp is enabled
Time stamp data are overwritten by latest time stamp data
4) EHL bit (EVIN pin, High / Low detection select)
Selection bit of EVIN Voltage level.
Table 31 EHL bit
EHL
Data
Function
Write / Read
0
EVIN pin detects active Low level
1
EVIN pin detects active High level
5) EPU bit (Enable Pull-up register)
EPU enables Pull-up-resistor of EVIN input terminal.
Table 32 EPU bit
EPU
Data
Function
Write / Read
0
Pull-up resistor is disabled
1
Pull-up resistor is enabled
6) RCE bit (Repeat Capture Enable)
RCE enables repeated times stamp capture.
Table 33 RCE bit
RCE
Data
Function
Write / Read
0
After time stamp, ECP bit is cleared to 0 automatically and Time stamp is not
executed, till ECP is set to 1 again
1
Repeated Time stamp is enabled
After a Time stamp execution, ECP is not cleared to 0
Time stamp is executed in every event detection and overwrites to Timestamp
register
7) EF bit (Event trigger Flag)
History bit of EVIN trigger.
Table 34 EF bit
EF
Data
Function
Write
0
/INT Low output is cleared to Hi-Z
1
The value of EF bit remains even EF = 0 or EF = 1
To keep the EF bit value, please write 1 to EF bit
Read
0
There is no EVIN detection history
1
There is EVIN detection history