Epson RX4111CE Instructions for use
Real Time Clock Module
RX4111CE
Application manual
ETM62E Revision History
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NOTICE：PLEASE READ CAREFULLY BELOW BEFORE THE USE OF THIS DOCUMENT
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
ETM62E Revision History
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Rev. No.
Date
Page
Description
Note is added the Metal pad of package.
5.1. External Dimensions
VVLF characteristics was added.
"7. Recommended Operating Conditions"
AC characteristics of VDD=1.8V was updated.
Note and comment was updated for SPI control.
"9.2. AC characteristics"
As for time of auto release of timer interruption, Symbol name was
updated to tRTN2 from tRTN. "TSEL1, TSEL0 bit"
tiThe symbol of tRTN was separated to tRTN1 and tRTN2.
As for time of auto release of Time update interruption, Symbol name was
updated to tRTN1 from tRTN.
The symbol of tRTN was separated to tRTN1 and tRTN2.
Auto release time of Time update interruption was corrected.
, from 7.57 ms.
"14.4. Time Update Interrupt Function"
"Table 37 UIE bit (Update Interrupt Enable)"
"Figure 1 Time Update Interruption Timing Chart" has been revised.
When UF is cleared, /INT returns to Hi-Z, Immediately.
"Note in using small EDLC " is deleted.
Even if using small EDLC, This note desn't need. Page42
Bypass capacitor value was corrected.
0.1 from 1.0 " 15.Connection example"
Contacts list was updated. "Contacts"
The link to index was added to the all footer.
INDEX
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ETM62E Revision History..................................................................................................2
INDEX................................................................................................................................3
1. Overview........................................................................................................................5
2. Block Diagram ...............................................................................................................5
3. Terminal Description......................................................................................................6
3.1. Terminal Connections.......................................................................................................................6
3.2. Pin Functions....................................................................................................................................6
4. Connection Example......................................................................................................7
4.1. Battery Switchover Connection Examples........................................................................................7
5. External Dimensions / Marking Layout...........................................................................8
5.1. External Dimensions.........................................................................................................................8
5.2. Marking Layout.................................................................................................................................8
6. Absolute Maximum Ratings ...........................................................................................9
7. Recommended Operating Conditions ............................................................................9
8. Frequency Characteristics .............................................................................................9
9.Electrical Characteristics.............................................................................................10
9.1. DC characteristics...........................................................................................................................10
9.1.1. DC characteristics ............................................................................................................10
9.1.2. Chargeable Current Characteristics .................................................................................11
9.1.3. Reference Value of Switching Element ............................................................................11
9.2. AC characteristics...........................................................................................................................12
9.2.1. AC Characteristics (1) ......................................................................................................12
9.2.2. AC Characteristics (2) ......................................................................................................13
10. Interface timing when power ON / OFF....................................................................13
10.1. Restrictions of SPI-Bus interface in the power ON / OFF. ............................................................13
10.2. VDD and CE Timing at Power On ..................................................................................................14
10.3. Reset by Software ........................................................................................................................15
11. Reference information................................................................................................16
11.1. Reference Data.............................................................................................................................16
12. Application notes........................................................................................................17
13. Overview of Functions and Registers.........................................................................18
13.1. Overview of Functions ..................................................................................................................18
13.2. Register Table ..............................................................................................................................19
13.2.1. Register Table................................................................................................................19
13.2.2. Register Initial value, And Read/Write Operation Table .................................................21
13.3. Description Of Registers...............................................................................................................23
13.3.1. Clock and Calendar Counter (Bank1 - 1h ~ 6h).............................................................23
13.3.2. Timer Setting and Timer Counter Register (Bank1 - Ah ~ Ch).......................................23
13.3.3. Alarm Registers (Bank1 –7h ~ 9h, Bank2 - Ch)............................................................23
13.3.4. Function-Related Register (Bank1 - 1Dh ~ 1Fh) ............................................................23
13.3.5. Power Switching Circuit-Related Register Bank3 02h .................................................24
13.3.6. Time stamp-related register............................................................................................24
13.3.7. RAM registers (Bank4, 5, 6, 7) ......................................................................................24
14. How to use.................................................................................................................25
14.1. Clock Calendar Explanation..........................................................................................................25
INDEX
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14.1.1. Clock Counter.................................................................................................................25
14.1.2. Week Counter.................................................................................................................26
14.1.3. Calendar Counter...........................................................................................................26
14.2. Wake-up Timer Interrupt Function................................................................................................27
14.2.1. Related Registers For Function Of Wake-up Timer Interrupt Function...........................27
14.2.2. Wake-up Timer Start Timing...........................................................................................30
14.2.3. Interruption period of wake-up Timer..............................................................................30
14.2.4. Diagram of Wake-up Timer Interrupt Function................................................................31
14.3. Alarm Interrupt Function ...............................................................................................................32
14.3.1. Related Registers for Alarm Interrupt Functions.............................................................32
14.3.2. Examples Of Alarm Settings...........................................................................................33
14.4. Time Update Interrupt Function....................................................................................................35
14.4.1. Related Registers For Time Update Interrupt Functions. ...............................................35
14.4.2. Time Update Interrupt Function Diagram .......................................................................36
14.5. Status Monitoring Function...........................................................................................................37
14.5.1. Related Registers For Status Monitoring........................................................................37
14.6.FOUT Function [Clock Output Function].......................................................................................38
14.6.1. FOUT Control Register...................................................................................................38
14.6.2. FOUT Function Table.....................................................................................................38
14.7. Battery Backup Switchover Function............................................................................................39
14.7.1. Description of Battery Backup Switchover Function .......................................................39
14.8. Time Stamp Function....................................................................................................................43
14.8.1. Description Of Time Stamp Function..............................................................................43
14.8.2. Related Registers For Time Stamp Functions................................................................43
14.8.3. Time Stamp function triggered by SPI Access................................................................45
14.8.4. Time Stamp Record Register. ........................................................................................46
14.8.5. RTC Self Monitoring Time stamp Function.....................................................................47
14.8.6. Time Stamp Record Register .........................................................................................47
14.8.7. Multiple Time Stamp.......................................................................................................48
14.9. Flow Chart ....................................................................................................................................50
14.10. Reading/Writing Data via the SPI-Bus Interface.........................................................................56
14.10.1 Write / Read and Bank Select........................................................................................56
14.10.2 Write of Data..................................................................................................................56
14.10.3 Read of Data .................................................................................................................56
15. Connection example..................................................................................................57
16.Tables.........................................................................................................................58
17.Figures........................................................................................................................59
Contacts ..........................................................................................................................60
1. Overview
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Built-in frequency adjusted 32.768 kHz crystal unit
Interface Type : SPI-Bus 4 wire, 4 MHz Max.
Low current consumption at backup
Wide operating voltage range : 1.6Vto5.5V
Wide time-keeper voltage range : 1.1Vto5.5V
Auto power switching function : Automatically switches to backup power supply
by monitoring the VDD voltage.
Time stamp function : 8 times time-stamp,1/256 seconds with many selectable trigger.
Time stamp memory can be used as users memory; 512 bit, 64 word x 8 bit
Alarm interruption : Day, date, hour, minute, second
The various functions include full calendar, seconds alarm, wake-up timer, and 32.768 kHz output
Self monitoring function : Voltage detection, Crystal oscillation stop, etc.
RX4111CE is a real-time clock module with integrated 32.768 kHz crystal oscillator and SPI-Bus interface. In addition to
providing a calendar (year, month, date, day, hour, minute, second), this module provides other functions including time-
stamp from 1/1024 second to year, alarm, wake-up timer, time update interruption, and 32.768 kHz output. Time stamp
function can record maximum of 8 events. Using the backup battery switch control function and the interface power supply
input pin, RX4111CE can support various power supply circuits. All of the functions mentioned above are offered in a thin
and compact 3.2 x 2.5 ceramic package which could be used in various applications requiring small footprints.
FOUT
VBAT
GND
Bus
Interface
Register
Control
(System
Control)
RTC Main Circuit
32 kHz
to
1 kHz
Divider
512 Hz
to
1Hz
Divider
Clock
and
Calendar
CLK
CE
VDD
VIO
(VDET)
VDD
Detector
OSC
32.768 kHz
Timer
Register
Interrupts
Controller
/INT
User RAM
Event
Controller
I/O
internal
VDD
DI
DO
Alarm, Timer,
Update, Event
FOUT,
Timer
FOUT Controller
Figure 2 Block Diagram
Low Power Real Time Clock Module with SPI-Bus Interface and Time Stamp Function
RX4111CE
3. Terminal Description
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3.1. Terminal Connections
RX4111CE
1.
VDD
10.
/INT
2.
VBAT
9.
GND
3.
DI
8.
VIO
4.
FOUT
7.
CE
5.
CLK
6.
DO
Figure 3 Package Pin Layout
3.2. Pin Functions
Table 1 Pin Description
Signal
name
I/O
Function
CE
Input
CLK
Input
Serial clock input pin (SCLK)
DI
Input
DO
Output
FOUT
Output
/INT
Open-Drain
Output
This pin is used to output alarm signals, timer signals, time update signals, and other
signals. This pin is an N-ch open drain
VDD
VIO
VBAT
GND
Ground pin
Note:
DD and GND.
For the input terminals, it is permitted for the input to be 5.5 V regardless of the VIO voltage.
For the Open-Drain pin, it is permitted for the pull-up to be 5.5 V regardless of the VIO voltage.
When FOUT or INT is not used, be left open in these pins. It doesn't need pull-Up/Down resistor.
4. Connection Example
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4.1. Battery Switchover Connection Examples
Note. When connecting an outside power supply or a large-sized battery to VBAT,
Install bypass capacitors more than 0.1 F in a VBAT terminal if necessary.
As for each of bypass-capacitor, Install nearest in each of pin as much as possible.
EX.1 VIO and VDD are different. Ex.2 VIO and VDD are the same.
Figure 4 Circuit Ex.1
Figure 5 Circuit Ex.2
Ex.3 Connecting a Non RE-Chargeable battery Ex.4 Not using power-switch function
Figure 6 Circuit Ex.3
Figure 7 Circuit EX.4
VDD
VBAT
VIO
1.8 V
3.3 V
I= V/R < 40 mA
0.1 F
0.1 F
Re-chargeable
Battery
EDLC
or
INIEN = 1
VDD
VBAT
VIO
Non-Re-chargeable
battery
3.3 V
I = V/R > 1 mA
0.1 F
INIEN = 1
VDD
VBAT
VIO
Re-chargeable
Battery
3.3 V
EDLC
or
I = V/R < 40 mA
0.1F
INIEN = 1
VDD
VBAT
VIO
3.3 V
0.1 F
INIEN = 0
SWSEL1 = 1
SWSEL0 = 0
5. External Dimensions / Marking Layout
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5.1. External Dimensions
RX4111CE
External Dimensions Recommended soldering pattern
Unit : mm
"CE"PKGRev.05
1.0Max.
0.7
0.3
0.62
0.42
0.2Min
.
0.4
0.7
0.4
0.9
1.1
0.3
3.2 0.2 (Typ.3.24)
2.5±0.2 (Typ.2.54)
0.35
*1
＊1. The metal pads on the short side of the 1st and 10th pins of the
package are inspection pads for the crystal unit.
For stable oscillation, make sure that leakage current due to
condensation or dust does not occur between these pads.
The metal pads on the short side of the 5-pin and 6-pin sides are not
connected inside the RTC.
Figure 8 External dimensions
5.2. Marking Layout
RX4111CE
#1 Pin Mark
Logo
Production lot
R4111X
123A
Frequency Tolerance
A : A
B : None
Type
Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and
positioning.
Figure 9 Marking layout
6. Absolute Maximum Ratings
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Table 2 Absolute Maximum Ratings
GND=0V
Item
Symbol
Condition
Rating
Unit
Supply voltage
VDD
0.3
+6.5
V
Backup supply voltage
VBAT
0.3
+6.5
V
Interface
supply voltage
VIO
0.3
+6.5
V
Input voltage
VIN
CE, CLK, DI
0.3
+6.5
V
Output voltage 1
VOUT1
/INT
0.3
+6.5
V
Output voltage 2
VOUT2
FOUT, DO
-0.3
VIO+0.3
V
Storage temperature
TSTG
When stored separately,
without packaging
55
to
+125
C
Table 3 Recommended Operating Conditions
Unless otherwise specified, GND=0V,Ta=40Cto+85C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating supply voltage
VDD
Normal operation mode (VDD)
1.25
3.0
5.5
V
Interface supply voltage
VIO
VDD=1.6V 5.5V
1.6
3.0
5.5
V
Clock supply voltage
VCLK
Backup operation mode (VBAT)
VVLF
3.0
5.5
V
VLF detection voltage
V VLF
Low voltage detection of supply Voltage.
-
-
1.1
V
Operating temperature
T_use
No condensation
40
+25
+85
C
Table 4 Frequency Characteristics Unless otherwise specified, VBAT = VDD = VIO = 1.6V 5.5 V, Ta = -40
C +85
C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Oscillation
Frequency
fo
32.768
kHz
Frequency
Tolerance
f/f
Ta=+25C
VDD=3.0V
11.5 *1
23.0 *2
106
106
Frequency/voltage
characteristics
f/V
Ta=+25C
VDD=1.1V5.5V
2
+2
106/V
Frequency/
Temperature
characteristics
fo-TC
Ta=20C+70C
VDD=3.0V;+25C reference
120
+10
106
Oscillation
Start-up time
tSTA
VDD=1.6V5.5V
1.0
s
Aging *3
fa
Ta=+25CVDD=3.0V
First year
5
+5
106
/year
1 Equivalent to 30 seconds per month deviation.
2 Equivalent to 60 seconds per month deviation.
*3 Aging stability is estimated from environmental reliability tests; expected amount of the frequency variation.
This does not intend to guarantee the product-life cycle.
9. Electrical Characteristics
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Electrical Characteristics
9.1. DC characteristics
9.1.1. DC characteristics
Table 5 DC characteristics
Unless otherwise specified, V
BAT
= V= V
IO
= 1.6 V 5.5 V, Ta = -40 C to +85 C
,
Ta=40C +105C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Current
consumption 1
IDD
CE = Low,
FOUT = OFF, /INT = OFF,
VDD = VIO = 3.0 V
INIEN = 0b
100
450
nA
Current
consumption 2
I32k
CE = Low
FOUT = 32.768 kHz, /INT = OFF
VDD = VIO = 3.0 V
FOUT pin CL = 15 pF
INIEN = 0b
2.0
3.0
A
Current
Consumption 3
IBAT
CE = Low,
VBAT = 3.0 V, VDD = VIO = 0.0 V
110
450
nA
Detection voltage of
VDD rise up
+VDET1
Switch voltage of V from V
1.25
1.35
1.45
V
Detection voltage of
VDD fall down
-VDET1
Switch voltage of V from V
1.20
1.30
1.40
V
High Input voltage
VIH
CE, CLK, DI
0.8 VIO
5.5
V
Low Input voltage
VIL
CE, CLK, DI
GND 0.3
0.2 VIO
V
High Output voltage
VOH1
FOUT,
DO
VIO = 5.0 V, IOH = -1 mA
4.5
5.0
V
VOH2
VIO = 3.0 V, IOH = -1 mA
2.2
3.0
VOH3
VIO = 3.0 V, IOH =-100 A
2.9
3.0
Low Output voltage
VOL1
FOUT,
DO
VIO = 5.0 V, IOL =1 mA
GND
GND+0.5
V
VOL2
VIO = 3.0 V, IOL = 1 mA
GND
GND+0.8
VOL3
VIO = 3.0 V, IOL=100 A
GND
GND+0.1
VOL4
/INT
VIO = 5 V, IOL = 1 mA
GND
GND+0.25
V
VOL5
VIO = 3 V, IOL = 1 mA
GND
GND+0.4
Input leakage current
ILK
Exclude CE
VIN=VIO or GND
0.1
0.1
A
ILKPD
CE, VIN= GND
0.1
0.1
Output leakage current
IOZ
FOUT, DO,
Output voltage = VIO or GND
0.1
0.1
A
VDD and VBAT
SW = OFF leak current
ISW
VBAT = 3.0 V、VDD = 0.0 V
50
nA
VBAT and VDD
SW = ON
resistance
ISWON1
VDD and VBAT SW = ON
＋0.1 V, VBAT=5.5 V , VDD=5.4 V
＋0.1 V, VBAT=3.0 V , VDD=2.9 V
RSWON1 = 125 ～750
133
-
800
A
Input Resistance
RDWN
CEpin
VIN=VIO
VIO=5 V
75
150
300
VIO=3 V
150
300
600
9. Electrical Characteristics
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9.1.2. Chargeable Current Characteristics
Figure 10 Chargeable current of VBAT (VDD = 3.0 V)
Figure 11 Chargeable Current of VBAT (VDD = 5.5V)
Figure 12 Circuit of charge to Re-chargeable Battery
9.1.3. Reference Value of Switching Element
Table 6 Reference value of switching element
Item
Characteristics
Condition
Current tolerance
40 mA Max.
SW = ON +25 °C
Diode Vf
0.60 V / 1 mA Typ.
0.85 V / 10 mA Typ.
VDD = 3.0 V, +25 °C
Diode IR
5 nA (Max.)
VR = 5.5 V, -40 °C +85 °C
Charge current into VBAT should be less than 40 mA.
VDD =3.0 VVdif (V) vs Ichg (mA)
VDD =5.5 VVdif (V) vs Ichg (mA)
(V)
9. Electrical Characteristics
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9.2. AC characteristics
9.2.1. AC Characteristics (1)
Table 7 AC Characteristics
Unless otherwise specified, GND = 0 V, VIO = 1.6 V 5.5 V, Ta = -40 C +85 C
Item
Symbol
Condition
VDD = 1.8 V 0.2 V
VDD = 3.0 V 10 %
VDD = 5.0 V 10 %
Unit
Min.
Max.
Min.
Max.
Min.
Max.
CLK clock cycle
tCLK
1000
－
332
－
250
－
ns
CLK H pulse width
tWH
450
－
166
－
125
－
ns
CLK L pulse width
tWL
450
－
166
－
125
－
ns
CLK rise and fall time
tRF
－
100
－
50
－
40
ns
CLK setup time
tCLKS
100
－
30
－
30
－
ns
CE setup time
tCS
400
－
150
－
130
－
ns
CE hold time
tCH
400
－
200
－
100
－
ns
CE recovery time
tCR
500
－
200
－
150
－
ns
CE rise and fall time
tCERF
100
－
50
－
40
s
Write data setup time
tDS
200
－
50
－
40
－
ns
Write data hold time
tDH
200
－
50
－
40
－
ns
Read data delay time
tRD
=50pF
0
400
－
150
－
110
ns
DO output disable time
tRZ
=50pF
=10k
0
400
－
120
－
110
ns
DI/DO conflict avoiding time
tZZ
0
－
0
－
0
－
ns
10 for
Timing chart
CLK
C E
tCLKS
tWH
tWL
tCH
tCR
Read
D I
tDS
Write
tDH
M 3
M 2
A 0
80 %
20 %
tRF
tRF
D O
D 7
D 6
D 0
Hi-Z
D I
M 3
M 2
A 0
D 7
D 0
tCLK
D 6
D O
Hi-Z
tWCE
tRZ
tZZ
tRD
tCS
tCERF
tCERF
1 or 0 *1
1 or 0 *1
Figure 13 SPI-Bus Timing Chart
Note: When writing data, it writes the data at CLK rise after received 8 bits of data in one time.
If communication is interrupted before receiving 8 bits data, data will not be written.
*1: Even if CE is Low, DI pin is active. Don't input half voltage and don't left open DI.
10. Interface timing when power ON / OFF
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9.2.2. AC Characteristics
Table 8 FOUT symmetry Unless otherwise specified､GND=0 V , VIO = 1.6 V 5.5 V , Ta= -40 C +85 C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
FOUT symmetry
SYM
50 % VIO Level
40
60
%
10.1. Restrictions of SPI-Bus interface in the power ON / OFF.
tR1 is needed for a proper power-on reset. If this power-on condition cannot be kept, it is necessary to reset the device by means
of a software command.
After all power-OFF, keep VDD = VBAT = GND for more than 10 seconds for a proper power-on reset by cold start.
When cannot it, please initialize the RTC by software.
The backup period against this standard does not indicate the noise characteristics with respect to the power supply.
The backup period should be long enough (60 seconds or more).
VDD, VBAT *3
VCLK
GND
Power supply VDD,VBAT
tR1
+VDET *1
Backup mode
tCL *2
tCU
-VDET
+VDET
SPI
Access is enabled
VBAT
Access is disabled
VDD
Access is
enabled
Figure 14 Power on Sequence
Table 9 Power up down characteristics
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Initial power supply rise
time
tR1
From GND to VDD = +VDET1
5 V
0.1
-
10
ms / V
3 V
0.5
-
10
ms / V
Access wait time
(Initial power on)
tCL
After arrival to VDD = 1.6 V
30
-
-
ms
Backup switchover start
wait time
tCD
After the access end
0
-
-
ms
Power supply fall time
tF
From VDD to VDD = -VDET1
1
-
-
ms / V
Power supply rise time
(Recovery from Backup)
tR2
Recovery to the operating voltage
0.1
-
-
ms / V
Access wait time
(Recovery from Backup)
tCU
The time from Recovery from
Backup to access start
40
-
-
ms
1 Power-on reset is performed at the rising edge of VBAT or VDD.
2 Since the VDD voltage monitoring (+VDET1) during backup is intermittent operation (31.25 ms) , a delay occurs after VDD reaches
+VDET1 until the power supply switches.
*3 For internal initialization, the VDD voltage at the initial power-on must be increased to 1.6 V or more.
10. Interface timing when power ON / OFF
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10.2. VDD and CE Timing at Power On
When the power is turned to ON, use with CE=Low,VCL V in the diagramas illustrated in the following timing chart.
VDD
1.6 V
VCL
tCL
CE
Figure 15 VDD, CE sequence
Table 10 CE Timing
Item
Symbol
Condition
Specification
Unit
CE voltage when power is
turned to ON
VCL
CE impressed voltage
until VDD=1.6 V
0.3 Max.
V
CE = VCLV time when power
is turned to ON
tCL
Time to maintain CE = VCL
until VDD=1.6 V
40 Min.
ms
10.2. Restrictions on Access Operations During Power-on Initialization and Recovery from Backup
Because most of RTC registers are synchronized with the oscillation clock of the built-in crystal oscillator, the RTC does
not work normally without the integrated oscillator having stabilized. Please initialize the RTC at the time the power supply
voltage returns (VLF = 1) after the oscillation has stabilized (after oscillation start time t_STA).
If intending to access the RTC after the main supply voltage returns, please note following points:
VDD
VDD detect voltage +VDET
Internal oscillation
(illustration)
t_str
Oscillation start time
(internal oscillation wait time)
Access is enabled
Normal operation start
Minimum voltage for clock maintenance VCLK
During power-on initialization or power
supply voltage recovery after drop in clock
maintenance voltage
30[ms]
After 30 ms progress, Confirm a state by VLF-bit
At the time of VLF=1: After a t_str wait, initial setting is necessary.
At the time of VLF=0: Register access is possible.
VBAT
FOUT
Figure 16 Oscillation start time chart (Power initial supply)
10. Interface timing when power ON / OFF
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ETM62E-02 Seiko Epson Corporation 15
Recovery from Backup
VBAT
VDD
VDD detect voltage +VDET1
Minimum voltage for clock maintenance VCLK Min.
Recovery from Backup
After 40 ms progress, access is enabled.
After VLF confirmation, it is similar
to initial power ON.
FOUT
40 ms
Because interface disable before 40 ms,
reading data are indefinite.
Figure 17 Recovery from Backup
10.3. Reset by Software
Software sequence for generating Power-on-reset
1) Power ON
2) Wait more than 40 ms. *1
3) Dummy readout *2
4) Confirm VLF-bit = 1.
5) Write 00h Address: Bank3 - 2h INIEN = 0b
6) Write 80h Address: Bank3 - Fh TEST = 1 *3
7) Write 6Ch Address: Bank5 - 0h
8) Write 03h Address: Bank5 - 1h
9) Write 10h Address: Bank5 - 2h
10) Write 20h Address: Bank5 - 3h
11) Wait more than 2 ms. TEST-bit is reset automatically. *4
*1 *1 When 40 ms waiting time is so long time in your system, an another method.
Jump to step3 from step1.
At step4, when VLF is 1, write 0 to VLF. While VLF is 1, repeat reset to VLF and verify VLF is 0.
If VLF is cleared to 0, jump to step5. In this method, it have possibility this sequence is short than 40 ms.
After 40 ms, when VLF doesn't reset to 0, go to step5.
*2 *2 Dummy reading. Any address is acceptable.
*3 *3 Should be execute this command even if VLF is 0. Even if VLF is 1, it available after step5.
*4 *4 2ms wait is needed for RESET completion.
Note: Except using this RESET sequence, never write 1 to a TEST- bit.
11. Reference information
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11.1. Reference Data
(1)Example of frequency and temperature characteristics
-150
-100
-50
0
-50
0
50
100
Temperature [C]
Frequency fT
10-6
T= +25 C Typ.
= -0.035 10-6 Typ.
[Finding the frequency stability]
1.Frequency and temperature characteristics can be
approximated using the following equations.
fT=
(
T
X)2
fT: Frequency deviation in any temperature
[1/
C2]: Coefficient of secondary temperature
(0.0350.005)106/
C2
T[
C]: Ultimate temperature(+255
C)
X[
C]: Any temperature
2.To determine overall clock accuracy, add the
frequency precision and voltage characteristics.
f/f=
f/fo+
fT+
fV
f/f : Clock accuracy (stable frequency)
in any temperature and voltage.
f/fo : Frequency precision
fT: Frequency deviation in any temperature.
fV: Frequency deviation in any voltage.
3.How to find the date difference
Date Difference =
f/f
86400 (Sec)
For example:
f/f = 11.57410-6 is an error of
approximately 1 second/day.
Figure 18 Frequency vs Temperature characteristics
"Link"
12. Application notes
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1) Notes on handling
This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling.
(1) Static electricity
While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by
a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials.
In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used
with this module, which should also be grounded when such devices are being used.
(2) Noise
If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up."
In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1F as close as possible
to the power supply pins. Also, avoid placing any device that generates high level of electronic noise near this module.
(3) Voltage levels of input pins
When the voltage of out of the input voltage specifications range input into an input terminal constantly, a penetration electric
current occurs. Thus, current consumption increases very much. This causes Latch-up, and there is the case that, as a result, a
built-in IC is destroyed. Please use an input terminal according to input voltage specifications.
(4) Handling of unused pins
Disposal of unused input terminals. When an input terminal is open state, it causes increase of a consumption electric current
and the behavior that are instability. Please connect an unused input terminal to VIO or GND.
2) Notes on packaging
(1) Soldering heat resistance.
If the temperature within the package exceeds +260 C, the characteristics of the crystal oscillator will be degraded and it may
be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting
temperature and time before mounting this device. Also, check again if the mounting conditions are later changed.
(2) Mounting equipment
While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in
some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the
mounting conditions are later changed, the same check should be performed again.
(3) Ultrasonic cleaning
Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during
ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time,
state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic
cleaning.
(4) Mounting orientation
This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before
mounting.
(5) Leakage between pins
Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the
device is dry and clean before supplying power to it.
(6) Installation of charged battery.
When a charged backup battery is installed by soldering, battery connection terminal of this device should connect to
GND, beforehand.
13. Overview of Functions and Registers
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ETM62E-02 Seiko Epson Corporation 18
Note: The initialization of the register is necessary about the unused function.
13.1. Overview of Functions
s
32 years
the /INT pin goes to low level and 1 is set to the TF bit to report
.
and the
.
oltage Drop Detection Function
Frequency Stop Detection Function
This flag bit indicates the retained status of clock operations or internal data. Its value changes from 0 to 1 when data loss
might have occurred due to a low supply voltage.
RAM register is read/write accessible for any data.
Built-in 8bit × 64word (512bit) RAM
When not use Timestamp function, it can use for users memory.
13. Overview of Functions and Registers
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ETM62E-02 Seiko Epson Corporation 19
13.2. Register Table
The target register is selected and accessed with the first 4-bit mode setting code of communication.
Table 11 SPI-Bus 4bits Registers
Mode
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Read
9h
Ah
Bh
Ch
Dh
Eh
Fh
Write
1h
2h
3h
4h
5h
6h
7h
13.2.1. Register Table
Table 12 Register Table 1
Bank1
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
0h
SEC
z
40
20
10
8
4
2
1
1h
MIN
z
40
20
10
8
4
2
1
2h
HOUR
z
z
20
10
8
4
2
1
3h
WEEK
z
6
5
4
3
2
1
0
4h
DAY
z
z
20
10
8
4
2
1
5h
MONTH
z
z
z
10
8
4
2
1
6h
YEAR
80
40
20
10
8
4
2
1
7h
MIN Alarm
AE
40
20
10
8
4
2
1
8h
HOUR Alarm
AE
20
10
8
4
2
1
9h
WEEK Alarm
AE
6
5
4
3
2
1
0
DAY Alarm
20
10
8
4
2
1
Ah
Timer Counter 0
128
64
32
16
8
4
2
1
Bh
Timer Counter 1
32768
16384
8192
4096
2048
1024
512
256
Ch
Timer Counter 2
8388608
4194304
524288
131072
65536
Dh
Extension Register
FSEL1
FSEL0
USEL
TE
WADA
TSEL1
TSEL0
Eh
Flag Register
POR
z
UF
TF
AF
EVF
VLF
XST
Fh
Control Register
z
z
UIE
TIE
AIE
EIE
z
STOP
Bank2
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
0h
Time Stamp 1/1024S
-
-
-
-
-
-
1/512
1/1024
1h
Time Stamp 1/256S
1/2
1/4
1/8
1/16
1/32
1/64
1/128
1/256
2h
Time Stamp SEC
z
40
20
10
8
4
2
1
3h
Time Stamp MIN
z
40
20
10
8
4
2
1
4h
Time Stamp HOUR
z
z
20
10
8
4
2
1
5h
Time Stamp WEEK
z
6
5
4
3
2
1
0
6h
Time Stamp DAY
z
z
20
10
8
4
2
1
7h
Time Stamp MONTH
z
z
z
10
8
4
2
1
8h
Time Stamp YEAR
80
40
20
10
8
4
2
1
9h
Status Stamp
z
z
VDET
z
XST
z
Ah
No Function
z
z
z
z
z
z
z
z
Bh
Over Write Control
No Function
OVW
-
Ch
SEC Alarm
AE
40
20
10
8
4
2
1
Dh
Timer Control
z
z
z
z
TBKON
TBKE
TMPIN
TSTP
Eh
Time Stamp control 0
z
z
z
z
z
z
z
COMTG
Fh
Command Trigger
z
z
z
z
z
z
z
z
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4
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