Epson RA8900SA/CE Instructions for use

ETM44E-01
Preliminary
Application Manual
Real Time Clock Module
RA8900SA/CE

NOTICE
This material is subject to change without notice.
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development and/or manufacture of weapon of mass destruction or for other military purposes. You
are also requested that you would not make the products available to any third party who may use
the products for such prohibited purposes.
These products are intended for general use in electronic equipment. When using them in specific
applications that require extremely high reliability, such as the applications stated below, you must
obtain permission from Seiko Epson in advance.
/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and
related (automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life /
Submarine transmitters / Power stations and related / Fire work equipment and security
equipment / traffic control equipment / and others requiring equivalent reliability.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their
respective.

RA8900 SA / CE
Contents
1. Overview ................................................................................................................................................................................1
2. Block Diagram........................................................................................................................................................................1
3. Terminal description...............................................................................................................................................................2
3.1. Terminal connections .............................................................................................................................................2
3.2. Pin Functions..........................................................................................................................................................2
4. Absolute Maximum Ratings ...................................................................................................................................................3
5. Recommended Operating Conditions ....................................................................................................................................3
6. Frequency Characteristics .....................................................................................................................................................3
7. Electrical Characteristics........................................................................................................................................................4
7.1. DC Characteristics .................................................................................................................................................4
7.2. AC Characteristics..................................................................................................................................................5
8. Use Methods ..........................................................................................................................................................................6
8.1. Description of Registers .........................................................................................................................................6
8.1.1. Write / Read and Bank Select ................................................................................................................6
8.1.2. Register table (Basic time and calendar register)...................................................................................6
8.1.3. Register table (Extension register) .........................................................................................................7
8.2. Details of Registers ................................................................................................................................................8
8.2.1. Clock counter (SEC - HOUR ) ................................................................................................................8
8.2.2. Calendar counter ( WEEK - YEAR ) .......................................................................................................9
8.2.3. Alarm registers .....................................................................................................................................10
8.2.4. Fixed-cycle timer control registers........................................................................................................10
8.2.5. Extension register.................................................................................................................................10
8.2.6. Flag register..........................................................................................................................................11
8.2.7. Control register .....................................................................................................................................12
8.2.8. Temperature Data register ...................................................................................................................14
8.2.9. Backup power supply function register.................................................................................................14
8.3. Fixed-cycle Timer Interrupt Function....................................................................................................................15
8.3.1. Diagram of fixed-cycle timer interrupt function .....................................................................................15
8.3.2. Related registers for function of time update interrupts........................................................................16
8.3.3. Fixed-cycle timer interrupt interval (example).......................................................................................17
8.3.4. Fixed-cycle timer start timing................................................................................................................17
8.4. Time Update Interrupt Function............................................................................................................................18
8.4.1. Time update interrupt function diagram................................................................................................18
8.4.2. Related registers for time update interrupt functions.
...........................................................................19
8.5. Alarm Interrupt Function
.......................................................................................................................................20
8.4.1. Diagram of alarm interrupt function ......................................................................................................20
8.5.2. Related registers ..................................................................................................................................21
8.5.2. Examples of alarm settings ..................................................................................................................22
8.6. About the interrupt function for operation /INT=”L” interrupt output......................................................................23
8.7. Temperature compensation function.
...................................................................................................................23
8.7.1. Temperature compensation function
....................................................................................................23
8.7.2. Related registers for temperature compensation function
....................................................................23
8.8. Battery backup switchover function......................................................................................................................24
8.8.1. Description of Battery backup switchover function ...............................................................................24
8.8.2. Control the contents of the power switching.........................................................................................25
8.8.3. Function that can be used in the backup state .....................................................................................25
8.8.4. Notes on power switching function is used...........................................................................................26
8.8.5. Related registers of the backup power supply switching function ........................................................26
8.9. Reading/Writing Data via the I2C Bus Interface...................................................................................................27
8.9.1. Overview of I2C-BUS ...........................................................................................................................27
8.9.2. System configuration ............................................................................................................................27
8.9.3. Starting and stopping I2C bus communications....................................................................................28
8.9.4. Data transfers and acknowledge responses during I2C-BUS communications ...................................29
8.9.5. Slave address.......................................................................................................................................29
8.9.6. I2C bus protocol ....................................................................................................................................30
8.10. Backup and Recovery ........................................................................................................................................31
8.11. About access at the time of backup return and Initial power supply ..................................................................32
8.12. Flow chart...........................................................................................................................................................33
8.13. Connection with Typical Microcontroller.............................................................................................................36
8.14. When used as a clock source (32 kHz-TCXO)...................................................................................................36
9. External Dimensions/Marking Layout.................................................................................................................................37
10. Application notes................................................................................................................................................................39

RA8900 SA / CE
Page - 1 ETM44E-01
For automotive I2C-Bus Interface Real-time Clock Module
RA8900 SA / CE
Features built-in 32.768 kHz DTCXO, High Stability.
Supports I2C-Bus's high speed mode (400 kHz)
Alarm interrupt function for day, date, hour, and minute settings
Fixed-cycle timer interrupt function
Time update interrupt function (Seconds, minutes)
32.768 kHz output with OE function (FOE and FOUT pins)
Auto correction of leap years (from 2000 to 2099)
Wide interface voltage range: 2.5 V to 5.5 V
Wide time-keeping voltage range:1.6 V to 5.5 V
Low current consumption: 0.70A / 3 V (Typ.)
Built-in Backup switchover circuit
The I2C-BUS is a trademark of NXP Semiconductors.
*This product is on development. This specification may be changed until it releases.
1. Overview
This module is an I2C bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO.
In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter
function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer
function,time update interrupt function,and 32.768 kHz output function. By the battery backup switchover
function and the interface power supply input pin, RA8900 can support various power supply circuitries.
The devices in this module are fabricated via a C-MOS process for low current consumption, which enables
long-term battery back-up.
2. Block Diagram
I NTERRUPT S
CONTROLLER
A
LARM REGI STE
R
/ IN
T
BUS
INTERF ACE
CIRCUI T
( 3 2. 768 k Hz )
CONTROL
REGISTER
and
SYSTE
M
CONTROL LE
R
DIVI DER CLOCK
POWER
CONTROLLE
R
and
SDA
VDD
SCL
C
ALEND
R
TI ME
R
REGI STE
R
DTCXO
VB A
T
CONTROLLE
R
FOUT
FOUT
FOE

RA8900 SA / CE
Page - 2 ETM44E-01
3. Terminal description
3.1. Terminal connections
RA8900SA
1. T1 (CE) 14. N.C.
2. SCL 13. SDA
3. FOU T 1 2. T2 ( VPP)
4. N.C . 11. GND
5. VBAT 10. / INT
6. VDD 9. N.C.
7. FOE
8. N.C.
SOP14
p
in
RA8900CE
1. F OE 1 0. / I N T
2. VDD 9. GND
3. VBAT 8. T2 (VPP)
4. FOUT 7. SD A
5. SCL 6. T1 (CE)
3.2. Pin Functions
Signal
name I/O Function
SDA I/O
This pin's signal is used for input and output of address, data, and ACK bits, synchronized
with the serial clock used for I2C communications.
Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable
pull-up resistance relative to the signal line capacity.
SCL Input This is the serial clock input pin for I2C Bus communications.
FOUT Output
This is the C-MOS output pin with output control provided via the FOE pin.
When FOE ="H"(high level), this pin outputs a 32.768 kHz signal.
When output is stopped, the FOUT pin = "Hi-Z"( high impedance ).
FOE Input
This is an input pin used to control the output mode of the FOUT pin.
When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the
FOUT pin is stopped.
/ INT Output This pins is used to output alarm signals, timer signals, time update signals, and other
signals. This pin is an open drain pin.
VBAT 
This is a power supply pin for backup battery.
This is a pin to connect a large-capacity capacitor, a secondary battery.
When the battery switchover function does not need, VBAT must be connected to VDD.
VDD This pin is connected to a positive power supply.
GND This pin is connected to a ground.
TEST Input Use by the manufacture for testing. ( Do not connect externally.)
T1 (CE) Input Use by the manufacture for testing. ( Do not connect externally.)
T2 (VPP) Use by the manufacture for testing. ( Do not connect externally.)
N.C. This pin is not connected to the internal IC.
Leave N.C. pins open or connect them to GND or VDD.
Note: Be sure to connect a bypass capacitor rated at least 0.1 μF between VDD and GND.

RA8900 SA / CE
Page - 3 ETM44E-01
4. Absolute Maximum Ratings GND=0V
Item Symbol Condition Rating Unit
Supply voltage (1) VDD Between VDD and GND 0.3 to +6.5 V
Supply voltage (2) VBAT Between VBAT and GND 0.3 to +6.5 V
Input voltage (2) VIN FOE,SCL, SDA pins GND0.3 to +6.5 V
Output voltage (1) VOUT1 FOUT pin GND0.3 to VDD+0.3 V
Output voltage (2) VOUT2 SDA and /INT pins GND0.3 to +6.5 V
Storage temperature TSTG When stored separately,
without packaging 55 to +125 C
5. Recommended Operating Conditions GND=0 V
Item Symbol Condition Min. Typ. Max. Unit
Operating supply voltage
(1) VACC Between VDD and GND (VDD = VBAT )1.6 3.0 5.5 V
Operating supply voltage
(2) VACCSW Between VDD and GND 2.5 3.0 5.5 V
Backup power supply
voltage VBAT Between VBAT and GND 1.6 3.0 5.5 V
Temp. compensation
voltage VTEM Temperature compensation voltage 2.0 3.0 5.5 V
Clock supply voltage VCLK 1.6 3.0 5.5 V
Operating temperature TOPR No condensation 40 +25 +85 C
*
6. Frequency Characteristics GND=0V
Item Symbol Condition Rating Unit
Frequency stability f / f
UA
Ta= 0 to +50 C, VDD=3.0 V
Ta=40 to +85 C, VDD=3.0 V
1.9 (1)
3.4 (2)
10６
UB
Ta= 0 to +50 C, VDD=3.0 V
Ta=40 to +85 C, VDD=3.0 V
3.8 (3)
5.0 (4)
U C
Ta= 0 to +50 C, VDD=3.0 V
Ta=30 to +70 C, VDD=3.0 V
3.8 (3)
5.0 (4)
Frequency/voltage
characteristics f / V
Ta= +25 C, VDD=2.0 V to 5.5 V
1.0 Max. 10６/ V
Oscillation start time tSTA Ta= +25 C, VDD=1.6 V 5.5 V
Ta=40 to +85 C, VDD=1.6 V to 5.5 V
1.0Max.
3.0Max.
s
Aging fa
Ta= +25 C, VDD=3.0 V, first year 3 Max. 10６/
year
Temperature Sensor
Accuracy Temp VDD=3.0 V 5.0 Max. (TBD) C
*
1
)
Equivalent to 5 seconds of month deviation. *
2
)
Equivalent to 9 seconds of month deviation.
*3 ) Equivalent to 10 seconds of month deviation. *4 ) Equivalent to 13 seconds of month deviation.

RA8900 SA / CE
Page - 4 ETM44E-01
7. Electrical Characteristics
7.1. DC Characteristics *Unless otherwise specified, GND=0V,VDD=2.5Vto5.5V,Ta=40Cto+85C
Item Symbol Condition Min. Typ. Max. Unit
Current
consumption (1) IDD1 f
SCL = 0 Hz, / INT = VDD
FOE = GND, VDD = VBAT
FOUT : output OFF (High Z)
Compensation interval 2.0 s
VDD=5 V
0.72 1.50
A
Current
consumption (2) IDD2 VDD=3 V
0.70 1.40
Current
consumption (3) IDD3 f
SCL = 0 Hz, / INT = VDD
FOE = VDD, VDD = VBAT
FOUT :32.768 kHz, CL =0pF
Compensation interval 2.0 s
VDD=5 V
1.60 2.50
A
Current
consumption (4) IDD4 VDD=3 V
1.15 2.40
Current
consumption (5) IDD5 f
SCL = 0 Hz, / INT = VDD
FOE = VDD, VDD = VBAT
FOUT :32.768 kHz, CL =30pF
Compensation interval 2.0 s
VDD=5 V
6.70 8.00
A
Current
consumption (6) IDD6 VDD=3 V
4.30 5.50
Current
consumption (7) IDD7 f
SCL = 0 Hz, / INT = VDD
FOE = GND, VDD = VBAT
FOUT : output OFF (High Z)
Compensation OFF
VDD=5 V
0.70 1.45
A
Current
consumption (8) IDD8 VDD=3 V
0.68 1.35
Current
consumption (9) IDD9 f
SCL = 0 Hz, / INT = VDD
FOE = GND, VDD = VBAT
FOUT : output OFF (High Z)
Compensation ON ( peak )
VDD=5 V
55 100
A
Current
consumption (10) IDD10 VDD=3 V
50 95
High-level input
voltage VIH CE, DI, CLK, FOE pins 0.8 VDD 5.5 V
Low-level input
voltage VIL CE, DI, CLK, FOE pins GND 0.3 0.2 VDD V
High-level output
voltage
VOH1
FOUT pin
VDD=5 V, IOH=1 mA 4.5 5.0
VVOH2 VDD=3 V, IOH=1 mA 2.2 3.0
VOH3 VDD=3 V, IOH=100 A 2.9 3.0
Low-level output
voltage
VOL1
FOUT pin
VDD=5 V, IOL=1 mA GND GND+0.5
V
VOL2 VDD=3 V, IOL=1 mA GND GND+0.8
VOL3 VDD=3 V, IOL=100 A GND GND+0.1
VOL4 / INT pin VDD=5 V, IOL=1 mA GND GND+0.25 V
VOL5 VDD=3 V, IOL=1 mA GND GND+0.4
VOL6 SDA pin VDD 2 V, IOL=3 mA GND GND+0.4 V
Input leakage
current ILK FOE, SCL, SDA pins , VIN = VDD or GND 0.5 0.5
A
Output leakage
current IOZ / INT, SDA, FOUT pins, VOUT = VDD or GND 0.5 0.5
A
Temperature compensation and consumption current
1.4 ms
IDD9,10
Compensation interval ( 2.0 s )
IDD7,8 IDD1,2
Compensation OFF
A
verage
Compensation ON

RA8900 SA / CE
Page - 5 ETM44E-01
7.2. AC Characteristics * Unless otherwise specified,
GND=0V,VDD=VBAT=1.6Vto5.5V,Ta=40Cto+85C
Item Symbol Condition Min. Typ. Max. Unit
SCL clock frequency fSCL 400 kHz
Start condition setup time tSU;STA 0.6
s
Start condition hold time tHD;STA 0.6
s
Data setup time tSU;DAT 100 ns
Data hold time tHD;DAT 0 900 ns
Stop condition setup time tSU;STO 0.6
s
Bus idle time between
start condition and stop condition tBUF 1.3
s
Time when SCL = "L"tLOW 1.3
s
Time when SCL = "H" tHIGH 0.6
s
Rise time for SCL and SDA tr 0.3
s
Fall time for SCL and SDA tf 0.3
s
Allowable spike time on bus tSP 50 ns
FOUT duty tW/t 50% of VDD level 40 50 60 %
Timing chart
tHD ; DAT tSU ; DAT tHD ; STA
tLOW tHIGH 1 / fSCL
tr tf
t
SU ; STA
SD
A
SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACK
(A)
Protocol
tBUF
tSU ; STO
STOP
CONDITION
(P)
START
CONDITION
(S)
(P)
(A)
tHD ; STA
t
SU ; STA
(S)
BIT 0
LSB
(R/W)
(S)
tSP
Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop
condition after access should be completed within 0.95 seconds.
If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus
timeout function.

RA8900 SA / CE
Page - 6 ETM44E-01
8. Use Methods
8.1. Description of Registers
8.1.1. Write / Read and Bank Select
Address 00h to 0Fh : Basic time and calendar register … Compatible with RX-8803.
Address 10h to 1Fh : Extension register.
8.1.2. Register table (Basic time and calendar register)
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read Write
00 SEC 40 20 10 8 4 2 1 P P
01 MIN 40 20 10 8 4 2 1 P P
02 HOUR 20 10 8 4 2 1 P P
03 WEEK 6 5 4 3 2 1 0 P P
04 DAY 20 10 8 4 2 1 P P
05 MONTH 10 8 4 2 1 P P
06 YEAR 80 40 20 10 8 4 2 1 P P
07 RAM P P
08 MIN Alarm AE 40 20 10 8 4 2 1 P P
09 HOUR Alarm AE 20 10 8 4 2 1 P P
0A
WEEK Alarm
AE
6 5 4 3 2 1 0 P P
DAY Alarm 20 10 8 4 2 1
0B Timer Counter 0 128 64 32 16 8 4 2 1 P P
0C Timer Counter 1 2048 1024 512 256 P P
0D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 P P
0E Flag Register UF TF AF VLF VDET P P
0F Control Register CSEL1 CSEL0 UIE TIE AIE RESET P P
P:Possible,I:Impossible
Note When after the initial power-up (from 0V) or when the result of read out the VLF bit is "1" , initialize all registers,
before using the module.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
time data is incorrect.
1) During the initial power-up, the TEST bit is reset to "0"and the VLF bit is set to "1".
At this point, all other register values are undefined, so be sure to perform a reset before using the module.
2) Only a "0" can be written to the UF, TF, AF, VLF, or VDET bit.
3) Any bit marked with "" should be used with a value of "0" after initialization.
4) Any bit marked with ""is a RAM bit that can be used to read or write any data.
5) The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.

RA8900 SA / CE
Page - 7 ETM44E-01
8.1.3. Register table (Extension register)
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read Write
10 SEC 40 20 10 8 4 2 1 P I
11 MIN 40 20 10 8 4 2 1 P P
12 HOUR 20 10 8 4 2 1 P P
13 WEEK 6 5 4 3 2 1 0 P P
14 DAY 20 10 8 4 2 1 P P
15 MONTH 10 8 4 2 1 P P
16 YEAR 80 40 20 10 8 4 2 1 P P
17 TEMP 128 64 32 16 8 4 2 1 P P
18 Backup Function VDET
OFF
SWOFF BKSMP1 BKSMP0 P P
19 Not use P P
1A
1B
Not use 
128

P P
Timer Counter 0 64 32 16 8 4 2 1
1C Timer Counter 1 2048 1024 512 256 P P
1D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 P P
1E Flag Register UF TF AF VLF VDET P P
1F Control Register CSEL1 CSEL0 UIE TIE AIE RESET P P
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P P

RA8900 SA / CE
Page - 8 ETM44E-01
8.2. Details of Registers
8.2.1. Clock counter (SEC - HOUR )
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00, 10 SEC 40 20 10 8 4 2 1
01, 11 MIN 40 20 10 8 4 2 1
02, 12 HOUR   20 10 8 4 2 1
)"o" indicates write-protected bits. A zero is always read from these bits.
The clock counter counts seconds, minutes, and hours.
The data format is BCD format. For example, when the "seconds" register value is "0101 1001" it indicates 59
seconds.
Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.
1) Second counter
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00, 10 SEC 40 20 10 8 4 2 1
This second counter counts from "00" to "01," "02," and up to 59 seconds, after which it starts again from
00 seconds.
2) Minute counter
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01, 11 MIN 40 20 10 8 4 2 1
This minute counter counts from "00" to "01," "02," and up to 59 minutes, after which it starts again from
00 minutes.
3) Hour counter
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
02, 12 HOUR   20 10 8 4 2 1
This hour counter counts from "00" hours to "01," "02," and up to 23 hours, after which it starts again from
00 hours.

RA8900 SA / CE
Page - 9 ETM44E-01
8.2.2. Calendar counter ( WEEK - YEAR )
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
03, 13 WEEK 6 5 4 3 2 1 0
)"o" indicates write-protected bits. A zero is always read from these bits.
1) Day of the WEEK counter
 The day (of the week) is indicated by 7 bits, bit 0 to bit 6.
The day data values are counted as: Day 01hDay 02hDay 04hDay 08hDay 10hDay
20hDay 40hDay 01hDay 02h, etc.
The correspondence between days and count values is shown below.
WEEK bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Day Data [h]
Write/Read
0 0 0 0 0 0 0 1 Sunday 01 h
0 0 0 0 0 0 1 0 Monday 02 h
0 0 0 0 0 1 0 0 Tuesday 04 h
0 0 0 0 1 0 0 0 Wednesday 08 h
0 0 0 1 0 0 0 0 Thursday 10 h
0 0 1 0 0 0 0 0 Friday 20 h
0 1 0 0 0 0 0 0 Saturday 40 h
Write prohibit
Do not set "1" to more than one day at the same time.
Also, note with caution that any setting other than the
seven shown above should not be made as it may
interfere with normal operation.

Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
04, 14 DAY   20 10 8 4 2 1
05, 15 MONTH    10 8 4 2 1
06, 16 YEAR 80 40 20 10 8 4 2 1
)"o" indicates write-protected bits. A zero is always read from these bits.
The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099.
The data format is BCD format. For example, a date register value of "0011 0001" indicates the 31st.
Note with caution that writing non-existent date data may interfere with normal operation of the calendar counter.
2) Date counter
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
04, 14 DAY   20 10 8 4 2 1
 The updating of dates by the date counter varies according to the month setting.
 A leap year is set whenever the year value is a multiple of four (such as 04, 08, 12, 88, 92, or 96). In
February of a leap year, the counter counts dates from "01," "02," "03," to "28," "29," "01," etc.
DAY Month Date update pattern
Write/Read
1, 3, 5, 7, 8, 10, or 12 01, 02, 03 30, 31, 01 
4, 6, 9, or 11 01, 02, 03 30, 01, 02 
February in normal year 01, 02, 03 28, 01, 02 
February in leap year 01, 02, 03 28, 29, 01 
3) Month counter
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
05, 15 MONTH    10 8 4 2 1
The month counter counts from 01 (January), 02 (February), and up to 12 (December), then starts again at
01 (January).
4) Year counter
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
06, 16 YEAR Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1
The year counter counts from 00, 01, 02 and up to 99, then starts again at 00.
Any year that is a multiple of four (04, 08, 12, 88, 92, 96, etc.) is handled as a leap year.

RA8900 SA / CE
Page - 10 ETM44E-01
8.2.3. Alarm registers
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
08, 18 MIN Alarm AE 40 20 10 8 4 2 1
09, 19 HOUR Alarm AE 20 10 8 4 2 1
0A, 1A WEEK Alarm AE 6 5 4 3 2 1 0
DAY Alarm 20 10 8 4 2 1
The alarm interrupt function is used, along with the AEI, AF, and WADA bits, to set alarms for specified date, day,
hour, and minute values.
When the settings in the above alarm registers and the WADA bit match the current time, the /INT pin goes to low
level and "1" is set to the AF bit to report that and alarm interrupt event has occurred.
8.2.4. Fixed-cycle timer control registers
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0B, 1B Timer Counter 0 128 64 32 16 8 4 2 1
0C, 1C Timer Counter 1 2048 1024 512 256
These registers are used to set the preset countdown value for the fixed-cycle timer interrupt function.
The TE, TF, TIE, and TSEL0/1 bits are also used to set the fixed-cycle timer interrupt function.
When the value in the above fixed-cycle timer control register changes from 001h to 000h, the /INT pin goes to low
level and "1" is set to the TF bit to report that a fixed-cycle timer interrupt event has occurred.
8.2.5. Extension register
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0D, 1D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0
(Default) (0) () () () (0) (0) () ()
1)The default value is the value that is read (or is set internally) after powering up from 0 V.
2)"o" indicates write-protected bits. A zero is always read from these bits.
3)"" indicates a default value is undefined.
This register is used to specify the target for the alarm function or time update interrupt function and to select or set
operations such as fixed-cycle timer operations.
1) TEST bit
This is the manufacturer's test bit. Its value should always be "0".
Be careful to avoid writing a "1" to this bit when writing to other bits.
TEST Data Description
Write/Read
0 Normal operation mode Default
1 Setting prohibited (manufacturer's test bit)
2) WADA ( Week Alarm/Day Alarm ) bit
This bit is used to specify either WEEK or DAY as the target of the alarm interrupt function.
Writing a "1" to this bit specifies DAY as the comparison obLCct for the alarm interrupt function.
Writing a "0" to this bit specifies WEEK as the comparison obLCct for the alarm interrupt function.
3) USEL ( Update Interrupt Select ) bit
This bit is used to specify either "second update" or "minute update" as the update generation timing of the time
update interrupt function.
USEL Data update interrupts
Auto reset time
tRTN
Write/Read 0 second update Default 500 ms
1 minute update 7.813 ms
4) TE ( Timer Enable ) bit
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
Writing a "1" to this bit specifies starting of the fixed-cycle timer interrupt function (a countdown starts from a
preset value).
Writing a "0" to this bit specifies stopping of the fixed-cycle timer interrupt function.

RA8900 SA / CE
Page - 11 ETM44E-01
5) FSEL0,1 ( FOUT frequency Select 0, 1 ) bits
The combination of these two bits is used to set the FOUT frequency.
FSEL0,1 FSEL1
(bit 3)
FSEL0
(bit 2) FOUT frequency
Write/Read
0 0
32768HzOutput Default
0 1
1024HzOutput
1 0
1HzOutput
1 1
32768HzOutput
6) TSEL0,1 ( Timer Select 0, 1 ) bits
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL0,1 TSEL1
(bit 1)
TSEL0
(bit 0) Source clock
Write/Read
0 0 4096 Hz / Once per 244.14 s
0 1 64 Hz / Once per 15.625 ms
1 0 "Second" update / Once per second
1 1 "Minute" update / Once per minute
8.2.6. Flag register
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0E, 1E Flag register   UF TF AF VLF VDET
(Default) (0) (0) () () () (0) (1) (1)
1)The default value is the value that is read (or is set internally) after powering up from 0 V.
2)"o" indicates write-protected bits. A zero is always read from these bits.
3)"" indicates a default value is undefined.
This register is used to detect the occurrence of various interrupt events and reliability problems in internal data.
1) UF ( Update Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a time update interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
For details, see "8.4. Time Update Interrupt Function".
2) TF ( Timer Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
For details, see "8.3. Fixed-cycle Timer Interrupt Function".
3) AF ( Alarm Flag ) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred.
Once this flag bit's value is "1", its value is retained until a "0" is written to it.
For details, see "8.5. Alarm Interrupt Function".
4) VLF ( Voltage Low Flag ) bit
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"
when data loss occurs, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is retained
until a "0" is written to it.
When after powering up from 0 V this bit's value is "1" .

RA8900 SA / CE
Page - 12 ETM44E-01
VLF Data Description
Write
0 The VLF bit is cleared to zero to prepare for the next status detection.
1 This bit is invalid after a "1" has been written to it.
Read
0 Data loss is not detected.
1 Data loss is detected. All registers must be initialized.
( This setting is retained until a "zero" is written to this bit. )
5) VDET ( Voltage Detection Flag ) bit
This flag bit indicates the status of temperature compensation. Its value changes from "0" to "1" when stop the
temperature compensation, such as due to a supply voltage drop. Once this flag bit's value is "1", its value is
retained until a "0" is written to it.
When after powering up from 0 V this bit's value is "1".
VDET Data Description
Write
0 The VDET bit is cleared to zero to prepare for the next low voltage detection.
1 The write access of "1" to this bit is invalid.
Read
0 Temperature compensation is normal.
1 Temperature compensation is stop detected.
8.2.7. Control register
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0F, 1F Control Register CSEL1 CSEL0 UIE TIE AIE RESET
(Default) (0) (1) () () () (0) (0) ()
1)The default value is the value that is read (or is set internally) after powering up from 0 V.
2)"o" indicates write-protected bits. A zero is always read from these bits.
3)"" indicates no default value has been defined.
This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and
calendar operations.
1) CSEL0,1 ( Compensation interval Select 0, 1 ) bits
The combination of these two bits is used to set the temperature compensation interval.
CSEL0,1 CSEL1
(bit 7)
CSEL0
(bit 6) Compensation interval
Write/Read
0 0 0.5 s
0 1 2.0 s
Default
1 0 10 s
1 1 30 s
2) UIE ( Update Interrupt Enable ) bit
When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0"is written to this bit, no interrupt signal is generated when an interrupt event occurs.

RA8900 SA / CE
Page - 13 ETM44E-01
UIE Data Function
Write/Read
0 When a time update interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status changes from low to Hi-Z).
1
When a time update interrupt event occurs, an interrupt signal is generated
(/INT status changes from Hi-Z to low).
 When a time update interrupt event occurs, low-level output from the /INTpin occurs only when
the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT
status changes from low to Hi-Z) 7.8ms after the interrupt occurs.
2) TIE ( Timer Interrupt Enable ) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0"is written to this bit, no interrupt signal is generated when an interrupt event occurs.
TIE Data Function
Write/Read
0 When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status changes from low to Hi-Z).
1
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
*When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).
3) AIE ( Alarm Interrupt Enable ) bit
When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value
specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status
remains Hi-Z).
When a "1"is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an
interrupt event is generated.
When a "0"is written to this bit, no interrupt signal is generated when an interrupt event occurs.
AIE Data Function
Write/Read
0 When an alarm interrupt event occurs, an interrupt signal is not generated
or is canceled (/INT status changes from low to Hi-Z).
1
When an alarm interrupt event occurs, an interrupt signal is generated (/INT
status changes from Hi-Z to low).
 When an alarm interrupt event has been generated low-level output from the /INT pin occurs
only when the value of the control register's AIE bit is "1". This setting is retained until the AF
bit value is cleared to zero. (No automatic cancellation)
For details, see "8.5. Alarm Interrupt Function".
[Caution]
(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.
When an interrupt has occurred (when the /INT pin is at low level), the UF, TF,read AF flags to determine which flag has a value of "1"
(this indicates which type of interrupt event has occurred).
(2) To keep the /INT pin from changing to low level, write "0" to the UIE,TIE,and AIE bits. To check whether an event has occurred without
outputting any interrupts via the /INT pin, use software to monitor the value of the UF,TF,and AF interrupt flags.
4) RESET bit
When this bit is set to "1", values (less than seconds) of the counter in the Clock & Calendar circuitry is reset,
and the clock also stops.
After "1" is written to this bit, this can be released by setting CE to "L".

RA8900 SA / CE
Page - 14 ETM44E-01
8.2.8. Temperature Data register
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
17 TEMP 128 64 32 16 8 4 2 1
1) Temperature Data register
This register can begin to read digital temperature data.
The temperature data are updated in an operation timing of the temperature compensation circuit.
You can make a conversion to a centigrade by temperature data by calculating in the following
expression .
Temperature[℃] = ( TEMP[ 7:0 ] * 2 – 187.19) / 3.218
8.2.9. Backup power supply function register
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
18 Backup Function VDET
OFF SWOFF BKSMP1 BKSMP0
This register is a setting register the voltage detection of VDD and built-in MOS switch of anti-countercurrent
control .
1) VDETOFF bit (Voltage Detector OFF)
This bit controls the voltage detection circuit of the main power supply VDD.
For details, see "8.＊. *****Function".
2) SWOFF bit (Switch OFF)
This bit controls the internal P-MOS switch for preventing back flow.
For details, see "8.＊. *****Function".
3) BKSMP1, BKSMP0 bit (Backup mode Sampling time)
This bit controls the operation time when to be intermittently driven the VDD voltage detection.
For details, see "8.＊. *****Function".

RA8900 SA / CE
Page - 15 ETM44E-01
8.3. Fixed-cycle Timer Interrupt Function
The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set
between 244.14sand 4095 minutes.
When an interrupt event is generated, the /INT pin goes to low level and "1" is set to the TF bit to report that an
event has occurred. (However, when a fixed-cycle timer interrupt event has been generated low-level output from
the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low-level to Hi-Z).
Example of
/INT operation
TIE ="1"
TE="0""1"
7.8ms
(Max.)
period TIE

=


"

1

"

"0"
8.3.1. Diagram of fixed-cycle timer interrupt function
TIE bit
/INT output
TF bit
Event occurs
TE bit
tRTN
tRTNtRTN
p
eriod
p
eriod
p
eriod
tRTN
p
eriod

"

1

"


"

0

"


"

1

"


"

0

"


Hi

-

z

"

L

"


"

1

"


"

0

"

Even when the TF
bit is cleared to zero,
the /INT status does
not change.
Even when the TE bit is
cleared to zero, /INT
remains low during the
tRTN time.
Operation of fixed-cycle timer
When the TE bit value changes from "0"to "1"the fixed-cycle timer function starts.
The counter always starts counting down from the preset value when the TE value changes from "0" to "1".
RTC internal operation
Write operation
Fixed-cycle timer starts Fixed-cycle timer stops
(1)
(1) (2)
001h000h
(3) (4)
(5)
"1"
(6)
(7)
(7)
(7)
(8)
(9)
(1) When a "1" is written to the TE bit, the fixed-cycle timer countdown starts from the preset value.
(2) A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When the
count value changes from 001h to 000h, an interrupt event occurs.
After the interrupt event that occurs when the count value changes from 001hto 000h, the counter
automatically reloads the preset value and again starts to count down. (Repeated operation)
(3) When a fixed-cycle timer interrupt event occurs, "1" is written to the TF bit.
(4) When the TF bit = "1" its value is retained until it is cleared to zero.
(5) If the TIE bit = "1" when a fixed-cycle timer interrupt occurs, /INT pin output goes low.
If the TIE bit = "0" when a fixed-cycle timer interrupt occurs, /INT pin output remains Hi-Z.
(6) Output from the /INT pin remains low during the tRTN period following each event, after which it is automatically
cleared to Hi-Z status.
/INT is again set low when the next interrupt event occurs.
(7)When a "0" is written to the TE bit, the fixed-cycle timer function is stopped and the /INT pin is set to Hi-Z status.
When /INT=low, the fixed-cycle timer function is stopped. The tRTN period is the maximum amount of time
before the /INT pin status changes from low to Hi-Z.
(8)As long as /INT=low, the /INT pin status does not change when the TF bit value changes from "1"to "0".
(9)When /INT=low, the /INT pin status changes from low to Hi-Z as soon as the TIE bit value changes from "1" to
"0".

RA8900 SA / CE
Page - 16 ETM44E-01
8.3.2. Related registers for function of time update interrupts.
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0B, 1B Timer Counter 0 128 64 32 16 8 4 2 1
0C, 1C Timer Counter 1 2048 1024 512 256
0D, 1D Extension Register TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0
0E, 1E Flag Register UF TF AF EVF VLF VDET
0F, 1F Control Register CSEL1 CSEL0 UIE TIE AIE EIE RESET
1)"o" indicates write-protected bits. A zero is always read from these bits.
2)Bits marked with "" are RAM bits that can contain any value and are read/write-accessible.
Before entering settings for operations, we recommend writing a "0" to the TE and TIE bits to prevent hardware
interrupts from occurring inadvertently while entering settings.
When the STOP bit or RESET bit value is "1"the time update interrupt function operates only partially.
(Operation continues if the source clock setting is 4096 Hz. Otherwise, operation is stopped.)
When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register (Reg – B to C)
can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE
bits.
1) TSEL0,1 bits (Timer Select 0, 1)
The combination of these two bits is used to set the countdown period (source clock) for the fixed-cycle timer
interrupt function (four settings can be made).
TSEL0,1 TSEL1
(bit 1)
TSEL0
(bit 0) Source clock Auto reset time tRTN
Effects of
RESET bits
Write/Read
0 0 4096 Hz /Once per 244.14 s122s 
0 1 64 Hz / Once per 15.625 ms 7.8125ms Does not operate
when the RESET
bit value is "1".
1 0 "Second" update /Once per second 7.8125ms
1 1 "Minute" update /Once per minute 7.8125ms
1) The /INT pin's auto reset time (tRTN) varies as shown above according to the source clock setting.
2) When the source clock has been set to "second update" or "minute update", the timing of both
countdown and interrupts is coordinated with the clock update timing.
2) Fixed-cycle Timer Control register (Reg - BtoC)
This register is used to set the default (preset) value for the counter. Any count value from 1(001h)to
4095(FFFh)can be set. The counter counts down based on the source clock's period, and when the count value
changes from 001h to 000h, the TF bit value becomes "1".
The countdown that starts when the TE bit value changes from "0"to "1" always begins from the preset value.
Be sure to write "0" to the TE bit before writing the preset value. If a value is written while TE ="1" the first
subsequent event will not be generated correctly.
Address C
Timer Counter 1
Address B
Timer Counter 0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
2048 1024 512 256 128 64 32 16 8 4 2 1
3) TE (Timer Enable) bit
This bit controls the start/stop setting for the fixed-cycle timer interrupt function.
TE Data Description
Write/Read
0 Stops fixed-cycle timer interrupt function.
1 Starts fixed-cycle timer interrupt function.
The countdown that starts when the TE bit value changes from "0"to "1" always begins from the
preset value.
4) TF (Timer Flag) bit
If set to "0" beforehand, this flag bit's value changes from "0" to 1" when a fixed-cycle timer interrupt event has
occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it.
TF Data Description
Write
0 The TF bit is cleared to zero to prepare for the next status detection
Clearing this bit to zero does not enable the /INT low output status to be cleared (to Hi-Z).
1 This bit is invalid after a "1" has been written to it.
Read
0 Fixed-cycle timer interrupt events are not detected.
1 Fixed-cycle timer interrupt events are detected.
(Result is retained until this bit is cleared to zero.)

RA8900 SA / CE
Page - 17 ETM44E-01
5) TIE (Timer Interrupt Enable) bit
When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value
specifies whether an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT
status remains Hi-Z).
TIE Data Description
Write/Read
0
1) When a fixed-cycle timer interrupt event occurs, an interrupt signal is not
generated or is canceled (/INT status remains Hi-Z).
2) When a fixed-cycle timer interrupt event occurs, the interrupt signal is
canceled (/INT status changes from low to Hi-Z).
 Even when the TIE bit value is "0" another interrupt event may change the /INT status to low (or
may hold /INT ="L").
1
When a fixed-cycle timer interrupt event occurs, an interrupt signal is
generated (/INT status changes from Hi-Z to low).
 When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin
occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt
occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z).
8.3.3. Fixed-cycle timer interrupt interval (example)
Timer
Counter
setting
Source clock
4096 Hz
TSEL1,0 = 0,0
64 Hz
TSEL1,0 = 0,1
"Second"
update
TSEL1,0 = 1,0
"Minute"
update
TSEL1,0 = 1,1
0   
1 244.14 s 15.625 ms 1 s 1 min
2 488.28 s 31.25 ms 2 s 2 min















41 10.010 ms 640.63 ms 41 s 41 min
205 50.049 ms 3.203 s 205 s 205 min
410 100.10 ms 6.406 s 410 s 410 min
2048 500.00 ms 32.000 s 2048 s 2048 min















4095 0.9998 s 63.984 s 4095 s 4095 min
Time error in fixed-cycle timer
A time error in the fixed-cycle timer will produce a positive or negative time period error in the selected
source clock. The fixed-cycle timer's time is within the following range relative to the time setting.
(Fixed-cycle timer's time setting () source clock period) to (timer's time setting)
) The timer's time setting = source clock period timer counter's division value.
The time actually set to the timer is adjusted by adding the time described above to the
communication time for the serial data transfer clock used for the setting.
8.3.4. Fixed-cycle timer start timing
Counting down of the fixed-cycle timer value starts at the rising edge of the SCL signal that occurs when the TE value
is changed from "0" to "1"(after bit 0 is transferred).
TSEL0
TE FSEL1 TSEL1
Operation of timer
/INT pin
SDA pin
SCL pin
Internal timer
A
ddress D
A
CKFSEL0