Epson SR3225SAA Instructions for use

ETM54E-07
RF Transmitter Module
SR3225SAA
Application Manual

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SR3225SAA
ETM54E-07
Table of Contents
1. Overview...................................................................................................................... 1
2. Part Number ................................................................................................................ 2
3. Block Diagram.............................................................................................................. 3
4. Pin Assignments............................................................................................................ 4
4.1. Pin Assignments ............................................................................................................................4
4.2. Pin Descriptions ............................................................................................................................4
5. Electrical Characteristics.............................................................................................. 5
5.1. Absolute Maximum Rating............................................................................................................5
5.2. DC Characteristics........................................................................................................................6
5.3. AC Characteristics........................................................................................................................8
6. Function Description................................................................................................... 12
6.1. Outline........................................................................................................................................12
6.2. SPI Interface...............................................................................................................................12
SPI interface mode change......................................................................................................136.2.1.
SFR access command.............................................................................................................146.2.2.
SPI checksum ........................................................................................................................166.2.3.
Transmit command.................................................................................................................176.2.4.
6.3. Operating Modes.........................................................................................................................21
State transition.......................................................................................................................216.3.1.
Control signal timing..............................................................................................................226.3.2.
6.4. Output Frequency Setting ...........................................................................................................23
Calculation for the frequency setting value...............................................................................236.4.1.
6.5. FSK Modulator...........................................................................................................................25
FSK deviation setting .............................................................................................................256.5.1.
Soft-FSK...............................................................................................................................266.5.2.
6.6. Output Power Setting..................................................................................................................26
ASK modulation ....................................................................................................................266.6.1.
Soft-ASK ..............................................................................................................................286.6.2.
Antenna tuning ......................................................................................................................286.6.3.
6.7. Fail-safe Function........................................................................................................................29
PLL Loss of Lock detection ....................................................................................................296.7.1.
VCO auto-calibration error detection.......................................................................................296.7.2.
Under voltage detection..........................................................................................................296.7.3.
6.8. Clock Output (CKOUT) Function...............................................................................................31
Frequency divider ..................................................................................................................316.8.1.
Frequency divider setting........................................................................................................326.8.2.
Output CMOS driver..............................................................................................................336.8.3.
6.9. Status Monitor ............................................................................................................................33
Transition counter ..................................................................................................................336.9.1.
Oscillation status monitor .......................................................................................................336.9.2.
7. SFR (Special Function Register).................................................................................. 34
7.1. SFR List......................................................................................................................................34
7.2. PLL Fractional Setting: Frequency Channel 1.............................................................................35
7.3. PLL Fractional Setting: Frequency Channel 2.............................................................................35
7.4. PLL Integer Setting: Frequency Channel 1 and 2........................................................................35

SR3225SAA
ETM54E-07
7.5. PLL Fractional Setting: Frequency Channel 3.............................................................................36
7.6. PLL Fractional Setting: Frequency Channel 4.............................................................................36
7.7. PLL Integer Setting: Frequency Channel 3 and 4........................................................................36
7.8. FSK Deviation Setting, Output Divider Setting, and CKOUT Slew Rate Control Setting ............37
7.9. FSK Deviation Setting.................................................................................................................37
7.10. ASK Modulation Control 0..........................................................................................................38
7.11. ASK Modulation Control 1..........................................................................................................38
7.12. ASK Modulation Control 2..........................................................................................................39
7.13. Soft-ASK Modulation Setting......................................................................................................39
7.14. Soft-FSK Modulation Setting ......................................................................................................40
7.15. CKOUT / Bitrate Signal Divider Setting 1...................................................................................40
7.16. CKOUT / Bitrate Signal Divider Setting 2...................................................................................41
7.17. Under Voltage Detection /Antenna Tuning Setting......................................................................42
7.18. Error Detection Status.................................................................................................................43
7.19. Transmitter Control ....................................................................................................................44
7.20. SPI Checksum.............................................................................................................................45
8. Dimensions................................................................................................................. 46
9. Marking ..................................................................................................................... 47
10. Soldering Pattern........................................................................................................ 48
11. Application Note......................................................................................................... 49
12. Application Manual Revision History.......................................................................... 51

SR3225SAA
Page - 1 ETM54E-07
1. Overview
RF transmitter module SR3225SAA is a wireless transmitter module for the UHF range. This module houses a
crystal resonator, capacitors for an oscillation circuit, a PLL, and a PowerAmp in a 3.2 mm x 2.5 mm ceramic
package. The crystal resonator is optimally matched with the IC at the factory. The SR3225SAA is ideal for small
wireless transmitters because wireless transmission can be achieved simply by combining it with an external
controller.
Output frequency range: 300 MHz to 465 MHz (0.25 kHz Step), 600 MHz to 930 MHz (0.49 kHz Step)
Δ-Σ fractional-N PLL
Programmable power amplifier (PA) output power: -15 dBm to 1dBm, -5 dBm to 11 dBm for each 64 steps
Modulation types: ASK/OOK/FSK with Soft-ASK and/or Soft FSK shaping
Multi-channel (up to 4 channels), channel hopping capability
3-wire/4-wire SPI interface for Special Function Register (SFR)
SFR (Special Function Register)
Fail-safe mechanism (PLL Loss of Lock: LOL, VCO auto-calibration error, Under Voltage Detection: UVD)
Embedded 32 MHz crystal resonator and crystal oscillation circuit
Synchronous transmission mode with crystal clock
Programmable clock output via CKOUT
Programmable voltage threshold of Under Voltage Detection (UVD): 4 step (1.8 V to 2.4 V)
10-pin ceramic 3.2 mm x 2.5 mm package
Supply voltage 1.8 V to 3.6 V
Operating temperature: -40°C to +85°C
Pb-free/RoHS-compliant

SR3225SAA
Page - 2 ETM54E-07
2. Part Number
SR3225SAA A
Model name
Crystal resonator frequency
A: 32 MHz

SR3225SAA
Page - 3 ETM54E-07
3. Block Diagram
Figure 3.1 Block Diagram

SR3225SAA
Page - 4 ETM54E-07
4. Pin Assignments
4.1. Pin Assignments
(Top View)
4.2. Pin Descriptions
Table 4.1 Pin Descriptions
No.
Pin Name
Type
Function
1
TEST1
Input/Output
Pull-down
Test pin/ TxDATA input / SPI interface pin
Leave floating and make no external connections to this pin if the
function of this pin is unused.
2
EN
Input
Pull-down
Enable input, SPI interface pin
3
SCK
Input
Pull-down
SPI clock input
4
SDIO
Input/Output
Pull-down
SPI data input/output
5
CKOUT
Output
-
Clock output
6
VSSPA
Power
-
GND for PA
7
PAOUT
Output
-
Power Amp output
8
RFC
Output
-
RF choke coil
9
VDD
Power
-
Positive power supply
10
VSS
Power
-
GND

SR3225SAA
Page - 5 ETM54E-07
5. Electrical Characteristics
5.1. Absolute Maximum Rating
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
Supply voltage
VDD
VSS = 0 V
-0.3
-
4.0
V
Input voltage
Vin
VSS = 0 V
VSS –0.3
-
VDD + 0.3
V
Storage temperature
Tstg
Store as bare product
-40
-
+125
°C

SR3225SAA
Page - 6 ETM54E-07
5.2. DC Characteristics
Table 5.1 Power Supply, Operating Temperature
VSS = 0 V, Ta = -40°C to +85°C
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
Supply voltage
VDD
-
1.8
3.0
3.6
V
Supply current Powerdown
Mode
IDDPD
VDD = 3.0 V, Ta = 25°C
-
20
100
nA
VDD = 3.6 V, Ta = 85°C*1
-
-
900
Supply current
ATOSC-Active Mode
IDDAT
-
-
860
1100
μA
Supply current PLL-Active
Mode
IDDPLL
FTX = 315 MHz, FPLL = 630 MHz
-
2.2
2.5
mA
FTX = 915 MHz, FPLL = 915 MHz*1
-
2.5
2.8
mA
Supply current
Transmitter-Active Mode
IDDTMA
FTX = 315 MHz, HPWR = 1, PADUTY = 10b
Pout = 5 dBm, AM* = 0x1A*1
-
10.0
11.0
mA
Pout = 8 dBm, AM* = 0x29*1
-
12.7
13.7
Pout = 10 dBm, AM* = 0x36
-
15.0
16.0
FTX = 433MHz, HPWR = 1, PADUTY = 10b
Pout = 5 dBm, AM* = 0x16*1
-
10
11
mA
Pout = 8 dBm, AM* = 0x24*1
-
12.5
13.5
Pout = 10 dBm, AM* = 0x30*1
-
14.5
15.5
FTX = 868 MHz, HPWR = 1, PADUTY = 01b
Pout = 5 dBm, AM* = 0x19*1
-
11.7
12.7
mA
Pout = 8 dBm, AM* = 0x28*1
-
14.4
15.4
Pout = 10 dBm, AM* = 0x35*1
-
16.5
17.5
FTX = 915 MHz, HPWR = 1, PADUTY = 01b
Pout = 5 dBm, AM* = 0x19*1
-
11.8
12.8
mA
Pout = 8 dBm, AM* = 0x27*1
-
14.4
15.4
Pout = 10 dBm, AM* = 0x34*1
-
16.5
17.5
CKOUT clock output
current
IDDCK
Load capacitance is 15 pF
SR = 11b, FCKOUT = 32 MHz*1
-
-
3.0
mA
SR = 00b, FCKOUT = 2 MHz*1
-
-
0.3
Operating temperature*1
Ta
-
-40
-
+85
°C
*1 Guaranteed by design, characterization, and/or simulation only and not by production test.

SR3225SAA
Page - 7 ETM54E-07
Table 5.2 Logic I/O
VDD = 1.8 V to 6 V, VSS = 0 V, Ta = -40 °C to 5 °C
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
High level input voltage
VIH
EN, SCK, SDIO, TEST1
VDD x 0.8
-
VDD + 0.3
V
Low level input voltage
VIL
EN, SCK, SDIO, TEST1
-0.3
-
VDD x 0.2
V
High level output voltage
VOH１
SDIO, TEST1, Io = -0.4 mA
VDD x 0.9
-
-
V
VOH２
CKOUT,
If the SR = 11b is set, Io = -1 mA
If the SR = 10b is set, Io = -0.7 mA
If the SR = 01b is set, Io = -0.5 mA
If the SR = 00b is set, Io = -0.2 mA
VDD x 0.9
-
-
V
Low level output voltage
VOL１
SDIO, TEST1 (4-wire SPI mode),
Io = 0.4 mA
-
-
VDD x 0.1
V
VOL２
CKOUT,
If the SR = 11b is set, Io = 1 mA
If the SR = 10b is set, Io = 0.7 mA
If the SR = 01b is set, Io = 0.5 mA
If the SR = 00b is set, Io = 0.2 mA
-
-
VDD x 0.1
V
Pull-down resistor*1
RDOWN
EN, SCK, SDIO, TEST1
-
250
-
kΩ
Input capacitance*1
CIN
EN, SCK, SDIO, TEST1
-
5
-
pF
*1 Guaranteed by design, characterization, and/or simulation only and not by production test.
Table 5.3 Under Voltage Detector Characteristics
VSS = 0 V, Ta = -40 °C to +85 °C
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
Detector threshold
VDECT
VDD Falling
VDET = 00b
1.75
1.80
1.85
V
VDET = 01b
1.95
2.00
2.05
V
VDET = 10b
2.15
2.20
2.25
V
VDET = 11b
2.35
2.40
2.45
V
Detector release threshold
VRELE
VDD Rising
VDET = 00b
1.95
2.00
2.05
V
VDET = 01b
2.15
2.20
2.25
V
VDET = 10b
2.35
2.40
2.45
V
VDET = 11b
2.55
2.60
2.65
V

SR3225SAA
Page - 8 ETM54E-07
5.3. AC Characteristics
Table 5.4 Transmitter Characteristics
VDD = 1.8 V to 3.6 V, VSS = 0 V, Ta = -40 °C to +85 °C
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
Carrier frequency bands
FTX
-
300
-
465
MHz
600
-
930
Modulation types
-
-
ASK / OOK / FSK
ASK bit rate*1
RASK
NRZ
-
-
100
kbps
FSK bit rate*1
RFSK
NRZ
-
-
50
kbps
Carrier frequency resolution
FSTEP
Carrier frequency = 300 MHz to 465 MHz
-
-
244
Hz
Carrier frequency = 600 MHz to 930 MHz
-
-
488
Hz
FSK deviation
FDEV
±0.49
-
±996.1
kHz
ASK modulation index*1
ADEV
In OOK setting
Ratio between ON and OFF
90
-
-
%
Internal crystal frequency
FOSC
-
32
-
MHz
Internal crystal frequency
tolerance*2
FTOL
Ta = +25°C
-2
-
2
ppm
Internal crystal frequency
temperature characteristics*1
FTC
-40°C to +85°C
-20
-
20
ppm
Internal crystal oscillator
start-up time
tXTAL
See Figure 6.15
-
-
500
μs
CKOUT output frequency
FCKOUT
See Figure 6.20
0.00049
-
32
MHz
CKOUT
rise/fall time*1
tr / tf
Load capacitance15 pF, 20 to 80% VDD
SR = 11b
-
-
5
ns
SR = 10b
-
-
7
ns
SR = 01b
-
-
10
ns
SR = 00b
-
-
20
ns
CKOUT symmetry*1
SYM
SR = 11b, load capacitance 15 pF
FCKOUT = 32MHz
45
-
55
%
PLL settling time*1
tFSTE
See Figure 6.9 and Figure 6.10.
-
-
100
μs
SSB phase noise*1
FCN
FTX = 315 MHz
100 Hz offset
-
-96
-
dBc/Hz
1 kHz offset
-
-106
-
10 kHz offset
-
-110
-
100 kHz offset
-
-106
-
1 MHz offset
-
-96
-
10 MHz offset
-
-104
-
FTX = 915 MHz
100 Hz offset
-
-87
-
dBc/Hz
1 kHz offset
-
-97
-
10 kHz offset
-
-103
-
100 kHz offset
-
-96
-
1 MHz offset
-
-88
-
10 MHz offset
-
-99
-
*1 Guaranteed by design, characterization, and/or simulation only and not by production test.
*2 Without aging.

SR3225SAA
Page - 9 ETM54E-07
Table 5.5 PACharacteristics VSS = 0 V
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
Nominal output power*1, 2, 3
POUT
Ta = 25°C, VDD = 3.0 V, FTX = 315 MHz, HPWR = 1, PADUTY = 10b
AM* = 0x3F
10.0
11.0
12.0
dBm
AM* = 0x01
-6.5
-5.5
-4.5
Ta = 25°C, VDD = 3.0 V, FTX = 433 MHz, HPWR = 1, PADUTY = 10b
AM* = 0x3F
10.5
11.5
12.5
dBm
AM* = 0x01
-6.0
-5.0
-4.0
Ta = 25°C, VDD = 3.0 V, FTX = 868 MHz, HPWR = 1, PADUTY = 01b
AM* = 0x3F
9.5
11
12.5
dBm
AM* = 0x01
-7.0
-5.5
-4.0
Ta = 25°C, VDD = 3.0 V, FTX = 915 MHz, HPWR = 1, PADUTY = 01b
AM* = 0x3F
9.5
11
12.5
dBm
AM* = 0x01
-7.0
-5.5
-4.0
Ta = 25°C, VDD = 3.0 V, FTX = 315 MHz, HPWR = 0, PADUTY = 10b
AM* = 0x3F
1.0
2.0
3.0
dBm
AM* = 0x01
-16.0
-15.0
-14.0
Output power temperature
dependence*1, 2
PTMP
Ta = -40°C to +85°C,
VDD = 3.0 V
-1
-
1
dB
Output power supply voltage
dependence*1, 2
PVDD
Ta = 25°C, VDD = 1.8 V to 3.6 V, VDD = 3.0V
AM* > 0x20
-4
-
1
dB
AM* ≦0x20
-1
-
1
dB
Harmonics level*1, 2
PdBc
Ta = 25°C, VDD = 3.0 V, AM* = 0x1F, HPWR = Ratio of the 1st and 2nd harmonics
FTX = 315 / 433 MHz,
PADUTY = 10b
-
-34
-
dBc
FTX = 868 / 915 MHz
PADUTY = 01b
-
-40
-
dBc
*1 Guaranteed by design, characterization, and/or simulation only and not by production test.
*2 Test circuit is shown in Figure 5.1.
*3 Without aging.

SR3225SAA
Page - 10 ETM54E-07
FTX
C1
C2
C3
C4
C5
L1
L2
315 MHz
0.1 μF
560 pF
7 pF
82 pF
10 pF
100 nH
39 nH
433 MHz
0.1 μF
560 pF
7 pF
22 pF
10 pF
82 nH
27 nH
868 MHz
0.1 μF
100 pF
3 pF
33 pF
5pF
22 nH
10 nH
915 MHz
0.1 uF
100 pF
3 pF
22 pF
5pF
22 nH
10 nH
Figure 5.1 PAOUTAC Test Circuit
Inductor: TDK MLG1005S series
Capacitor: TDK C1005C0G1 series

SR3225SAA
Page - 11 ETM54E-07
Table 5.6 SPI Interface Characteristics
VDD = 1.8 V to 3.6 V, VSS = 0 V, Ta = -40°C to +85°C
Item
Symbol
Condition
Standard
Unit
Min.
Typ.
Max.
SCK clock cycle
tSCK
-
330
-
-
ns
SCK H pulse width
tWH
-
150
-
-
ns
SCK L pulse width
tWL
-
150
-
-
ns
SCK rise and fall time
tRF
-
-
-
20
ns
SCK setup time
tSCKS
-
100
-
-
ns
EN setup time
tES
-
150
-
-
ns
EN hold time
tEH
-
100
-
-
ns
EN recovery time
tER
-
100
-
-
ns
EN rise and fall time
tENRF
-
-
-
30
ns
Write data setup time
tDS
-
20
-
-
ns
Write data hold time
tDH
-
20
-
-
ns
Read data delay time
tRD
CL = 50 pF
0
-
100
ns
SDIO output disable time
tRZ
CL = 50 pF
0
-
100
ns

SR3225SAA
Page - 12 ETM54E-07
6. Function Description
6.1. Outline
RF transmitter module SR3225SAA is a wireless transmitter module for the UHF range. This module houses a
crystal resonator, capacitors for an oscillation circuit, a PLL, and a PowerAmp in a 3.2 mm x 2.5 mm ceramic
package. The crystal resonator is optimally matched with the IC at the factory. The SR3225SAA is ideal for small
wireless transmitters because wireless transmission can be achieved simply by combining it with an external
controller.
As you can control the wireless transmitter settings via the SPI interface, the SR3225SAAsupports carrier
frequency of 300-465 MHz, 600-930 MHz. You can selectASK, OOK, or FSK modulation. Soft-ASK and
Soft-FSK are provided to reduce modulation bandwidth.
This module has a fail-safe function. If a failure is detected, it shuts down the power supply to PA.
The signals of the internal crystal oscillator are outputted from the CKOUT pin. They can be used as clock source
and interrupt signal for an MCU.
6.2. SPI Interface
SR3225SAA has a 3-wire/4-wire SPI interface.
It is used to access SFR, which controls operations, and to transmit modulated signals using transmit commands.
EN
The EN pin is used to input SPI enable signal, control SPI communications, and input the timing to latch
transmission data.
When the EN pin rises, the mode of SR3225SAA is transited from Powerdown mode toATOSC-Active mode,
and 2 MHz (32 MHz divided by 16) is outputted from the CKOUT pin after tXTAL. (Max: 500 μs) When the EN
pin falls, the SPI interface is initialized. If the EN pin is kept low at least 8.2 ms (218 crystal clocks), the state
transits to Powerdown mode.
After sending the transmit command (if bit “B” = 1), the EN pin additional function is available. The SDIO signal
is latched as transmission data at the falling edge of the EN signals.
SCK
The SCK pin is the clock input for SPI. This pin is used for loading SDIO data, synchronized with the SCK
falling edge.
SDIO
The SDIO pin is the bi-directional data input/output pin for 3-wire SPI mode. It also works as data input pin for
4-wire SPI mode.
The SDIO pin is used for RF transmission data input during RF data transfer. If you select RF transmission data
input through the TEST1 pin, the SDIO signals do not affect RF data transmission. See section 6.2.4 for details.
TEST1
The TEST1 pin is used for data output in 4-wire SPI mode.
If you select this pin to data input for RF data transmission, this TEST1 pin becomes the data input pin. See
section 6.2.4 for details.

SR3225SAA
Page - 13 ETM54E-07
SPI interface mode change6.2.1.
The SPI interface mode is changed by setting IFSEL[1:0], which is assigned to SFR address 0x15. (See Table 6.1
and Figure 6.1.)
When connecting SR3225SAA with MCU in 4-wire SPI mode, you can write data without setting IFSEL[1:0]. To
read data, set IFSEL[1:0].
Table 6.1 Interface Mode Setting
IFSEL[1:0]
SPI mode
Transmission data
input pin
00b
3-wire SPI mode (default)
SDIO
01b
4-wire SPI mode
SDIO
10b
3-wire SPI mode
TEST1
11b
Invalid
3-wire SPI mode 4-wire SPI mode
Figure 6.1 HOST Interface Example

SR3225SAA
Page - 14 ETM54E-07
SFR access command6.2.2.
You can access SFR using 3-wire and 4-wire SPI mode.
Figure 6.2 depicts the timing for writing access in 3-wire and 4-wire SPI modes, Figure 6.3 shows the timing for
read access in 3-wire SPI mode, and Figure 6.4 shows the timing for read access in 4-wire SPI mode.
Figure 6.2 WriteAccess to SFR
Figure 6.3 3-wire SPI ReadAccess to SFR
Figure 6.4 4-wire SPI ReadAccess to SFR

SR3225SAA
Page - 15 ETM54E-07
As the loading of data is synchronized with SCK falling, the output data is updated with the SCK rising edge.
After the rising of the EN pin, write the 2 bits of the command bit shown in Table 6.2 and the 6 bits of the
address. If the command is SFR writing, the host may continue sending data to be written on SFR. If the
command is SFR reading, this device shifts out the data of SFR.
Table 6.2 Command Bit
Command bit
Function
00b
SFR reading
01b
SFR writing
10b
Not available
11b
Transmit command
SR3225SAA supports burst write and read. Figure 6.5 depicts the timing for burst write access in 3-wire and
4-wire SPI modes, Figure 6.6 shows the timing for burst read access in 3-wire SPI mode, and Figure 6.7 shows
the timing for burst read access in 4-wire SPI mode. While burst writing & reading, the SFR address is
incremented automatically from any address sent by the command address bit.
It is recommended to reset the SFR communication by setting EN pin low after SFR access is finished.
If the EN pin is not set to low, external noise may cause unintentional write access.
Figure 6.5 Burst WriteAccess to SFR
Figure 6.6 3-wire SPI Burst ReadAccess to SFR
Figure 6.7 4-wire SPI Burst ReadAccess to SFR

SR3225SAA
Page - 16 ETM54E-07
SPI checksum6.2.3.
SPI checksum is available (Figure 6.8).
The XOR arithmetic calculation of command + address 8 bits and data 8 bits is operated during SFR write access.
The checksum result is stored in 0x16 SFR address. The checksum is reset by transiting to Powerdown mode or
writing any data to checksum register (address 0x16).
Figure 6.8 SPI Checksum Process Block Diagram
Table 6.3 shows SPI checksum example. If you write 0x02 in address 0x04 and 0x01 in address 0x05, the value
0x02 is stored in checksum register.
Table 6.3 SPI Checksum Calculation Example
Transmission byte by SPI
Checksum result
0100 0100 (Write + Address)
0100 0100
0000 0010 (Data)
0100 0110
0100 0101 (Write + Address)
0000 0011
0000 0001 (Data)
0000 0010
SPI shift register XOR Checksum SFR
Address:0x16
Read Access
/ Write Clear
8
8
8