Epson RX8130 CE Instructions for use

ETM50E-05
Preliminary
Application Manual
Real Time Clock Module
RX8130 CE

NOTICE
•This material is subject to change without notice.
•Any part of this material may not be reproduced or duplicated in any form or any means without the
written permission of Seiko Epson.
•The information about applied circuitry, software, usage, etc. written in this material is intended for
reference only. Seiko Epson does not assume any liability for the occurrence of infringing on any
patent or copyright of a third party. This material does not authorize the licensing for any patent or
intellectual copyrights.
•When exporting the products or technology described in this material, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws and
regulations.
•You are requested not to use the products (and any technical information furnished, if any) for the
development and/or manufacture of weapon of mass destruction or for other military purposes. You
are also requested that you would not make the products available to any third party who may use the
products for such prohibited purposes.
•These products are intended for general use in electronic equipment. When using them in specific
applications that require extremely high reliability, such as the applications stated below, you must
obtain permission from Seiko Epson in advance.
/ Space equipment (artificial satellites, rockets, etc.) / Transportation vehicles and related
(automobiles, aircraft, trains, vessels, etc.) / Medical instruments to sustain life /
Submarine transmitters / Power stations and related / Fire work equipment and security
equipment / traffic control equipment / and others requiring equivalent reliability.
•All brands or product names mentioned herein are trademarks and/or registered trademarks of their
respective.

ETM50E Revision History
Rev No.
Date
Page
Description
ETM50E-01
--
--
ETM50E-02
05.Oct.2015
Release
ETM50E-03
10.May.2016
1
Corrected a the block diagram.
4
Add description to [3.2. Pin Functions].
9
Corrected a [10.1. Characteristic for the fluctuation of the power
supply ]
13
Corrected a [7) Clock output function]
27
Corrected a [14.7.2. Related register of Battery backup
switchover function]
ETM50E-04
20.Sep.2016
3
Updated the Recommended soldering pattern
Optimization of the text.
ETM50E-05
23.Jan.2018
2
Added terminal processing when output terminal is not used.
3
Added typical value of external dimensions.
3
Added recommended soldering pattern.
6
Corrected Max. value of Hihgh- Level input voltage.
8
Corrected reset delay time (at recovery form backup).
9
Corrected access wait time.
20
Changed 7) TSTP bit related table.
21
Added timer circuit block diagram
25
Added alarm circuit block diagram
27
Added time update circuit block diagram
30
Corrected table operation stages of voltage detection.
36
Added comment to wait time.
37
Added comments related to STOP bit in 3)The setting of the
clock and calendar.
42
Added address circulation table of auto increment function.

RX8130 CE
ETM50E-05
Contents
1. Overview........................................................................................................................1
2. Block Diagram ...............................................................................................................1
3. Terminal description .....................................................................................................2
4. Examples of external connection...................................................................................2
5. External Dimensions / Marking Layout...........................................................................3
6.Absolute Maximum Ratings...........................................................................................4
7. Recommended Operating Conditions............................................................................4
8. Frequency Characteristics.............................................................................................4
9.Electrical Characteristics ..............................................................................................5
10. Matters that demand special attention on use..............................................................9
11. Reference information ...............................................................................................11
12. Application notes .......................................................................................................12
13. Overview of Functions and Description of Registers................................................13
13.1. Overview of Functions..................................................................................................................13
13.2. Register table ...............................................................................................................................14
13.3. Description of registers.................................................................................................................15
14. How to use.................................................................................................................17
14.1. Clock calendar explanation ..........................................................................................................17
14.2. Fixed-cycle Timer Interrupt Function............................................................................................18
14.3. Alarm Interrupt Function...............................................................................................................23
14.4. Time Update Interrupt Function....................................................................................................26
14.5. Frequency stop detection function ...............................................................................................28
14.6.FOUT function [clock output function] ..........................................................................................28
14.7. Battery backup switchover function..............................................................................................28
14.8. Reset output function ...................................................................................................................33
14.9. Detection voltage setting..............................................................................................................34
14.10. Digital offset function..................................................................................................................34
14.11. Flow-chart...................................................................................................................................36
14.12. Reading/Writing Data via the I2C Bus Interface .........................................................................40

RX8130CE

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ETM50E-05
Build-in backup battery charge control function
SERIAL-INTERFACE REAL TIME CLOCK MODULE
RX8130CE
•Built in frequency adjusted 32.768 kHz crystal unit.
•Interface type : I2C-Bus interface (up to 400 kHz)
•Wide operating voltage range : 1.6Vto5.5V
•Wide timekeeper voltage range : 1.1Vto5.5V
•Auto power switching function : Switchover by main power supply monitor.
•Backup battery charge control function : For rechargeable lithium batteries.
•Low leak current : A leak current from a backup power supply pin. 5nA (Max.)
•Reset function : At low supply voltage, external reset signal is generated.
•Low voltage detection : supply voltage and backup voltage detection
•Time correction : digital offset function
•The various function include full calendar, alarm, timer, etc.
The I2C-Bus is a trademark of NXP Semiconductors.
1. Overview
This is a real-time clock module of the serial interface system that incorporates a 32.768 kHz crystal oscillator.
The real-time clock function incorporates not only a calendar and clock counter for the year, month, day, day of the
week, hour, minute, and second, but also a time alarm, interval timer, and time update interruption, among other
features. By the backup battery charge control function and the interface power supply input pin, RX8130CE can
support various power supply circuitries.
All of these many functions are implemented in a thin, compact ceramic package, which makes it suitable for various
kinds of small electronic devices.
2. Block Diagram
VOUT
FOUT
VBAT
GND
(System
Control)
Logic Area
SDA
SCL
VDD
Reset
(Delay)
/RST
VIO
CMP
Power
Control
VBAT
Detector
(VDET1)
(VDET2)
(VDET3)
(VDET4)
（VCMP）
Register
Flag
VDD
Detector
OSC
32.768kHz
/IRQ
Divider
Divider
Clock
and
Calendar
Timer
Register
Alarm
Register
Bus
Interface
FOUT Controller
Interrupts
Controller

RX8130CE
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ETM50E-05
3. Terminal description 
3.1. Terminal connections
RX8130CE
1.
VIO
10.
VBAT
2.
SCL
9.
VOUT
3.
SDA
8.
VDD
4.
FOUT
7.
GND
5.
/RST
6.
/IRQ
3.2. Pin Functions
Signal
name
I/O
Function
SCL
Input
Serial clock input pin.
SDA
Bi-directional
Data input and output pin.
FOUT
Output
Frequency output pin with output control function. (CMOS)
Output frequency can be selected as 32.768kHz, 1024Hz, 1Hz.
/ RST
Open-Drain
Output
Even in the backup mode, this pin can opperate. In case of VDD voltage drop detection, a
reset signal is outputted.
In case of VDD voltage rise detection, it releases the reset signal after 60ms.
/ IRQ
Open-Drain
Output
Interrupt output by Alarm and Timer events.(N-ch open drain)
This pin can output even a backup mode.
VDD

This is a power-supply pin for the internal logic.
VIO

This is a interface power supply pin. (There is an level shifter between VDD and VIO)
VOUT

Internal voltage output pin.
Connect smoothing capacitor of 1.0uF
VBAT

This is a power supply pin for backup battery.
This is a pin to connect a large-capacity capacitor, a secondary battery, and a primary
battery.
In a backup mode, the voltage is supplied inside by this pin.
GND

Connected to a ground.
Note: Connect a bypass capacitor rated at least 0.1μF between power supply pins and GND pin.
Note: Input pins are able to input up to 5.5V regardless of VIO applied voltage.
Note: Open drain pins are able to Pull-up to 5.5V regardless of VIO applied voltage.
Note: Use the FOUT, /RST, /IRQ terminals as OPEN when not in use.
4. Examples of external connection
4.1. Examples of power supply connection
VDD
VBAT
VIO
VD1.8
VD3
R
0.1F
secondary
battery
EDLC
or
0.1F
1.0F
VOUT
0.1F
VDD
VBAT
VIO
VD3
VD3
R
0.1F
secondary
battery
EDLC
or
1.0F
VOUT
0.1F
VDD
VBAT
VIO
VD3
R
0.1F
Primary
battery
1.0F
VOUT
0.1F
(2) Same I/F voltage and
charge voltage
(CHGEN=1, INIEN=1)
(3) Primary battery as backup
(CHGEN=0)
(1) Case of different I/F voltage
and charge vlotage

RX8130CE
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ETM50E-05
5. External Dimensions / Marking Layout
5.1. External Dimensions
RX8130CE
•External dimensions •Recommended soldering pattern
Unit : mm
3.2 0.2 (Typ.3.24)
"CE"PKGRev.04
2.5±0.2 (Typ.2.54)
1.0Max.
0.7
0.3
0.62
0.42
0.2Min.
0.4
0.35
0.7
0.4
0.9
1.1
0.3
0.7
0.4
0.9
1.1
Type.1 (for small mounting area)
Type.2
5.2. Marking Layout
RX8130CE
#1 Pin Mark
Logo
Production lot
R8130

A123B
Type
Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning.

RX8130CE
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ETM50E-05
6.Absolute Maximum Ratings
GND=0V
Item
Symbol
Condition
Rating
Unit
Supply voltage
VDD

0.3

+6.5
V
Internal voltage
VOUT

0.3

+6.5
V
Backup supply voltage
VBAT

0.3

+6.5
V
Interface
supply voltage
VIO

0.3

+6.5
V
Input voltage 1
VIN1
SCL, SDA
0.3

+6.5
V
Output voltage 1
VOUT1
/RST, /IRQ, SDA
0.3

+6.5
V
Output voltage 2
VOUT2
FOUT
-0.3

VIO+0.3
V
Storage temperature
TSTG
When stored separately,
without packaging
55
to
+125
C
7. Recommended Operating
Conditions
*Unless otherwise specified, GND=0V,Ta=40Cto+85C 
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating supply voltage
VDD
Normal operation mode (VDD)
1.25
3.0
5.5
V
Interface supply voltage
VIO
VDD=VDET1 5.5V
The interface halts
when VDD becomes less than VDET1.
1.6
3.0
5.5
V
Clock supply voltage
VCLK
Backup operation mode (VBAT)
1.1
3.0
5.5
V
Operating temperature
T_use
No condensation
40
+25
+85
C
Minimum value of Clock supply voltage VCLK is the timekeeping continuation lower limit value that initialized RX8130 in operating
supply voltage VDD.
8. Frequency Characteristics
*Unless otherwise specified, GND=0V,Ta=40Cto+85C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Output frequency
fo
32.768
(Typ.)
kHz
Frequency stability
f/f
Ta=+25C
VDD=3.0V
523
(1)
106
Frequency/voltage
characteristics
f/V
Ta=+25C
VDD=1.1V5.5V
2
+2
106/V
Frequency/temperature
characteristics
Top
Ta=20C+70C
VDD=3.0V;+25C reference
120
+10
106
Oscillation start time
t_str
VDD=2.75V5.5V
Internal X'tal oscillation start
0.19
1.0
s
Aging
fa
Ta=+25C,VBAT=3.0V;
first year
5
+5
106
/year
1 ) The monthly error is equal to 60 seconds. ( excluding offset )

RX8130CE
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Page5
ETM50E-05
9.Electrical Characteristics
9.1.DC characteristics
*Unless otherwise specified, GND=0V,Ta=40Cto+85C
9.1.1.DC characteristics(1)
*Unless otherwise specified, GND =0V,VBAT=VDD=1.1V5.5V,VIO=1.6V5.5V,
Ta=40C +85C 
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Current consumption in
normal operation mode
without FOUT (1)
IDD
SCL=SDA = ”H” ,
FOUT=OFF, /IRQ=OFF,
VDD=VIO=3.0V, -40C+85C
CHGEN=0b or VBAT≧VDET3
1500
1600
nA
Current consumption in
normal operation with
FOUT (2)
I32k
SCL=SDA = ”H” ,
FOUT=32.768kHz, /IRQ=OFF,
VDD=VIO=3.0V, -40C+85C
FOUT pin CL=15pF
CHGEN=0b or VBAT≧VDET3
3.5
4.0
uA
Current consumption in
backup mode(3)
IBAT
SCL=SDA = ”L” ,
VBAT=3.0V ,VDD=VIO=0.0V, -40C+85C
300
500
nA
Detector Threshold
Voltage1
(rising edge of VDD )
+VDET11
2.75V setting Reset-releases
2.72
2.80
2.88
V
Detector Threshold
Voltage1
(falling edge of VDD )
-VDET11
2.75V setting、Reset output
2.67
2.75
2.83
V
Detector Threshold
Voltage2
(rising edge of VDD )
+VDET12
2.7V setting Reset-releases
2.67
2.75
2.83
V
Detector Threshold
Voltage2
(falling edge of VDD )
-VDET12
2.7V setting , Reset output
2.62
2.70
2.78
V
Detector Threshold
Voltage3
(rising edge of VDD )
+VDET2
Switching voltage from VBAT to VDD
1.25
1.35
1.45
V
Detector Threshold
Voltage3
(falling edge of VDD )
-VDET2
Switching voltage from VDD to VBAT
1.20
1.30
1.40
V
Detector Threshold
Voltage1
(rising edge of VBAT)
+VDET31
Charge stop voltage (full charge)
BFVSEL=00b
2.94
3.02
3.10
V
Detector Threshold
Voltage1
(falling edge of VBAT)
-VDET31
Recharge voltage.
BFVSEL=00b
2.89
2.97
3.05
V
Detector Threshold
Voltage2
(rising edge of VBAT)
+VDET30
Charge stop voltage (full charge)
BFVSEL=10b
2.84
2.92
3.00
V
Detector Threshold
Voltage2
(falling edge of VBAT)
-VDET30
Recharge voltage.
BFVSEL=10b
2.79
2.87
2.95
V
Detector Threshold
Voltage3
(rising edge of VBAT)
+VDET32
Charge stop voltage (full charge)
BFVSEL=01b
3.00
3.08
3.16
V
Detector Threshold
Voltage3
(falling edge of VBAT)
-VDET32
Recharge voltage.
BFVSEL=01b
2.95
3.03
3.11
V
VBAT end voltage
-VDET4
Low VBATdetection
Register flag VBLF = 1b
2.32
2.40
2.48
V
VDD-VOUT
off-leak current
ISW1
VOUT=3.0V、VDD=0.0V
5.0
nA
VBAT-VOUT
off-leak current
ISW2
VBAT=3.0V、VOUT=0.0V
5.0
nA

RX8130CE
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Page6
ETM50E-05
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
VOUT output voltage 1
VVOUT1
VDD=3.0V、IOUT=1mA
VDD-0.06
V
VOUT output voltage 2
VVOUT2
VBAT=3.0V、IOUT=0.1mA
VBAT-0.02
V
High-level
input voltage
VIH1
SCL, SDA
0.8 VIO
5.5
V
Low-level
input voltage
VIL
SCL, SDA
GND 0.3
0.2 VIO
V
High-level
output voltage
VOH
FOUT
IOH=-1 mA
VIO–0.5
VIO
V
Low-level
output voltage
VOL1
FOUT
IOL=1 mA
GND
GND+0.5
V
VOL2
/RST,/IRQ
VIO=5 V, IOL=1 mA
GND
GND+0.25
V
VOL3
VIO=3 V, IOL=1 mA
GND
GND+0.4
V
VOL4
SDA
VIO 2 V, IOL=3 mA
GND
GND+0.4
V

RX8130CE
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ETM50E-05
9.2. AC characteristics
9.2.1. AC characteristics(1)
*Unless otherwise specified, GND =0V,VIO=1.6V5.5V,Ta=40C +85C
Item
Symbol
Standard-Mode
(fSCL=100kHz)
Fast-Mode
(fSCL=400kHz)
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
fSCL
100
400
kHz
Start condition setup time
tSU;STA
4.7
0.6
s
Start condition hold time
tHD;STA
4.0
0.6
s
Data setup time
tSU;DAT
250
100
ns
Data hold time
tHD;DAT
0
0
ns
Stop condition setup time
tSU;STO
4.0
0.6
s
Bus idle time between
start condition and stop condition
tBUF
4.7
1.3
s
Time when SCL = "L"
tLOW
4.7
1.3
s
Time when SCL = "H"
tHIGH
4.0
0.6
s
Rise time for SCL and SDA
tr
1.0
0.3
s
Fall time for SCL and SDA
tf
0.3
0.3
s
Allowable spike time on bus
tSP
50
50
ns
• Timing chart
tHD ; DAT
tSU ; DAT
tHD ; STA
tLOW
tHIGH
1 / fSCL
tr
tf
tSU ; STA
SDA
SCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACK
(A)
Protocol
tBUF
tSU ; STO
STOP
CONDITION
(P)
START
CONDITION
(S)
(P)
(A)
tHD ; STA
tSU ; STA
(S)
BIT 0
LSB
(R/W)
(S)
tSP
Warning: When accessing this device, all communication from transmitting the start condition to transmitting the stop
condition after access should be completed within 0.95 seconds.
If such communication requires 0.95 seconds or longer, the I2C bus interface is reset by the internal bus
timeout function.
When bus-time-out occur, SDA turns to Hi-Z input mode.
Note:During access to the time registers, the time counting is on hold! This means that up to 1 second can be “lost” in
case of unsuccessful communication as mentioned above!
Please make sure to send I2C start condition before actual transmission of the RTCs slave address as
otherwise the slave address appears to be shifted by 1 bit!
9.2.2. AC characteristics(2)
※Unless otherwise specified､GND=0 V , VIO=1.6 V 5.5 V , Ta= 40 C +85 C
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
FOUT symmetry
SYM
50% VIO Level
40
60
%

RX8130CE
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ETM50E-05
9.2.3. AC characteristics(3)
Item
symbol
Min
Typ
Max
unit
Reset internal delay time
tDELAY
60
ms
Reset delay time
(Initial power ON)
tDELAYF
250
(t_str+tDELAY)
ms
Timing chart
VDD
/RST
tDELAY
+VDET11
+VDET12
t_str
tDELAYF
* t_str is oscillation startup time.
Item
symbol
Min
Typ
Max
unit
Reset delay time
(Recovery from Backup)
t_int+t_DELAY
tDELAYB
60
95
ms
Timing chart
VDD
/RST
tDELAY
+VDET11
+VDET12
t_int
tDELAYB
+VDET2
*t_int is an intermittence drive timing of a VDET2 detect circuit.Maximum value is 35ms.

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Page9
ETM50E-05
10. Matters that demand special attention on use
10.1. Characteristic for the fluctuation of the power supply
*This circuit is sensitive to power supply noise and supply voltage should be stabilized to avoid negative impact on the
accuracy.
* tR1 is needed for a proper power-on reset. If this power-on condition can not be kept, it is necessary to send a
initialization routine to the RTCby software.
*In case of repeated ON/OFF of the power supply within short term, it is possible that the power-on reset becomes
unstable.
After power-OFF, keep VDD=VBAT=GND for more than 10 seconds for a proper power-on reset.
When it is impossible, please initialize the RTC by the software.
*Before shifting to a backup operation, please transfer stop condition and finish communication as otherwise data
might be lost or a time error of 1sec might occur.
VDD
VCLK
GND
VDD
tR1
tF
tR2
+VDET11
Backup mode
tCL
tCD
tCU
-VDET11 or
-VDET12 *
+VDET11 or
+VDET12 *
* It depends on register setting
before a switching to backup
I2CIF
VDD
Access is possible
VOUT
Access is impossible
Access is
possible
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Power supply rise time
tR1
From GND to VDD=+VDET11
0.1
-
10
ms / V
access wait time
(Initial power on)
tCL
After arrival to VDD=+VDET11
30
-
-
ms
Backup switchover
start wait time
tCD
After the access end
0
-
-
ms
Power supply fall time
tF
From VDD toVDD=-VDET1x
1
-
-
ms / V
Power supply rise time
(Recovery from Backup)
tR2
Recovery to the operating voltage
1
-
-
ms / V
Access wait time
(Recovery from Backup)
tCU
After arrival to VDD=+VDET1x
35
-
-
ms

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Page10
ETM50E-05
10.2. Restrictions on Access Operations During Power-on Initialization and Recovery from Backup
•
Because most of RTC registers are synchronized with the oscillation clock of the built-in crystal oscillator, the RTC does
not work normally without the integrated oscillator having stabilized. Please initialize the RTCat the time thepower supply
voltage returns (VLF = 1) after the oscillation has stabilized (after oscillation start time tSTA).
If intending to access the RTC after the main supply voltage returns, please note following points:
VDD
VDD detect voltage +VDET11
 Internal oscillation
(illustration)
t_str
Oscillation start time
(internal oscillation wait
time)
•Access is enabled
•Normal operation start
Minimum voltage for clock maintenance
VCLK(Min.)[V]
During power-on initialization or power
supply voltage recovery after drop in clock
maintenance voltage
30[ms]
After 30 ms progress, Confirm a state by VLF-bit
At the time of VLF=1: After a t_str wait, initial setting is necessary.
At the time of VLF=0: Register access is possible.
VOUT
/RST
FOUT
t_DELAY
t_DELAYF
• Recovery from Backup
VOUT
VDD
VDD detect voltage +VDET11 or +VDET12
（register setting）
Minimum voltage for clock maintenance VCLK(Min.)[V]
Recovery from Backup
After t_int progress, access is enabled.
After VLF confirmation, it is similar
to initial power ON.
/RST
FOUT
t_DELAY
t_DELAYB
t_int

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Page11
ETM50E-05
11. Reference information
11.1. Reference Data
(1)Example of frequency and temperature characteristics
-150
-100
-50
0
-50
0
50
100
Temperature [C]
Frequency fT
10-6
T= +25 C Typ.
= -0.035 10-6 Typ.
[Finding the frequency stability]
1.Frequency and temperature characteristics can be
approximated using the following equations.

fT=

(

T

X)2


fT: Frequency deviation in any temperature


[1/

C2]: Coefficient of secondary temperature
(0.0350.005)106/

C2


T[

C]: Ultimate temperature (+255

C)


X[

C]: Any temperature
2.To determine overall clock accuracy, add the
frequency precision and voltage characteristics.

f/f=

f/fo+

fT+

fV


f/f : Clock accuracy (stable frequency)
in any temperature and voltage.


f/fo : Frequency precision


fT: Frequency deviation in any temperature.


fV: Frequency deviation in any voltage.
3.How to find the date difference
Date Difference =

f/f

86400(Sec)
 For example:

f/f = 11.57410-6 is an error of
approximately 1 second/day.

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ETM50E-05
12. Application notes
1) Notes on handling
This module uses a C-MOS IC to realize low power consumption. Carefully note the following cautions when handling.
(1) Static electricity
While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by
a large discharge of static electricity. Containers used for packing and transport should be constructed of conductive materials.
In addition, only soldering irons, measurement circuits, and other such devices which do not leak high voltage should be used
with this module, which should also be grounded when such devices are being used.
(2) Noise
If a signal with excessive external noise is applied to the power supply or input pins, the device may malfunction or "latch up."
In order to ensure stable operation, connect a filter capacitor (preferably ceramic) of greater that 0.1F as close as possible
to the power supply pins. Also, avoid placing any device that generates high level of electronic noise near this module.
(3) Voltage levels of input pins
When the voltage of out of the input voltage specifications range input into an input terminal constantly, a penetration electric
current occurs. Thus, current consumption increases very much. This causes Latch-up, and there is the case that, as a result, a
built-in IC is destroyed. Please use an input terminal according to input voltage specifications.
Furthermore, please input the VIO or GND most recent voltage as much as possible.
(4) Handling of unused pins
Disposal of unused input terminals. When an input terminal is open state, it causes increase of a consumption electric current
and the behavior that are instability. Please fix an unused input terminal to the voltage that is near to VIO or GND.
2) Notes on packaging
(1) Soldering heat resistance.
If the temperature within the package exceeds +260 C, the characteristics of the crystal oscillator will be degraded and it may
be damaged. The reflow conditions within our reflow profile is recommended. Therefore, always check the mounting
temperature and time before mounting this device. Also, check again if the mounting conditions are later changed.
(2) Mounting equipment
While this module can be used with general-purpose mounting equipment, the internal crystal oscillator may be damaged in
some circumstances, depending on the equipment and conditions. Therefore, be sure to check this. In addition, if the
mounting conditions are later changed, the same check should be performed again.
(3) Ultrasonic cleaning
Depending on the usage conditions, there is a possibility that the crystal oscillator will be damaged by resonance during
ultrasonic cleaning. Since the conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time,
state of the inside of the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic
cleaning.
(4) Mounting orientation
This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device before
mounting.
(5) Leakage between pins
Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure the
device is dry and clean before supplying power to it.
(6) Installation of charged battery.
When a charged backup battery is installed by soldering, battery connection terminal of this device should connect to
GND, beforehand.

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Page13
ETM50E-05
13. Overview of Functions and Description of Registers
Note:
The initialization of the register is necessary about the unused function.
13.1. Overview of Functions
1) Clock functions
This function is used to set and read out second, minute, hour, day, month, year ( to the last two digits), and date
data.
Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the
year 2099.
At the start of a I2C communication, the time and clock counting stops (which causes loss of time), and clock starts
automatically again at the end of the I2C communication.
2) Fixed-cycle Timer Interrupt function
The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between
244.14sand 65535 hours.
When an interrupt event is generated, the /IRQ pin goes to low level ("L") and "1" is set to the TF bit to report that
an event has occurred.
3) Long-Timer function
It is able to use fixed cycle timer interrupt function as Long-Timer or usage counter.
This function measures the operation time on the main power supply and the operation time on the backup power
supply and can automatically sum them up.
4) Alarm interrupt function
The alarm interrupt function generates interrupt events for alarm settings such as date, day, hour, and minute
settings. When an interrupt event occurs, the AF bit value is set to "1"and the /IRQ pin goes to low level to
indicate that an event has occurred.
5) Time Update Interrupt Function
The time update interrupt function generates interrupt in one-second or one-minute intervals which are
synchronized to the update of the second or minute time register of the RTC When an interrupt event is generated,
the /IRQ pin goes to low level ("L") and "1" is set to the UF bit to report that an event has occurred.
6) Frequency stop detection function
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to "1"
when data loss might have occured due to a low supply voltage.
7) Clock output function
A clock with the same frequency (32.768 kHz) as the built-in crystal resonator can be output from the FOUT pin.
Output could also be 1Hz, or 1024Hz.
8) User RAM
RAM register is read/write accessible for any data.
9) Digital offset function
The clock precision can be increased by adding a time offset.

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Page14
ETM50E-05
13.2. Register table
13.2.1. Register table
Address[h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
10
SEC

40
20
10
8
4
2
1
11
MIN

40
20
10
8
4
2
1
12
HOUR


20
10
8
4
2
1
13
WEEK

6
5
4
3
2
1
0
14
DAY


20
10
8
4
2
1
15
MONTH



10
8
4
2
1
16
YEAR
80
40
20
10
8
4
2
1
17
MIN Alarm
AE
40
20
10
8
4
2
1
18
HOUR Alarm
AE
•
20
10
8
4
2
1
19
WEEK Alarm
AE
6
5
4
3
2
1
0
DAY Alarm
•
20
10
8
4
2
1
1A
Timer Counter 0
128
64
32
16
8
4
2
1
1B
Timer Counter 1
32768
16384
8192
4096
2048
1024
512
256
1C
Extension Register
FSEL1
FSEL0
USEL
TE
WADA
TSEL2
TSEL1
TSEL0
1D
Flag Register
VBLF

UF
TF
AF
RSF
VLF
VBFF
1E
Control Register0
TEST
STOP
UIE
TIE
AIE
TSTP
TBKON
TBKE
1F
Control Register1
SMP
TSEL1
SMP
TSEL0
CHG
EN
INIEN

RS
VSEL
BF
VSEL1
BF
VSEL0
Address[h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
20
|
23
RAM
User Register
32 bit ( 4 word x 8 bit )
Address[h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
30
Digital offset
DTE
L7
L6
L5
L4
L3
L2
L1
1.
After the initial power-up (from 0V) or in case the VLF bit returns "1" , make sure to initialize all registers,
before using the RTC.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
time data is incorrect.
2.
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing. Be sure to
write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing
3.
Any bit marked with "" should be used with a value of "0" after initialization
4.
Any bit marked with "•"is a RAM bit that can be used to read or write any data.
5.
User Register is a free register which can be used as user RAM.
6.
The above table shows only the user registers. Due to functional reasons, RTC has different registers not
mentioned above table which are programmed by the manufactorer. Please make sure to only access above
mentioned user registers.

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Page15
ETM50E-05
13.2.2. Register initial value , and Read/Write operation table
【０： Write impossible、Read value "0"Fix 】
【X：Undefined （Initialization by register writing is needed）】
【0：Reset state 】
【1：Set state 】
Address[h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
10
SEC
0
X
X
X
X
X
X
X
11
MIN
0
X
X
X
X
X
X
X
12
HOUR
0
0
X
X
X
X
X
X
13
WEEK
0
X
X
X
X
X
X
X
14
DAY
0
0
X
X
X
X
X
X
15
MONTH
0
0
0
X
X
X
X
X
16
YEAR
X
X
X
X
X
X
X
X
17
MIN Alarm
X
X
X
X
X
X
X
X
18
HOUR Alarm
X
X
X
X
X
X
X
X
19
WEEK Alarm
X
X
X
X
X
X
X
X
DAY Alarm
X
X
X
X
X
X
X
1A
Timer Counter 0
X
X
X
X
X
X
X
X
1B
Timer Counter 1
X
X
X
X
X
X
X
X
1C
Extension Register
0
0
0
0
0
1
0
0
1D
Flag Register
0
0
0
0
0
1
1
0
1E
Control Register0
0
0
0
0
0
0
0
0
1F
Control Register1
0
0
0
0
0
0
0
0
Address[h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
20-23
RAM
X
X
X
X
X
X
X
X
Address[h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
30
Digital offset
0
0
0
0
0
0
0
0
13.3. Description of registers
13.3.1. Clock and calender counter (10[h]16[h])
This is counter registers from a second to a year.
Please refer to [14.1 Clock calendar explanation] for details.
13.3.2. RAM registers (20[h]23[h])
This RAM register is read/write accessible for any data in the range from 00h to FFh.
13.3.3. Alarm registers (17[h]19[h])
The alarm interrupt function is used, along with the AE, AF, and WADA bits, to set alarms for specified date, day,
hour, and minute values.
Please refer to [14.3. Alarm Interrupt Function ] for the details.
13.3.4. Timer setting and Timer counter register (1A[h]1E[h])
This register is used to set the default (preset) value for the counter.
To use the fixed-cycle timer interrupt function,TE,TF,TIE,TSEL2,TSEL1,TSEL0,TBKON,TBKE bits are
set and used. When the fixed-cycle timer interrupt function is not being used, the fixed-cycle timer control register
can be used as a RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and
TIE bits. Please refer to [14.2. Fixed-cycle Timer Interrupt Function ] for the details.

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Page16
ETM50E-05
13.3.5. Function-related register 1 (1C[h]1E[h])
1) FSEL1, FSEL0 bit
A combination of the FSEL1 and FSEL0 bits are used to select the frequency to be output.
The choice is possible by a combining FSEL-bits and CE/FOE-pin, select the frequency of clock output
or inhibit the clock output. Please refer to [14.6. FOUT Function ] for the details.
2) USEL , UF, UIE bit
This bit is used to specify either "second update" or "minute update" as the update generation timing of
the time update interrupt function.
Please refer to [14.4. Update interrupt function] for the details.
3) TE, TF, TIE, TSEL2, TSEL1, TSEL0, TSTP,TBKON,TBKE bit
These bits are used to control operation of the fixed-cycle timer interrupt function.
4) WADA, AF, AIE bit
These bits are used to control operation of the alarm interrupt function.
5) TEST bit
These bits are the manufacturer's test bit. Always leave this bit value as "0"..
6) VLF bit
This flag bit indicates the retained status of clock operations or internal data. Its value changes from "0" to
"1" when data loss occurs, such as due to a supply voltage drop.
Please refer to [14.5. Frequency stop detection function] for the details.
7) STOP bit
This bit is to stop a timekeeping operation. In the case of “STOP bit = 1":
1) All the update of timekeeping and the calendar operation stops.
With it, an update interrupt event does not occur at an alarm interrupt and the time.
2) The part of the fixed-cycle timer interrupt function stops.
A count stops the source clock setting of the timer in case of "64Hz, 1Hz, 1min, 1h".
3) Note 3: The effect of STOP bit to FOUT functions.
When STOP = "1", 32768Hz and 1024Hz output is possible. But 1Hz output is disabled.
 4) Switchover function cannot work in order that the VDD voltage drop detection stops even if a main
power supply falls.
8) RSF bit
This flag bit holds the result of detecting the reset voltage.
13.3.6. Function-related register 2 (1F[h])
1) SMPTSEL1,SMPTSEL0 bit
Operation time setting of a voltage detector circuit for each power supply pin.
Please refer to [14.7. Battery Backup switchover function] for the details.
2) CHGEN bit
Setting of backup battery charge control (ON/OFF).
3) INIEN bit
Setting of a power switchover function (ON/OFF).
4) RSVSEL bit
Setting of voltage detection level of a VDD pin.
5) BFVSEL1,BFVSEL0 bit
Setting of the full charge detection voltage of a backup battery.
13.3.7. Digital offset register (30[h])
1) DTE bit Setting of a Digital offset function (ON/OFF).
Please refer to [14.10. Digital offset function ] for the details.
2) L7 L1 bit
Setting of a Digital offset value.