Freescale Semiconductor MCF5329 User manual

MCF5329 Reference Manual
Devices Supported:
MCF5327
MCF5328
MCF53281
MCF5329
Document Number: MCF5329RM
Rev. 3
12/2008

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MCF5329RM
Rev. 3
12/2008

Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
Crossbar Switch (XBS)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Enhanced Direct Memory Access (eDMA)
FlexBus
SDRAM Controller (SDRAMC)
Fast Ethernet Controller (FEC)
Universal Serial Bus Interface – Host Module
Universal Serial Bus Interface – On-The-Go Module
Liquid Crystal Display Controller (LCDC)
FlexCAN
Synchronous Serial Interface (SSI)
Real-Time Clock
Pulse-Width Modulation (PWM) Module
Watchdog Timer Module
Programmable Interrupt Timers (PIT0–PIT3)
DMA Timers (DTIM0–DTIM3)
UART Modules
I2C Interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Queued Serial Peripheral Interface (QSPI)
1
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Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Register Memory Map Quick Reference
Revision History
Debug Module
A
B

Revision History
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
Crossbar Switch (XBS)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Enhanced Direct Memory Access (eDMA)
FlexBus
SDRAM Controller (SDRAMC)
Fast Ethernet Controller (FEC)
Universal Serial Bus Interface – Host Module
Universal Serial Bus Interface – On-The-Go Module
Liquid Crystal Display Controller (LCDC)
FlexCAN
Synchronous Serial Interface (SSI)
Real-Time Clock
Pulse-Width Modulation (PWM) Module
Watchdog Timer Module
Programmable Interrupt Timers (PIT0–PIT3)
DMA Timers (DTIM0–DTIM3)
UART Modules
I2C Interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Queued Serial Peripheral Interface (QSPI)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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21
22
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25
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27
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29
30
31
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35
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37
B
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Register Memory Map Quick Reference
Debug Module
A

Freescale Semiconductor v
Contents
Paragraph
Number Title Page Number
About This Book
Audience ....................................................................................................................... xxix
Organization .................................................................................................................. xxix
Suggested Reading ....................................................................................................... xxxii
Hardware Specification ....................................................................................... xxxii
General Information ............................................................................................ xxxiii
ColdFire Documentation .................................................................................... xxxiii
Conventions ................................................................................................................ xxxiii
Register Figure Conventions .............................................................................. xxxiv
Acronyms and Abbreviations .......................................................................................xxxv
Terminology Conventions ........................................................................................... xxxvi
Chapter 1
Overview
1.1 MCF532xDevice Configurations.................................................................................................. 1-1
1.2 Block Diagram ............................................................................................................................... 1-2
1.3 Features .......................................................................................................................................... 1-3
1.3.1 V3 Core Overview...........................................................................................................1-8
1.3.2 Debug Module ................................................................................................................. 1-9
1.3.3 JTAG................................................................................................................................ 1-9
1.3.4 On-chip Memories...........................................................................................................1-9
1.3.5 LCD Controller.............................................................................................................. 1-10
1.3.6 Voice-over-IP (VoIP) System Solution......................................................................... 1-10
1.3.7 SDR/DDR SDRAM Controller ..................................................................................... 1-11
1.3.8 USB Host and OTG Controllers.................................................................................... 1-11
1.3.9 Synchronous Serial Interface (SSI)................................................................................ 1-12
1.3.10 Fast Ethernet Controller (FEC)...................................................................................... 1-12
1.3.11 Cryptography Accelerators............................................................................................ 1-12
1.3.12 FlexCAN........................................................................................................................ 1-13
1.3.13 UARTs........................................................................................................................... 1-13
1.3.14 I2C Bus...........................................................................................................................1-13
1.3.15 QSPI............................................................................................................................... 1-13
1.3.16 Pulse Width Modulation (PWM) Timer........................................................................ 1-13
1.3.17 Real Time Clock............................................................................................................ 1-13
1.3.18 DMA Timers (DTIM0-DTIM3) .................................................................................... 1-13
1.3.19 Software Watchdog Timer............................................................................................. 1-14
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Contents
Paragraph
Number Title Page Number
1.3.20 Periodic Interrupt Timers (PIT0–PIT3)......................................................................... 1-14
1.3.21 Clock Module and Phase Locked Loop (PLL).............................................................. 1-14
1.3.22 Interrupt Controllers ...................................................................................................... 1-14
1.3.23 DMA Controller............................................................................................................. 1-14
1.3.24 FlexBus External Interface ............................................................................................ 1-15
1.3.25 Reset Controller Module................................................................................................ 1-15
1.3.26 GPIO.............................................................................................................................. 1-15
1.4 Documentation............................................................................................................................. 1-16
Chapter 2
Signal Descriptions
2.1 Introduction.................................................................................................................................... 2-1
2.2 Signal Properties Summary............................................................................................................ 2-1
2.2.1 Internal Pull-up/Pull-downs Resistors ............................................................................. 2-8
2.3 Signal Primary Functions............................................................................................................... 2-9
2.3.1 Reset Signals.................................................................................................................... 2-9
2.3.2 PLL and Clock Signals .................................................................................................... 2-9
2.3.3 Mode Selection .............................................................................................................. 2-10
2.3.4 FlexBus Signals ............................................................................................................. 2-11
2.3.5 SDRAM Controller Signals........................................................................................... 2-12
2.3.6 External Interrupt Signals.............................................................................................. 2-12
2.3.7 DMA Signals ................................................................................................................. 2-12
2.3.8 LCD Controller Signals ................................................................................................. 2-13
2.3.9 Ethernet Module (FEC) Signals..................................................................................... 2-13
2.3.10 I2C I/O Signals .............................................................................................................. 2-14
2.3.11 FlexCAN Signals...........................................................................................................2-15
2.3.12 Queued Serial Peripheral Interface (QSPI).................................................................... 2-15
2.3.13 Synchronous Serial Interface (SSI) Signals................................................................... 2-15
2.3.14 Universal Serial Bus (USB) Signals.............................................................................. 2-16
2.3.15 Pulse Width Modulation (PWM) Module Signals......................................................... 2-16
2.3.16 UART Module Signals .................................................................................................. 2-17
2.3.17 DMA Timer Signals....................................................................................................... 2-17
2.3.18 Debug Support Signals .................................................................................................. 2-17
2.3.19 Test Signals.................................................................................................................... 2-19
2.3.20 Power and Ground Pins ................................................................................................. 2-19
2.4 External Boot Mode..................................................................................................................... 2-20
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Freescale Semiconductor vii
Contents
Paragraph
Number Title Page Number
Chapter 3
ColdFire Core
3.1 Introduction.................................................................................................................................... 3-1
3.1.1 Overview.......................................................................................................................... 3-1
3.2 Memory Map/Register Description................................................................................................ 3-4
3.2.1 Data Registers (D0–D7)................................................................................................... 3-6
3.2.2 Address Registers (A0–A6)............................................................................................. 3-6
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)................................................... 3-6
3.2.4 Condition Code Register (CCR)...................................................................................... 3-7
3.2.5 Program Counter (PC) ..................................................................................................... 3-8
3.2.6 Cache Control Register (CACR) ..................................................................................... 3-8
3.2.7 Access Control Registers (ACRn)................................................................................... 3-9
3.2.8 Vector Base Register (VBR)............................................................................................3-9
3.2.9 Status Register (SR)......................................................................................................... 3-9
3.2.10 Memory Base Address Register (RAMBAR) ............................................................... 3-10
3.3 Functional Description................................................................................................................. 3-10
3.3.1 Version 3 ColdFire Microarchitecture........................................................................... 3-10
3.3.2 Instruction Set Architecture (ISA_A+).......................................................................... 3-11
3.3.3 Exception Processing Overview.................................................................................... 3-12
3.3.4 Processor Exceptions..................................................................................................... 3-15
3.3.5 Instruction Execution Timing........................................................................................ 3-23
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1 Introduction.................................................................................................................................... 4-1
4.1.1 Overview.......................................................................................................................... 4-1
4.2 Memory Map/Register Definition.................................................................................................. 4-3
4.2.1 MAC Status Register (MACSR)...................................................................................... 4-3
4.2.2 Mask Register (MASK)................................................................................................... 4-5
4.2.3 Accumulator Registers (ACC0–3)................................................................................... 4-6
4.2.4 Accumulator Extension Registers (ACCext01, ACCext23)............................................ 4-7
4.3 Functional Description................................................................................................................... 4-8
4.3.1 Fractional Operation Mode............................................................................................ 4-10
4.3.2 EMAC Instruction Set Summary................................................................................... 4-12
4.3.3 EMAC Instruction Execution Times ............................................................................. 4-13
4.3.4 Data Representation....................................................................................................... 4-14
4.3.5 MAC Opcodes ............................................................................................................... 4-14
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Contents
Paragraph
Number Title Page Number
Chapter 5
Cache
5.1 Introduction.................................................................................................................................... 5-1
5.1.1 Overview.......................................................................................................................... 5-1
5.2 Memory Map/Register Definition.................................................................................................. 5-2
5.2.1 Cache Control Register (CACR) ..................................................................................... 5-2
5.2.2 Access Control Registers (ACR0–ACR1)....................................................................... 5-4
5.3 Functional Description................................................................................................................... 5-5
5.3.1 Cache Organization.......................................................................................................... 5-5
5.3.2 Cache Operation .............................................................................................................. 5-7
5.3.3 Caching Modes ..............................................................................................................5-10
5.3.4 Cache-Inhibited Accesses.............................................................................................. 5-11
5.3.5 Cache Protocol............................................................................................................... 5-11
5.3.6 Cache Coherency........................................................................................................... 5-13
5.3.7 Memory Accesses for Cache Maintenance.................................................................... 5-13
5.3.8 Cache Locking............................................................................................................... 5-15
5.3.9 Cache Management........................................................................................................ 5-16
5.3.10 Cache Operation Summary............................................................................................ 5-17
Chapter 6
Static RAM (SRAM)
6.1 Introduction.................................................................................................................................... 6-1
6.1.1 Overview.......................................................................................................................... 6-1
6.1.2 Features............................................................................................................................ 6-1
6.2 Memory Map/Register Description................................................................................................ 6-2
6.2.1 SRAM Base Address Register (RAMBAR).................................................................... 6-2
6.3 Initialization/Application Information ........................................................................................... 6-4
6.3.1 SRAM Initialization Code ............................................................................................... 6-4
6.3.2 Power Management ......................................................................................................... 6-5
Chapter 7
Clock Module
7.1 Introduction.................................................................................................................................... 7-1
7.1.1 Block Diagram................................................................................................................. 7-3
7.1.2 Features............................................................................................................................ 7-3
7.1.3 Modes of Operation .........................................................................................................7-3
7.2 Memory Map/Register Definition.................................................................................................. 7-5
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Contents
Paragraph
Number Title Page Number
7.2.1 PLL Output Divider Register (PODR) ............................................................................ 7-6
7.2.2 PLL Control Register (PCR)............................................................................................7-6
7.2.3 PLL Modulation Divider Register (PMDR).................................................................... 7-7
7.2.4 PLL Feedback Divider Register (PFDR)......................................................................... 7-8
7.3 Functional Description................................................................................................................... 7-8
7.3.1 PLL Dithered and Non-Dithered Operation .................................................................... 7-8
7.3.2 Dithering Waveform Definition....................................................................................... 7-9
7.3.3 PLL Frequency Multiplication Factor Select................................................................. 7-10
7.3.4 System Clock Modes ..................................................................................................... 7-11
7.3.5 Clock Operation During Reset....................................................................................... 7-11
Chapter 8
Power Management
8.1 Introduction.................................................................................................................................... 8-1
8.1.1 Features............................................................................................................................ 8-1
8.2 Memory Map/Register Definition.................................................................................................. 8-1
8.2.1 Wake-up Control Register ............................................................................................... 8-2
8.2.2 Peripheral Power Management Set Registers (PPMSR0 & PPMSR1) ........................... 8-3
8.2.3 Peripheral Power Management Clear Registers (PPMCR0 & PPMCR1)....................... 8-4
8.2.4 Peripheral Power Management Registers (PPMHR0, PPMHR1, & PPMLR0)..............8-4
8.2.5 Low-Power Control Register (LPCR) ............................................................................. 8-7
8.3 Functional Description................................................................................................................... 8-8
8.3.1 Peripheral Shut Down...................................................................................................... 8-8
8.3.2 Limp mode....................................................................................................................... 8-8
8.3.3 Low-Power Modes........................................................................................................... 8-9
8.3.4 Peripheral Behavior in Low-Power Modes ................................................................... 8-10
8.3.5 Summary of Peripheral State During Low-power Modes ............................................. 8-15
Chapter 9
Chip Configuration Module (CCM)
9.1 Introduction.................................................................................................................................... 9-1
9.1.1 Block Diagram................................................................................................................. 9-1
9.1.2 Features............................................................................................................................ 9-1
9.1.3 Modes of Operation .........................................................................................................9-1
9.2 External Signal Descriptions.......................................................................................................... 9-2
9.2.1 RCON .............................................................................................................................. 9-2
9.2.2 D[9:86:1] (Reset Configuration Override) ...................................................................... 9-2
9.3 Memory Map/Register Definition.................................................................................................. 9-2
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Contents
Paragraph
Number Title Page Number
9.3.1 Chip Configuration Register (CCR) ................................................................................ 9-3
9.3.2 Reset Configuration Register (RCON)............................................................................ 9-4
9.3.3 Chip Identification Register (CIR) .................................................................................. 9-4
9.3.4 Miscellaneous Control Register (MISCCR).................................................................... 9-5
9.3.5 Clock Divider Register .................................................................................................... 9-6
9.3.6 USB Host Controller Status Register (UHCSR).............................................................. 9-7
9.3.7 USB On-the-Go Controller Status Register (UOCSR).................................................... 9-7
9.4 Functional Description................................................................................................................... 9-9
9.4.1 Reset Configuration......................................................................................................... 9-9
9.4.2 PLL Mode Selection...................................................................................................... 9-11
9.4.3 Oscillator Mode Selection ............................................................................................. 9-11
9.4.4 Boot Device Selection ................................................................................................... 9-11
9.4.5 Output Pad Strength Configuration ............................................................................... 9-11
9.4.6 Chip Select Configuration ............................................................................................. 9-12
Chapter 10
Reset Controller Module
10.1 Introduction.................................................................................................................................. 10-1
10.1.1 Block Diagram............................................................................................................... 10-1
10.1.2 Features.......................................................................................................................... 10-1
10.2 External Signal Description ......................................................................................................... 10-2
10.2.1 RESET ........................................................................................................................... 10-2
10.2.2 RSTOUT........................................................................................................................ 10-2
10.3 Memory Map/Register Definition................................................................................................ 10-2
10.3.1 Reset Control Register (RCR) ....................................................................................... 10-2
10.3.2 Reset Status Register (RSR) .......................................................................................... 10-3
10.4 Functional Description................................................................................................................. 10-4
10.4.1 Reset Sources................................................................................................................. 10-4
10.4.2 Reset Control Flow........................................................................................................ 10-5
10.4.3 Concurrent Resets.......................................................................................................... 10-7
Chapter 11
System Control Module (SCM)
11.1 Introduction.................................................................................................................................. 11-1
11.1.1 Overview........................................................................................................................ 11-1
11.1.2 Features.......................................................................................................................... 11-1
11.2 Memory Map/Register Definition................................................................................................ 11-2
11.2.1 Master Privilege Register 0 (MPR0) ............................................................................. 11-3
MCF5329 Reference Manual, Rev 3